2006-10-12 21:04:14 +02:00
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---------- Begin Simulation Statistics ----------
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2010-05-14 05:45:59 +02:00
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host_inst_rate 153450 # Simulator instruction rate (inst/s)
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|
host_mem_usage 210984 # Number of bytes of host memory used
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|
host_seconds 548.58 # Real time elapsed on the host
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host_tick_rate 73456175 # Simulator tick rate (ticks/s)
|
2006-10-12 21:04:14 +02:00
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sim_freq 1000000000000 # Frequency of simulated ticks
|
2007-02-27 11:37:48 +01:00
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|
sim_insts 84179709 # Number of instructions simulated
|
2010-05-14 05:45:59 +02:00
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sim_seconds 0.040297 # Number of seconds simulated
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sim_ticks 40296654500 # Number of ticks simulated
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2009-03-07 23:30:55 +01:00
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|
|
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2010-05-14 05:45:59 +02:00
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|
system.cpu.BPredUnit.BTBHits 11897638 # Number of BTB hits
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system.cpu.BPredUnit.BTBLookups 15852760 # Number of BTB lookups
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system.cpu.BPredUnit.RASInCorrect 1209 # Number of incorrect RAS predictions.
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system.cpu.BPredUnit.condIncorrect 1887267 # Number of conditional branches incorrect
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system.cpu.BPredUnit.condPredicted 14560688 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 19536875 # Number of BP lookups
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system.cpu.BPredUnit.usedRAS 1737186 # Number of times the RAS was used to get a target.
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2007-02-27 11:37:48 +01:00
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|
system.cpu.commit.COM:branches 10240685 # Number of branches committed
|
2010-05-14 05:45:59 +02:00
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|
system.cpu.commit.COM:bw_lim_events 2907966 # number cycles where commit BW limit reached
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2006-10-12 21:04:14 +02:00
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|
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
2010-05-14 05:45:59 +02:00
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|
system.cpu.commit.COM:committed_per_cycle::samples 72454759 # Number of insts commited each cycle
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|
system.cpu.commit.COM:committed_per_cycle::mean 1.268420 # Number of insts commited each cycle
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|
system.cpu.commit.COM:committed_per_cycle::stdev 1.963909 # Number of insts commited each cycle
|
2009-07-07 00:49:48 +02:00
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system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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2010-05-14 05:45:59 +02:00
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system.cpu.commit.COM:committed_per_cycle::0-1 35335976 48.77% 48.77% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::1-2 18219580 25.15% 73.92% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::2-3 7350657 10.15% 84.06% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::3-4 3843959 5.31% 89.37% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::4-5 2026400 2.80% 92.16% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::5-6 1285963 1.77% 93.94% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::6-7 738665 1.02% 94.96% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::7-8 745593 1.03% 95.99% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::8 2907966 4.01% 100.00% # Number of insts commited each cycle
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2009-07-07 00:49:48 +02:00
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system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
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|
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|
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2010-05-14 05:45:59 +02:00
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|
|
system.cpu.commit.COM:committed_per_cycle::total 72454759 # Number of insts commited each cycle
|
2007-02-27 11:37:48 +01:00
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system.cpu.commit.COM:count 91903055 # Number of instructions committed
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system.cpu.commit.COM:loads 20034413 # Number of loads committed
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2006-10-12 21:04:14 +02:00
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system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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2007-02-27 11:37:48 +01:00
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|
system.cpu.commit.COM:refs 26537108 # Number of memory references committed
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2006-10-12 21:04:14 +02:00
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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2010-05-14 05:45:59 +02:00
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system.cpu.commit.branchMispredicts 1874087 # The number of times a branch was mispredicted
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2007-02-27 11:37:48 +01:00
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system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions
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2007-02-17 10:38:13 +01:00
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system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
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2010-05-14 05:45:59 +02:00
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system.cpu.commit.commitSquashedInsts 55786698 # The number of squashed insts skipped by commit
|
2007-02-27 11:37:48 +01:00
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system.cpu.committedInsts 84179709 # Number of Instructions Simulated
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system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated
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2010-05-14 05:45:59 +02:00
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system.cpu.cpi 0.957396 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.957396 # CPI: Total CPI of All Threads
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system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_hits 11 # number of LoadLockedReq hits
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system.cpu.dcache.ReadReq_accesses 23323647 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 30060.090703 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32045.634921 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 23322765 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 26513000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.000038 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 882 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 378 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 16151000 # number of ReadReq MSHR miss cycles
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2007-08-27 05:27:53 +02:00
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
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2010-05-14 05:45:59 +02:00
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system.cpu.dcache.ReadReq_mshr_misses 504 # number of ReadReq MSHR misses
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2008-03-18 04:07:22 +01:00
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system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
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2010-05-14 05:45:59 +02:00
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system.cpu.dcache.WriteReq_avg_miss_latency 35743.318729 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36228.400108 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 6492795 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 296955492 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.001278 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 8308 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 6456 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 67094997 # number of WriteReq MSHR miss cycles
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2008-02-26 08:20:40 +01:00
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.000285 # mshr miss rate for WriteReq accesses
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2010-05-14 05:45:59 +02:00
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system.cpu.dcache.WriteReq_mshr_misses 1852 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs 4187.125000 # average number of cycles each access was blocked
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2009-04-22 19:25:17 +02:00
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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2010-05-14 05:45:59 +02:00
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system.cpu.dcache.avg_refs 13310.644643 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 8 # number of cycles access was blocked
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2009-04-22 19:25:17 +02:00
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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2010-05-14 05:45:59 +02:00
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system.cpu.dcache.blocked_cycles::no_mshrs 33497 # number of cycles access was blocked
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2009-04-22 19:25:17 +02:00
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2006-10-12 21:04:14 +02:00
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2010-05-14 05:45:59 +02:00
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system.cpu.dcache.demand_accesses 29824750 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 35197.877258 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 35333.615025 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 29815560 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 323468492 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.000308 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 9190 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 6834 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 83245997 # number of demand (read+write) MSHR miss cycles
|
2007-08-13 01:43:55 +02:00
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system.cpu.dcache.demand_mshr_miss_rate 0.000079 # mshr miss rate for demand accesses
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2010-05-14 05:45:59 +02:00
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system.cpu.dcache.demand_mshr_misses 2356 # number of demand (read+write) MSHR misses
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2006-10-12 21:04:14 +02:00
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2010-05-14 05:45:59 +02:00
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system.cpu.dcache.occ_%::0 0.356016 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::0 1458.239906 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses 29824750 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 35197.877258 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 35333.615025 # average overall mshr miss latency
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2009-04-22 19:25:17 +02:00
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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2010-05-14 05:45:59 +02:00
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system.cpu.dcache.overall_hits 29815560 # number of overall hits
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system.cpu.dcache.overall_miss_latency 323468492 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.000308 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 9190 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 6834 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 83245997 # number of overall MSHR miss cycles
|
2007-08-13 01:43:55 +02:00
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system.cpu.dcache.overall_mshr_miss_rate 0.000079 # mshr miss rate for overall accesses
|
2010-05-14 05:45:59 +02:00
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system.cpu.dcache.overall_mshr_misses 2356 # number of overall MSHR misses
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2006-10-12 21:04:14 +02:00
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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2010-05-14 05:45:59 +02:00
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system.cpu.dcache.replacements 160 # number of replacements
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2008-08-04 00:13:29 +02:00
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system.cpu.dcache.sampled_refs 2240 # Sample count of references to valid blocks.
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2006-10-12 21:04:14 +02:00
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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2010-05-14 05:45:59 +02:00
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system.cpu.dcache.tagsinuse 1458.239906 # Cycle average of tags in use
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system.cpu.dcache.total_refs 29815844 # Total number of references to valid blocks.
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2006-10-12 21:04:14 +02:00
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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2010-05-14 05:45:59 +02:00
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system.cpu.dcache.writebacks 106 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 3560307 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 13329 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 3136527 # Number of times decode resolved a branch
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|
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|
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system.cpu.decode.DECODE:DecodedInsts 162153476 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 39273061 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 29418237 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 8029960 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 48947 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 203154 # Number of cycles decode is unblocking
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system.cpu.dtb.data_accesses 31794123 # DTB accesses
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2009-04-09 07:21:30 +02:00
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system.cpu.dtb.data_acv 0 # DTB access violations
|
2010-05-14 05:45:59 +02:00
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system.cpu.dtb.data_hits 31394253 # DTB hits
|
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system.cpu.dtb.data_misses 399870 # DTB misses
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2009-04-09 07:21:30 +02:00
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
|
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
|
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.dtb.read_accesses 24584547 # DTB read accesses
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.dtb.read_hits 24185700 # DTB read hits
|
|
|
|
|
system.cpu.dtb.read_misses 398847 # DTB read misses
|
|
|
|
|
system.cpu.dtb.write_accesses 7209576 # DTB write accesses
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.dtb.write_hits 7208553 # DTB write hits
|
|
|
|
|
system.cpu.dtb.write_misses 1023 # DTB write misses
|
|
|
|
|
system.cpu.fetch.Branches 19536875 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu.fetch.CacheLines 19049745 # Number of cache lines fetched
|
|
|
|
|
system.cpu.fetch.Cycles 49533111 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu.fetch.IcacheSquashes 485697 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu.fetch.Insts 167120080 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu.fetch.SquashCycles 2034068 # Number of cycles fetch has spent squashing
|
|
|
|
|
system.cpu.fetch.branchRate 0.242413 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu.fetch.icacheStallCycles 19049745 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu.fetch.predictedBranches 13634824 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu.fetch.rate 2.073622 # Number of inst fetches per cycle
|
|
|
|
|
system.cpu.fetch.rateDist::samples 80484719 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::mean 2.076420 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::stdev 3.094224 # Number of instructions fetched each cycle (Total)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.fetch.rateDist::0-1 50001427 62.13% 62.13% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::1-2 3132178 3.89% 66.02% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::2-3 1884597 2.34% 68.36% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::3-4 3228306 4.01% 72.37% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::4-5 4370184 5.43% 77.80% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::5-6 1507606 1.87% 79.67% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::6-7 1854945 2.30% 81.98% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::7-8 1658454 2.06% 84.04% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::8 12847022 15.96% 100.00% # Number of instructions fetched each cycle (Total)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.fetch.rateDist::total 80484719 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 19049745 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 15752.064632 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11876.097465 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_hits 19038605 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 175478000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000585 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_misses 11140 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 1003 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 120388000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000532 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 10137 # number of ReadReq MSHR misses
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.avg_refs 1878.130117 # Average number of references to valid blocks.
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.demand_accesses 19049745 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 15752.064632 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 11876.097465 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_hits 19038605 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_miss_latency 175478000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.000585 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_misses 11140 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 1003 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 120388000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000532 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 10137 # number of demand (read+write) MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.occ_%::0 0.755796 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.occ_blocks::0 1547.870707 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.overall_accesses 19049745 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 15752.064632 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 11876.097465 # average overall mshr miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.overall_hits 19038605 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_miss_latency 175478000 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.000585 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_misses 11140 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 1003 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 120388000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000532 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 10137 # number of overall MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.replacements 8223 # number of replacements
|
|
|
|
|
system.cpu.icache.sampled_refs 10137 # Sample count of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.tagsinuse 1547.870707 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 19038605 # Total number of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.idleCycles 108591 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.iew.EXEC:branches 12897175 # Number of branches executed
|
|
|
|
|
system.cpu.iew.EXEC:nop 12739019 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.EXEC:rate 1.262855 # Inst execution rate
|
|
|
|
|
system.cpu.iew.EXEC:refs 31847616 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.EXEC:stores 7211217 # Number of stores executed
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iew.WB:consumers 91218394 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.WB:count 99932054 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.WB:fanout 0.721984 # average fanout of values written-back
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iew.WB:producers 65858228 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.WB:rate 1.239955 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.WB:sent 100793715 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.branchMispredicts 2037312 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewBlockCycles 220727 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 33778811 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 434 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 1499848 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 10610374 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 147688610 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 24636399 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 2142931 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 101777656 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 90810 # Number of times the IQ has become full, causing a stall
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iew.iewLSQFullEvents 223 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewSquashCycles 8029960 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 123733 # Number of cycles IEW is unblocking
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu.iew.lsq.thread.0.forwLoads 852201 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 2584 # Number of memory responses ignored because the instruction is squashed
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 270101 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 9831 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 13744398 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedStores 4107679 # Number of stores squashed
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 270101 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 440641 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 1596671 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.ipc 1.044500 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.044500 # IPC: Total IPC of All Threads
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntAlu 64410892 61.98% 61.98% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntMult 474451 0.46% 62.44% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.44% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2784957 2.68% 65.12% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 114528 0.11% 65.23% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2385482 2.30% 67.52% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatMult 305123 0.29% 67.82% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 755228 0.73% 68.54% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 324 0.00% 68.54% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::MemRead 25350766 24.39% 92.94% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::MemWrite 7338829 7.06% 100.00% # Type of FU issued
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::total 103920587 # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 1852625 # FU busy when requested
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.017827 # FU busy rate (busy events/executed inst)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full::IntAlu 210356 11.35% 11.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 11.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 11.35% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatAdd 363 0.02% 11.37% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.37% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatCvt 3342 0.18% 11.55% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatMult 2324 0.13% 11.68% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatDiv 819264 44.22% 55.90% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 55.90% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::MemRead 748090 40.38% 96.28% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::MemWrite 68886 3.72% 100.00% # attempts to use FU when none available
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::samples 80484719 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.291184 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.543424 # Number of insts issued each cycle
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::0-1 34420666 42.77% 42.77% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::1-2 18632497 23.15% 65.92% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::2-3 11734091 14.58% 80.50% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::3-4 6720766 8.35% 88.85% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::4-5 5079668 6.31% 95.16% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::5-6 2378591 2.96% 98.11% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::6-7 1227784 1.53% 99.64% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::7-8 245969 0.31% 99.94% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::8 44687 0.06% 100.00% # Number of insts issued each cycle
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::total 80484719 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:rate 1.289444 # Inst issue rate
|
|
|
|
|
system.cpu.iq.iqInstsAdded 134949157 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqInstsIssued 103920587 # Number of instructions issued
|
|
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 434 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu.iq.iqSquashedInstsExamined 50119883 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 297027 # Number of squashed instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 46887079 # Number of squashed operands that are examined and possibly removed from graph
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
|
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
|
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
|
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.itb.fetch_accesses 19049819 # ITB accesses
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.itb.fetch_hits 19049745 # ITB hits
|
|
|
|
|
system.cpu.itb.fetch_misses 74 # ITB misses
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_accesses 1736 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34694.700461 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31523.329493 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 60230000 # number of ReadExReq miss cycles
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_misses 1736 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 54724500 # number of ReadExReq MSHR miss cycles
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 1736 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 10641 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34281.074697 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31079.421317 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 7254 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 116110000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.318297 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 3387 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 105266000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.318297 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 3387 # number of ReadReq MSHR misses
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_accesses 123 # number of UpgradeReq accesses(hits+misses)
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34414.634146 # average UpgradeReq miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31256.097561 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_latency 4233000 # number of UpgradeReq miss cycles
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_misses 123 # number of UpgradeReq misses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3844500 # number of UpgradeReq MSHR miss cycles
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 123 # number of UpgradeReq MSHR misses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.Writeback_accesses 106 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 106 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 4333.333333 # average number of cycles each access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.avg_refs 2.165420 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.blocked::no_mshrs 3 # number of cycles access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 13000 # number of cycles access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.demand_accesses 12377 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34421.237556 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31229.845793 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_hits 7254 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 176340000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.413913 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_misses 5123 # number of demand (read+write) misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 159990500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.413913 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 5123 # number of demand (read+write) MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.occ_%::0 0.068298 # Average percentage of cache occupancy
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu.l2cache.occ_%::1 0.000414 # Average percentage of cache occupancy
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.occ_blocks::0 2237.998108 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 13.556876 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.overall_accesses 12377 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34421.237556 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31229.845793 # average overall mshr miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.overall_hits 7254 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 176340000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.413913 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_misses 5123 # number of overall misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 159990500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.413913 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 5123 # number of overall MSHR misses
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.sampled_refs 3343 # Sample count of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 2251.554984 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 7239 # Total number of references to valid blocks.
|
2006-10-12 21:04:14 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.memDep0.conflictingLoads 17229574 # Number of conflicting loads.
|
|
|
|
|
system.cpu.memDep0.conflictingStores 5033996 # Number of conflicting stores.
|
|
|
|
|
system.cpu.memDep0.insertedLoads 33778811 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.insertedStores 10610374 # Number of stores inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.numCycles 80593310 # number of cpu cycles simulated
|
|
|
|
|
system.cpu.rename.RENAME:BlockCycles 1589033 # Number of cycles rename is blocking
|
2007-02-27 11:37:48 +01:00
|
|
|
system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.rename.RENAME:IQFullEvents 926186 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.RENAME:IdleCycles 40466713 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.RENAME:LSQFullEvents 962025 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu.rename.RENAME:RenameLookups 202340521 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.RENAME:RenamedInsts 157033543 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.RENAME:RenamedOperands 115331786 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RENAME:RunCycles 28409670 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.RENAME:SquashCycles 8029960 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.RENAME:UnblockCycles 1983994 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RENAME:UndoneMaps 46904425 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.RENAME:serializeStallCycles 5349 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RENAME:serializingInsts 467 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.RENAME:skidInsts 4530466 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.rename.RENAME:tempSerializingInsts 456 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu.timesIdled 2422 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
2007-02-17 10:38:13 +01:00
|
|
|
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
|
2006-10-12 21:04:14 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
