2011-02-08 04:23:11 +01:00
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---------- Begin Simulation Statistics ----------
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2012-07-27 22:08:05 +02:00
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sim_seconds 2.332810 # Number of seconds simulated
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sim_ticks 2332810264000 # Number of ticks simulated
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final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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2011-02-08 04:23:11 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2012-09-25 18:49:41 +02:00
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host_inst_rate 1681370 # Simulator instruction rate (inst/s)
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host_op_rate 2162138 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 64929680145 # Simulator tick rate (ticks/s)
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host_mem_usage 380112 # Number of bytes of host memory used
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host_seconds 35.93 # Real time elapsed on the host
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2012-07-27 22:08:05 +02:00
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sim_insts 60408639 # Number of instructions simulated
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sim_ops 77681819 # Number of ops (including micro ops) simulated
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2012-06-05 07:23:16 +02:00
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system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory
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2012-06-29 17:19:03 +02:00
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system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
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2012-07-27 22:08:05 +02:00
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system.physmem.bytes_read::cpu.inst 705120 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 9071632 # Number of bytes read from this memory
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system.physmem.bytes_read::total 121450608 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 705120 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 3703232 # Number of bytes written to this memory
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2012-06-05 07:23:16 +02:00
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system.physmem.bytes_written::cpu.data 3015816 # Number of bytes written to this memory
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2012-07-27 22:08:05 +02:00
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system.physmem.bytes_written::total 6719048 # Number of bytes written to this memory
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2012-06-05 07:23:16 +02:00
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system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory
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2012-06-29 17:19:03 +02:00
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system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
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2012-07-27 22:08:05 +02:00
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system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 141778 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 14118174 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 57863 # Number of write requests responded to by this memory
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2012-06-05 07:23:16 +02:00
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system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory
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2012-07-27 22:08:05 +02:00
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system.physmem.num_writes::total 811817 # Number of write requests responded to by this memory
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system.physmem.bw_read::realview.clcd 47870736 # Total read bandwidth from this memory (bytes/s)
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2012-06-29 17:19:03 +02:00
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system.physmem.bw_read::cpu.dtb.walker 137 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.itb.walker 82 # Total read bandwidth from this memory (bytes/s)
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2012-07-27 22:08:05 +02:00
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system.physmem.bw_read::cpu.inst 302262 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 3888714 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 52061931 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 302262 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 302262 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 1587455 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu.data 1292782 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 2880238 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 1587455 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.clcd 47870736 # Total bandwidth to/from this memory (bytes/s)
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2012-06-29 17:19:03 +02:00
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system.physmem.bw_total::cpu.dtb.walker 137 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.itb.walker 82 # Total bandwidth to/from this memory (bytes/s)
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2012-07-27 22:08:05 +02:00
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system.physmem.bw_total::cpu.inst 302262 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 5181496 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 54942169 # Total bandwidth to/from this memory (bytes/s)
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2012-06-05 07:23:16 +02:00
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system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
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system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
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system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
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system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
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system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
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system.realview.nvmem.bw_read::cpu.inst 9 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::cpu.inst 9 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
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2012-10-15 14:08:06 +02:00
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system.cpu.l2cache.replacements 62243 # number of replacements
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system.cpu.l2cache.tagsinuse 50007.272909 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 1669922 # Total number of references to valid blocks.
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system.cpu.l2cache.sampled_refs 127628 # Sample count of references to valid blocks.
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system.cpu.l2cache.avg_refs 13.084292 # Average number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.occ_blocks::writebacks 36899.582990 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.dtb.walker 2.960148 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.inst 7014.720482 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.data 6089.015357 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_percent::writebacks 0.563043 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::cpu.inst 0.107036 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::cpu.data 0.092911 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::total 0.763050 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7507 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3129 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::cpu.inst 838871 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::cpu.data 366771 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::total 1216278 # number of ReadReq hits
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system.cpu.l2cache.Writeback_hits::writebacks 592643 # number of Writeback hits
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system.cpu.l2cache.Writeback_hits::total 592643 # number of Writeback hits
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system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
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system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
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system.cpu.l2cache.ReadExReq_hits::cpu.data 113739 # number of ReadExReq hits
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system.cpu.l2cache.ReadExReq_hits::total 113739 # number of ReadExReq hits
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system.cpu.l2cache.demand_hits::cpu.dtb.walker 7507 # number of demand (read+write) hits
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system.cpu.l2cache.demand_hits::cpu.itb.walker 3129 # number of demand (read+write) hits
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system.cpu.l2cache.demand_hits::cpu.inst 838871 # number of demand (read+write) hits
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system.cpu.l2cache.demand_hits::cpu.data 480510 # number of demand (read+write) hits
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system.cpu.l2cache.demand_hits::total 1330017 # number of demand (read+write) hits
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system.cpu.l2cache.overall_hits::cpu.dtb.walker 7507 # number of overall hits
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system.cpu.l2cache.overall_hits::cpu.itb.walker 3129 # number of overall hits
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system.cpu.l2cache.overall_hits::cpu.inst 838871 # number of overall hits
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system.cpu.l2cache.overall_hits::cpu.data 480510 # number of overall hits
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system.cpu.l2cache.overall_hits::total 1330017 # number of overall hits
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system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_misses::cpu.inst 10604 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_misses::cpu.data 9871 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_misses::total 20483 # number of ReadReq misses
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system.cpu.l2cache.UpgradeReq_misses::cpu.data 2919 # number of UpgradeReq misses
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system.cpu.l2cache.UpgradeReq_misses::total 2919 # number of UpgradeReq misses
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system.cpu.l2cache.ReadExReq_misses::cpu.data 133468 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_misses::total 133468 # number of ReadExReq misses
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system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses
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system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses
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system.cpu.l2cache.demand_misses::cpu.inst 10604 # number of demand (read+write) misses
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system.cpu.l2cache.demand_misses::cpu.data 143339 # number of demand (read+write) misses
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system.cpu.l2cache.demand_misses::total 153951 # number of demand (read+write) misses
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system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses
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system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses
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system.cpu.l2cache.overall_misses::cpu.inst 10604 # number of overall misses
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system.cpu.l2cache.overall_misses::cpu.data 143339 # number of overall misses
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system.cpu.l2cache.overall_misses::total 153951 # number of overall misses
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system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7512 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3132 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_accesses::cpu.inst 849475 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_accesses::cpu.data 376642 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_accesses::total 1236761 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.Writeback_accesses::writebacks 592643 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.Writeback_accesses::total 592643 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2945 # number of UpgradeReq accesses(hits+misses)
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system.cpu.l2cache.UpgradeReq_accesses::total 2945 # number of UpgradeReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_accesses::cpu.data 247207 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_accesses::total 247207 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7512 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_accesses::cpu.itb.walker 3132 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_accesses::cpu.inst 849475 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_accesses::cpu.data 623849 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_accesses::total 1483968 # number of demand (read+write) accesses
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system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7512 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_accesses::cpu.itb.walker 3132 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_accesses::cpu.inst 849475 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_accesses::cpu.data 623849 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_accesses::total 1483968 # number of overall (read+write) accesses
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system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000666 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000958 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012483 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026208 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_miss_rate::total 0.016562 # miss rate for ReadReq accesses
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system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991171 # miss rate for UpgradeReq accesses
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|
|
|
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system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991171 # miss rate for UpgradeReq accesses
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|
|
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system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.539904 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_miss_rate::total 0.539904 # miss rate for ReadExReq accesses
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|
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system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000666 # miss rate for demand accesses
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system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000958 # miss rate for demand accesses
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|
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system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012483 # miss rate for demand accesses
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|
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system.cpu.l2cache.demand_miss_rate::cpu.data 0.229766 # miss rate for demand accesses
|
|
|
|
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system.cpu.l2cache.demand_miss_rate::total 0.103743 # miss rate for demand accesses
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|
|
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system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000666 # miss rate for overall accesses
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|
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system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000958 # miss rate for overall accesses
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|
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system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012483 # miss rate for overall accesses
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|
|
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system.cpu.l2cache.overall_miss_rate::cpu.data 0.229766 # miss rate for overall accesses
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|
|
|
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system.cpu.l2cache.overall_miss_rate::total 0.103743 # miss rate for overall accesses
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|
|
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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|
|
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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|
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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|
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system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.writebacks::writebacks 57863 # number of writebacks
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system.cpu.l2cache.writebacks::total 57863 # number of writebacks
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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2011-08-19 22:08:09 +02:00
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|
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system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
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|
|
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system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
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system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
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system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
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system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
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system.cf0.dma_write_txs 0 # Number of DMA write transactions.
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
|
2012-07-27 22:08:05 +02:00
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|
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system.cpu.dtb.read_hits 14971214 # DTB read hits
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system.cpu.dtb.read_misses 7294 # DTB read misses
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system.cpu.dtb.write_hits 11217004 # DTB write hits
|
2012-05-11 01:04:29 +02:00
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system.cpu.dtb.write_misses 2181 # DTB write misses
|
2011-02-08 04:23:11 +01:00
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|
|
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.dtb.flush_entries 3496 # Number of entries that have been flushed from TLB
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
2012-05-11 01:04:29 +02:00
|
|
|
system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
|
system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.dtb.read_accesses 14978508 # DTB read accesses
|
|
|
|
|
system.cpu.dtb.write_accesses 11219185 # DTB write accesses
|
2011-02-08 04:23:11 +01:00
|
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.dtb.hits 26188218 # DTB hits
|
|
|
|
|
system.cpu.dtb.misses 9475 # DTB misses
|
|
|
|
|
system.cpu.dtb.accesses 26197693 # DTB accesses
|
|
|
|
|
system.cpu.itb.inst_hits 61431840 # ITB inst hits
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.itb.inst_misses 4471 # ITB inst misses
|
|
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
|
|
|
system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB
|
|
|
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.itb.inst_accesses 61436311 # ITB inst accesses
|
|
|
|
|
system.cpu.itb.hits 61431840 # DTB hits
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.itb.misses 4471 # DTB misses
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.itb.accesses 61436311 # DTB accesses
|
|
|
|
|
system.cpu.numCycles 4665543516 # number of cpu cycles simulated
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.committedInsts 60408639 # Number of instructions committed
|
|
|
|
|
system.cpu.committedOps 77681819 # Number of ops (including micro ops) committed
|
|
|
|
|
system.cpu.num_int_alu_accesses 68795605 # Number of integer alu accesses
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.num_func_calls 2136008 # number of times a function call or return occured
|
2012-09-25 18:49:41 +02:00
|
|
|
system.cpu.num_conditional_control_insts 7942113 # number of instructions that are conditional controls
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.num_int_insts 68795605 # number of integer instructions
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.num_fp_insts 10269 # number of float instructions
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.num_int_register_reads 349324274 # number of times the integer registers were read
|
|
|
|
|
system.cpu.num_int_register_writes 74103608 # number of times the integer registers were written
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
|
|
|
|
|
system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.num_mem_refs 27361637 # number of memory refs
|
|
|
|
|
system.cpu.num_load_insts 15639527 # Number of load instructions
|
|
|
|
|
system.cpu.num_store_insts 11722110 # Number of store instructions
|
|
|
|
|
system.cpu.num_idle_cycles 4586746360.692756 # Number of idle cycles
|
|
|
|
|
system.cpu.num_busy_cycles 78797155.307244 # Number of busy cycles
|
|
|
|
|
system.cpu.not_idle_fraction 0.016889 # Percentage of non-idle cycles
|
|
|
|
|
system.cpu.idle_fraction 0.983111 # Percentage of idle cycles
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
2012-05-11 01:04:29 +02:00
|
|
|
system.cpu.kern.inst.quiesce 82795 # number of quiesce instructions executed
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.icache.replacements 850590 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 511.678593 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 60583498 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 851102 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 71.182418 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.occ_blocks::cpu.inst 511.678593 # Average occupied blocks per requestor
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.icache.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.occ_percent::total 0.999372 # Average percentage of cache occupancy
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 60583498 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_hits::total 60583498 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits::cpu.inst 60583498 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_hits::total 60583498 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits::cpu.inst 60583498 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_hits::total 60583498 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 851102 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::total 851102 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses::cpu.inst 851102 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_misses::total 851102 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses::cpu.inst 851102 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_misses::total 851102 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 61434600 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::total 61434600 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses::cpu.inst 61434600 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_accesses::total 61434600 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::cpu.inst 61434600 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::total 61434600 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013854 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.013854 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.013854 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::total 0.013854 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.013854 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::total 0.013854 # miss rate for overall accesses
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.dcache.replacements 623337 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 511.997031 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 23628343 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 623849 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 37.875100 # Average number of references to valid blocks.
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit.
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.dcache.occ_blocks::cpu.data 511.997031 # Average occupied blocks per requestor
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 13180066 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::total 13180066 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 9962072 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::total 9962072 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 236039 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits::total 236039 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 247221 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits::total 247221 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits::cpu.data 23142138 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_hits::total 23142138 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits::cpu.data 23142138 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_hits::total 23142138 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 365459 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::total 365459 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 250152 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::total 250152 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 11183 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_misses::total 11183 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses::cpu.data 615611 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_misses::total 615611 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses::cpu.data 615611 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_misses::total 615611 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 13545525 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::total 13545525 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 10212224 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::total 10212224 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247222 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 247222 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 247221 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses::total 247221 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 23757749 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 23757749 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 23757749 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 23757749 # number of overall (read+write) accesses
|
2012-05-11 01:04:29 +02:00
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026980 # miss rate for ReadReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.026980 # miss rate for ReadReq accesses
|
2012-05-11 01:04:29 +02:00
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045235 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045235 # miss rate for LoadLockedReq accesses
|
2012-05-11 01:04:29 +02:00
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.025912 # miss rate for demand accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses
|
2012-05-11 01:04:29 +02:00
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.025912 # miss rate for overall accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.dcache.overall_miss_rate::total 0.025912 # miss rate for overall accesses
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu.dcache.writebacks::writebacks 592643 # number of writebacks
|
|
|
|
|
system.cpu.dcache.writebacks::total 592643 # number of writebacks
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.iocache.replacements 0 # number of replacements
|
|
|
|
|
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
|
|
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
|
|
|
|
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
2012-05-09 20:52:14 +02:00
|
|
|
system.iocache.avg_refs nan # Average number of references to valid blocks.
|
2011-08-19 22:08:09 +02:00
|
|
|
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-08-19 22:08:09 +02:00
|
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-02-08 04:23:11 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
