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gem5/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt

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Added SPARC o3 insttest regression. --HG-- extra : convert_revision : b008b4bda60ced329df9b700ff9b0a978e2d3b19
2007-04-09 09:59:56 +02:00
---------- Begin Simulation Statistics ----------
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
sim_seconds 0.000018 # Number of seconds simulated
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
sim_ticks 18114000 # Number of ticks simulated
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
final_tick 18114000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
Added SPARC o3 insttest regression. --HG-- extra : convert_revision : b008b4bda60ced329df9b700ff9b0a978e2d3b19
2007-04-09 09:59:56 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
host_inst_rate 74785 # Simulator instruction rate (inst/s)
host_tick_rate 93746300 # Simulator tick rate (ticks/s)
host_mem_usage 213808 # Number of bytes of host memory used
host_seconds 0.19 # Real time elapsed on the host
regress: update regressions for tty emulation fix.
2008-07-25 01:31:54 +02:00
sim_insts 14449 # Number of instructions simulated
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.physmem.bytes_read 30464 # Number of bytes read from this memory
system.physmem.bytes_inst_read 21120 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.physmem.num_reads 476 # Number of read requests responded to by this memory
system.physmem.num_writes 0 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 1681793088 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 1165948990 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total 1681793088 # Total bandwidth to/from this memory (bytes/s)
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.workload.num_syscalls 18 # Number of system calls
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.numCycles 36229 # number of cpu cycles simulated
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.BPredUnit.lookups 5641 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 3757 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 847 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 5015 # Number of BTB lookups
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.BPredUnit.BTBHits 2638 # Number of BTB hits
tests: update tests because of changes in stat names and in the stats package
2009-03-07 23:30:55 +01:00
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.BPredUnit.usedRAS 357 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 168 # Number of incorrect RAS predictions.
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.fetch.icacheStallCycles 10704 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 25822 # Number of instructions fetch has processed
system.cpu.fetch.Branches 5641 # Number of branches that fetch encountered
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.fetch.predictedBranches 2995 # Number of branches that fetch has predicted taken
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.fetch.Cycles 8176 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 2307 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 6717 # Number of cycles fetch has spent blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 641 # Number of stall cycles due to pending traps
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.fetch.CacheLines 4608 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 368 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 27606 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.935376 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.035144 # Number of instructions fetched each cycle (Total)
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.fetch.rateDist::0 19430 70.38% 70.38% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 4056 14.69% 85.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 538 1.95% 87.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 472 1.71% 88.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 725 2.63% 91.36% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 639 2.31% 93.68% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 274 0.99% 94.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 241 0.87% 95.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 1231 4.46% 100.00% # Number of instructions fetched each cycle (Total)
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.fetch.rateDist::total 27606 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.155704 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.712744 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 11125 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 7403 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 7524 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 190 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1364 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 24270 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 1364 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 11622 # Number of cycles rename is idle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.rename.BlockCycles 225 # Number of cycles rename is blocking
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.rename.serializeStallCycles 6687 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 7253 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 455 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 22509 # Number of instructions processed by rename
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 135 # Number of times rename has blocked due to LSQ full
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.rename.RenamedOperands 20189 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 41765 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 41765 # Number of integer rename lookups
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.rename.CommittedMaps 13832 # Number of HB maps that are committed
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.rename.UndoneMaps 6357 # Number of HB maps that are undone due to squashing
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.rename.serializingInsts 639 # count of serializing insts renamed
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.rename.tempSerializingInsts 633 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 2443 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 3114 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1976 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.iq.iqInstsAdded 19328 # Number of instructions added to the IQ (excludes non-spec)
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.iqNonSpecInstsAdded 615 # Number of non-speculative instructions added to the IQ
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.iq.iqInstsIssued 18581 # Number of instructions issued
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.iqSquashedInstsIssued 81 # Number of squashed instructions issued
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.iq.iqSquashedInstsExamined 4856 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 3975 # Number of squashed operands that are examined and possibly removed from graph
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.iqSquashedNonSpecRemoved 140 # Number of squashed non-spec instructions that were removed
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.iq.issued_per_cycle::samples 27606 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.673078 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.254278 # Number of insts issued each cycle
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.iq.issued_per_cycle::0 19117 69.25% 69.25% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 3446 12.48% 81.73% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 2219 8.04% 89.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 1536 5.56% 95.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 657 2.38% 97.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 384 1.39% 99.11% # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.issued_per_cycle::6 197 0.71% 99.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 41 0.15% 99.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 9 0.03% 100.00% # Number of insts issued each cycle
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.iq.issued_per_cycle::total 27606 # Number of insts issued each cycle
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.fu_full::IntAlu 35 25.18% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 25.18% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 26 18.71% 43.88% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 78 56.12% 100.00% # attempts to use FU when none available
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.iq.FU_type_0::IntAlu 13779 74.16% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.16% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 2952 15.89% 90.04% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 1850 9.96% 100.00% # Type of FU issued
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.iq.FU_type_0::total 18581 # Type of FU issued
system.cpu.iq.rate 0.512876 # Inst issue rate
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.fu_busy_cnt 139 # FU busy when requested
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.iq.fu_busy_rate 0.007481 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 64988 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 24825 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 17429 # Number of integer instruction queue wakeup accesses
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.iq.int_alu_accesses 18720 # Number of integer alu accesses
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.iew.lsq.thread0.forwLoads 26 # Number of loads that had data forwarded from stores
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 888 # Number of loads squashed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
O3: Update stats for new ordering fix.
2011-09-13 18:58:09 +02:00
system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.iew.lsq.thread0.squashedStores 528 # Number of stores squashed
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.iew.iewSquashCycles 1364 # Number of cycles IEW is squashing
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.iewBlockCycles 96 # Number of cycles IEW is blocking
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.iew.iewDispatchedInsts 21045 # Number of instructions dispatched to IQ
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.iewDispSquashedInsts 247 # Number of squashed instructions skipped by dispatch
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.iew.iewDispLoadInsts 3114 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1976 # Number of dispatched store instructions
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.iewDispNonSpecInsts 615 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
O3: Update stats for new ordering fix.
2011-09-13 18:58:09 +02:00
system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.predictedTakenIncorrect 371 # Number of branches that were predicted taken incorrectly
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.iew.predictedNotTakenIncorrect 573 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 944 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 17855 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 2862 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 726 # Number of squashed instructions skipped in execute
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.iew.exec_nop 1102 # number of nop insts executed
system.cpu.iew.exec_refs 4620 # number of memory reference insts executed
system.cpu.iew.exec_branches 3963 # Number of branches executed
system.cpu.iew.exec_stores 1758 # Number of stores executed
system.cpu.iew.exec_rate 0.492837 # Inst execution rate
system.cpu.iew.wb_sent 17592 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 17429 # cumulative count of insts written-back
system.cpu.iew.wb_producers 8123 # num instructions producing a value
system.cpu.iew.wb_consumers 9726 # num instructions consuming a value
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.iew.wb_rate 0.481079 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.835184 # average fanout of values written-back
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
regress: update regressions for tty emulation fix.
2008-07-25 01:31:54 +02:00
system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.commit.commitSquashedInsts 5794 # The number of squashed insts skipped by commit
regress: update regressions for tty emulation fix.
2008-07-25 01:31:54 +02:00
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.commit.branchMispredicts 847 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 26259 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.577897 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.280480 # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.commit.committed_per_cycle::0 19069 72.62% 72.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 3994 15.21% 87.83% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 1208 4.60% 92.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 790 3.01% 95.44% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 369 1.41% 96.84% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 322 1.23% 98.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 345 1.31% 99.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 57 0.22% 99.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 105 0.40% 100.00% # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.commit.committed_per_cycle::total 26259 # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.count 15175 # Number of instructions committed
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 3674 # Number of memory references committed
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.loads 2226 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.commit.branches 3359 # Number of branches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 12186 # Number of committed integer instructions.
system.cpu.commit.function_calls 187 # Number of function calls committed.
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.commit.bw_lim_events 105 # number cycles where commit BW limit reached
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.rob.rob_reads 46300 # The number of ROB reads
system.cpu.rob.rob_writes 43308 # The number of ROB writes
system.cpu.timesIdled 181 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 8623 # Total number of cycles that the CPU has spent unscheduled due to idling
regress: update regressions for tty emulation fix.
2008-07-25 01:31:54 +02:00
system.cpu.committedInsts 14449 # Number of Instructions Simulated
system.cpu.committedInsts_total 14449 # Number of Instructions Simulated
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.cpi 2.507371 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.507371 # CPI: Total CPI of All Threads
system.cpu.ipc 0.398824 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.398824 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 28557 # number of integer regfile reads
system.cpu.int_regfile_writes 15938 # number of integer regfile writes
system.cpu.misc_regfile_reads 6251 # number of misc regfile reads
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.misc_regfile_writes 569 # number of misc regfile writes
system.cpu.icache.replacements 0 # number of replacements
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.icache.tagsinuse 193.216525 # Cycle average of tags in use
system.cpu.icache.total_refs 4151 # Total number of references to valid blocks.
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.icache.sampled_refs 332 # Sample count of references to valid blocks.
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.icache.avg_refs 12.503012 # Average number of references to valid blocks.
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.icache.occ_blocks::0 193.216525 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.094344 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 4151 # number of ReadReq hits
system.cpu.icache.demand_hits 4151 # number of demand (read+write) hits
system.cpu.icache.overall_hits 4151 # number of overall hits
system.cpu.icache.ReadReq_misses 457 # number of ReadReq misses
system.cpu.icache.demand_misses 457 # number of demand (read+write) misses
system.cpu.icache.overall_misses 457 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 15956000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 15956000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 15956000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 4608 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 4608 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 4608 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.099175 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.099175 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.099175 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 34914.660832 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 34914.660832 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 34914.660832 # average overall miss latency
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.icache.ReadReq_mshr_hits 125 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 125 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 125 # number of overall MSHR hits
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.icache.ReadReq_mshr_misses 332 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 332 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 332 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.ReadReq_mshr_miss_latency 11653500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 11653500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 11653500 # number of overall MSHR miss cycles
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate 0.072049 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.072049 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.072049 # mshr miss rate for overall accesses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35100.903614 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35100.903614 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35100.903614 # average overall mshr miss latency
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.dcache.tagsinuse 102.149831 # Cycle average of tags in use
system.cpu.dcache.total_refs 3712 # Total number of references to valid blocks.
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.dcache.avg_refs 25.424658 # Average number of references to valid blocks.
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.dcache.occ_blocks::0 102.149831 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.024939 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 2672 # number of ReadReq hits
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.dcache.WriteReq_hits 1034 # number of WriteReq hits
Added SPARC o3 insttest regression. --HG-- extra : convert_revision : b008b4bda60ced329df9b700ff9b0a978e2d3b19
2007-04-09 09:59:56 +02:00
system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.dcache.demand_hits 3706 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 3706 # number of overall hits
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.ReadReq_misses 114 # number of ReadReq misses
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.dcache.WriteReq_misses 408 # number of WriteReq misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.demand_misses 522 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 522 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 3994500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 14649500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 18644000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 18644000 # number of overall miss cycles
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.dcache.ReadReq_accesses 2786 # number of ReadReq accesses(hits+misses)
regress: update regressions for tty emulation fix.
2008-07-25 01:31:54 +02:00
system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses)
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses)
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.dcache.demand_accesses 4228 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 4228 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.040919 # miss rate for ReadReq accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu.dcache.WriteReq_miss_rate 0.282940 # miss rate for WriteReq accesses
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.dcache.demand_miss_rate 0.123463 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.123463 # miss rate for overall accesses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.ReadReq_avg_miss_latency 35039.473684 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 35905.637255 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 35716.475096 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 35716.475096 # average overall miss latency
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
Added SPARC o3 insttest regression. --HG-- extra : convert_revision : b008b4bda60ced329df9b700ff9b0a978e2d3b19
2007-04-09 09:59:56 +02:00
system.cpu.dcache.cache_copies 0 # number of cache copies performed
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.dcache.writebacks 0 # number of writebacks
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.ReadReq_mshr_hits 51 # number of ReadReq MSHR hits
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.dcache.WriteReq_mshr_hits 325 # number of WriteReq MSHR hits
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.demand_mshr_hits 376 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 376 # number of overall MSHR hits
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.dcache.ReadReq_mshr_misses 63 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 83 # number of WriteReq MSHR misses
Ref output: Update refs for PCState change.
2010-10-31 08:07:48 +01:00
system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses
Added SPARC o3 insttest regression. --HG-- extra : convert_revision : b008b4bda60ced329df9b700ff9b0a978e2d3b19
2007-04-09 09:59:56 +02:00
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.ReadReq_mshr_miss_latency 2241500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 2985000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 5226500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 5226500 # number of overall MSHR miss cycles
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.dcache.ReadReq_mshr_miss_rate 0.022613 # mshr miss rate for ReadReq accesses
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.dcache.WriteReq_mshr_miss_rate 0.057559 # mshr miss rate for WriteReq accesses
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.dcache.demand_mshr_miss_rate 0.034532 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.034532 # mshr miss rate for overall accesses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35579.365079 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35963.855422 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 35797.945205 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 35797.945205 # average overall mshr miss latency
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
Added SPARC o3 insttest regression. --HG-- extra : convert_revision : b008b4bda60ced329df9b700ff9b0a978e2d3b19
2007-04-09 09:59:56 +02:00
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.l2cache.tagsinuse 228.374360 # Cycle average of tags in use
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.005089 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
O3: Update stats for LSQ changes.
2011-08-19 22:08:06 +02:00
system.cpu.l2cache.occ_blocks::0 228.374360 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.006969 # Average percentage of cache occupancy
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 2 # number of overall hits
system.cpu.l2cache.ReadReq_misses 393 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 83 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 476 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 476 # number of overall misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.ReadReq_miss_latency 13475000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 2872000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 16347000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 16347000 # number of overall miss cycles
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.l2cache.ReadReq_accesses 395 # number of ReadReq accesses(hits+misses)
regress: update regressions for tty emulation fix.
2008-07-25 01:31:54 +02:00
system.cpu.l2cache.ReadExReq_accesses 83 # number of ReadExReq accesses(hits+misses)
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.l2cache.demand_accesses 478 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 478 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.994937 # miss rate for ReadReq accesses
Regression: Update insttest regressions for new cache. --HG-- extra : convert_revision : 100478b2ae00d9d3464c41d940276843a226422f
2007-08-14 06:16:08 +02:00
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.l2cache.demand_miss_rate 0.995816 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.995816 # miss rate for overall accesses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.ReadReq_avg_miss_latency 34287.531807 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34602.409639 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34342.436975 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34342.436975 # average overall miss latency
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
Added SPARC o3 insttest regression. --HG-- extra : convert_revision : b008b4bda60ced329df9b700ff9b0a978e2d3b19
2007-04-09 09:59:56 +02:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.l2cache.writebacks 0 # number of writebacks
Added SPARC o3 insttest regression. --HG-- extra : convert_revision : b008b4bda60ced329df9b700ff9b0a978e2d3b19
2007-04-09 09:59:56 +02:00
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.l2cache.ReadReq_mshr_misses 393 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 83 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 476 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 476 # number of overall MSHR misses
Added SPARC o3 insttest regression. --HG-- extra : convert_revision : b008b4bda60ced329df9b700ff9b0a978e2d3b19
2007-04-09 09:59:56 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_latency 12215000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2608500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 14823500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 14823500 # number of overall MSHR miss cycles
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994937 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.995816 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.995816 # mshr miss rate for overall accesses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.424936 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31427.710843 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31141.806723 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31141.806723 # average overall mshr miss latency
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
Added SPARC o3 insttest regression. --HG-- extra : convert_revision : b008b4bda60ced329df9b700ff9b0a978e2d3b19
2007-04-09 09:59:56 +02:00
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
Added SPARC o3 insttest regression. --HG-- extra : convert_revision : b008b4bda60ced329df9b700ff9b0a978e2d3b19
2007-04-09 09:59:56 +02:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink