2004-02-11 22:07:55 +01:00
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/*
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2006-03-30 00:37:25 +02:00
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* Copyright (c) 2006 The Regents of The University of Michigan
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2004-02-11 22:07:55 +01:00
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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2006-06-01 01:26:56 +02:00
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*
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* Authors: Ali Saidi
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* Nathan Binkert
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2004-02-11 22:07:55 +01:00
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*/
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2006-08-30 18:57:46 +02:00
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#include "base/chunk_generator.hh"
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2006-05-31 00:57:42 +02:00
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#include "base/trace.hh"
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2004-02-11 22:07:55 +01:00
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#include "dev/io_device.hh"
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2004-04-06 19:02:00 +02:00
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#include "sim/builder.hh"
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2006-07-13 02:22:07 +02:00
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#include "sim/system.hh"
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2004-02-11 22:07:55 +01:00
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2006-03-21 21:45:31 +01:00
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2006-07-13 02:22:07 +02:00
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PioPort::PioPort(PioDevice *dev, System *s, std::string pname)
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2006-10-31 19:59:30 +01:00
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: SimpleTimingPort(dev->name() + pname, dev), device(dev)
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2006-03-21 21:45:31 +01:00
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{ }
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Tick
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2006-10-20 09:10:12 +02:00
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PioPort::recvAtomic(PacketPtr pkt)
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2006-03-21 21:45:31 +01:00
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{
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2006-08-31 01:24:26 +02:00
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return pkt->isRead() ? device->read(pkt) : device->write(pkt);
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2006-03-21 21:45:31 +01:00
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}
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void
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2006-04-06 06:51:46 +02:00
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PioPort::getDeviceAddressRanges(AddrRangeList &resp, AddrRangeList &snoop)
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2006-03-21 21:45:31 +01:00
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{
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2006-04-06 06:51:46 +02:00
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snoop.clear();
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device->addressRanges(resp);
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2006-03-21 21:45:31 +01:00
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}
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2004-02-11 22:07:55 +01:00
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PioDevice::~PioDevice()
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{
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2006-01-31 20:20:39 +01:00
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if (pioPort)
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2006-03-21 21:45:31 +01:00
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delete pioPort;
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2004-02-11 22:07:55 +01:00
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}
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2006-04-11 19:42:47 +02:00
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void
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2006-04-10 20:40:22 +02:00
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PioDevice::init()
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{
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if (!pioPort)
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panic("Pio port not connected to anything!");
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pioPort->sendStatusChange(Port::RangeChange);
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}
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2006-07-13 02:22:07 +02:00
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unsigned int
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PioDevice::drain(Event *de)
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{
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unsigned int count;
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count = pioPort->drain(de);
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if (count)
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changeState(Draining);
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else
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changeState(Drained);
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return count;
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}
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2006-04-10 20:14:06 +02:00
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void
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BasicPioDevice::addressRanges(AddrRangeList &range_list)
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{
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assert(pioSize != 0);
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range_list.clear();
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range_list.push_back(RangeSize(pioAddr, pioSize));
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}
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2006-03-21 21:45:31 +01:00
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2006-07-13 02:22:07 +02:00
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DmaPort::DmaPort(DmaDevice *dev, System *s)
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2006-10-31 19:59:30 +01:00
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: Port(dev->name() + "-dmaport", dev), device(dev), sys(s),
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pendingCount(0), actionInProgress(0), drainEvent(NULL)
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2006-03-21 21:45:31 +01:00
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{ }
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bool
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2006-10-20 09:10:12 +02:00
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DmaPort::recvTiming(PacketPtr pkt)
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2006-01-31 20:20:39 +01:00
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{
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2006-06-09 01:43:50 +02:00
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if (pkt->result == Packet::Nacked) {
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DPRINTF(DMA, "Received nacked Pkt %#x with State: %#x Addr: %#x\n",
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pkt, pkt->senderState, pkt->getAddr());
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pkt->reinitNacked();
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sendDma(pkt, true);
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} else if (pkt->senderState) {
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2006-04-20 23:14:30 +02:00
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DmaReqState *state;
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2006-06-09 01:43:50 +02:00
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DPRINTF(DMA, "Received response Pkt %#x with State: %#x Addr: %#x\n",
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pkt, pkt->senderState, pkt->getAddr());
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2006-05-26 20:17:33 +02:00
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state = dynamic_cast<DmaReqState*>(pkt->senderState);
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2006-06-09 01:43:50 +02:00
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pendingCount--;
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assert(pendingCount >= 0);
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2006-05-31 00:57:42 +02:00
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assert(state);
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2006-06-09 01:43:50 +02:00
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state->numBytes += pkt->req->getSize();
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if (state->totBytes == state->numBytes) {
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state->completionEvent->process();
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delete state;
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}
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2006-05-19 04:32:21 +02:00
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delete pkt->req;
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delete pkt;
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2006-07-13 02:22:07 +02:00
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if (pendingCount == 0 && drainEvent) {
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drainEvent->process();
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drainEvent = NULL;
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}
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2006-04-28 21:38:43 +02:00
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} else {
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2006-06-09 01:43:50 +02:00
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panic("Got packet without sender state... huh?\n");
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2006-04-20 23:14:30 +02:00
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}
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2006-04-28 21:38:43 +02:00
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2006-05-31 00:57:42 +02:00
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return true;
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2006-01-31 20:20:39 +01:00
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}
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2004-04-06 19:02:00 +02:00
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2006-04-06 06:51:46 +02:00
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DmaDevice::DmaDevice(Params *p)
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2006-04-20 23:14:30 +02:00
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: PioDevice(p), dmaPort(NULL)
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{ }
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2006-01-31 20:20:39 +01:00
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2006-07-13 02:22:07 +02:00
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unsigned int
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DmaDevice::drain(Event *de)
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{
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unsigned int count;
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count = pioPort->drain(de) + dmaPort->drain(de);
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if (count)
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changeState(Draining);
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else
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changeState(Drained);
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return count;
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}
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unsigned int
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DmaPort::drain(Event *de)
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{
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if (pendingCount == 0)
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return 0;
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drainEvent = de;
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return 1;
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}
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2006-01-31 20:20:39 +01:00
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void
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2006-03-21 21:45:31 +01:00
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DmaPort::recvRetry()
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{
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2006-10-20 09:10:12 +02:00
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PacketPtr pkt = transmitList.front();
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2006-05-31 19:45:37 +02:00
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bool result = true;
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while (result && transmitList.size()) {
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DPRINTF(DMA, "Retry on Packet %#x with senderState: %#x\n",
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pkt, pkt->senderState);
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result = sendTiming(pkt);
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if (result) {
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DPRINTF(DMA, "-- Done\n");
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transmitList.pop_front();
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} else {
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DPRINTF(DMA, "-- Failed, queued\n");
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}
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2006-05-31 00:57:42 +02:00
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}
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2006-03-21 21:45:31 +01:00
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}
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2006-05-26 20:17:33 +02:00
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2006-03-21 21:45:31 +01:00
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void
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2006-05-26 20:17:33 +02:00
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DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
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uint8_t *data)
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2006-01-31 20:20:39 +01:00
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{
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assert(event);
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2006-07-13 02:22:07 +02:00
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assert(device->getState() == SimObject::Running);
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2006-06-09 01:43:50 +02:00
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DmaReqState *reqState = new DmaReqState(event, this, size);
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2006-01-31 20:20:39 +01:00
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2006-02-21 18:20:02 +01:00
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for (ChunkGenerator gen(addr, size, peerBlockSize());
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!gen.done(); gen.next()) {
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2006-05-31 06:12:29 +02:00
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Request *req = new Request(gen.addr(), gen.size(), 0);
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2006-10-20 09:10:12 +02:00
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PacketPtr pkt = new Packet(req, cmd, Packet::Broadcast);
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2006-05-26 20:17:33 +02:00
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2006-01-31 20:20:39 +01:00
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// Increment the data pointer on a write
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2006-04-25 01:31:50 +02:00
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if (data)
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2006-06-09 01:43:50 +02:00
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pkt->dataStatic(data + gen.complete());
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2006-05-26 20:17:33 +02:00
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2006-06-09 01:43:50 +02:00
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pkt->senderState = reqState;
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2006-05-26 20:17:33 +02:00
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2006-04-20 23:14:30 +02:00
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assert(pendingCount >= 0);
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pendingCount++;
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2006-04-25 01:31:50 +02:00
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sendDma(pkt);
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2006-01-31 20:20:39 +01:00
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}
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2006-07-13 02:22:07 +02:00
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2006-01-31 20:20:39 +01:00
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}
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void
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2006-10-20 09:10:12 +02:00
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DmaPort::sendDma(PacketPtr pkt, bool front)
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2006-01-31 20:20:39 +01:00
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{
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2006-07-13 02:22:07 +02:00
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// some kind of selction between access methods
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// more work is going to have to be done to make
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// switching actually work
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2006-07-13 21:48:17 +02:00
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2006-07-13 02:22:07 +02:00
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System::MemoryMode state = sys->getMemoryMode();
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if (state == System::Timing) {
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DPRINTF(DMA, "Attempting to send Packet %#x with addr: %#x\n",
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pkt, pkt->getAddr());
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if (transmitList.size() || !sendTiming(pkt)) {
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if (front)
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transmitList.push_front(pkt);
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else
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transmitList.push_back(pkt);
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DPRINTF(DMA, "-- Failed: queued\n");
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} else {
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DPRINTF(DMA, "-- Done\n");
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}
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} else if (state == System::Atomic) {
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2006-07-13 21:48:17 +02:00
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Tick lat;
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lat = sendAtomic(pkt);
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2006-07-13 02:22:07 +02:00
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assert(pkt->senderState);
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DmaReqState *state = dynamic_cast<DmaReqState*>(pkt->senderState);
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assert(state);
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state->numBytes += pkt->req->getSize();
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if (state->totBytes == state->numBytes) {
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2006-07-13 21:48:17 +02:00
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state->completionEvent->schedule(curTick + lat);
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2006-07-13 02:22:07 +02:00
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delete state;
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delete pkt->req;
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}
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pendingCount--;
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assert(pendingCount >= 0);
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delete pkt;
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if (pendingCount == 0 && drainEvent) {
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drainEvent->process();
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drainEvent = NULL;
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}
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2006-01-31 20:20:39 +01:00
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} else
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panic("Unknown memory command state.");
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}
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2004-02-11 22:07:55 +01:00
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DmaDevice::~DmaDevice()
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{
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2006-03-21 21:45:31 +01:00
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if (dmaPort)
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delete dmaPort;
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2004-02-11 22:07:55 +01:00
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}
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2004-04-06 19:02:00 +02:00
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