gem5/SConscript

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# -*- mode:python -*-
Many files: Update copyright dates and author list SConscript: arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_linux_process.hh: arch/alpha/alpha_memory.cc: arch/alpha/alpha_memory.hh: arch/alpha/alpha_tru64_process.cc: arch/alpha/alpha_tru64_process.hh: arch/alpha/aout_machdep.h: arch/alpha/arguments.cc: arch/alpha/arguments.hh: arch/alpha/ev5.cc: arch/alpha/ev5.hh: arch/alpha/faults.cc: arch/alpha/faults.hh: arch/alpha/isa_desc: arch/alpha/isa_traits.hh: arch/alpha/osfpal.cc: arch/alpha/osfpal.hh: arch/alpha/pseudo_inst.cc: arch/alpha/pseudo_inst.hh: arch/alpha/vptr.hh: arch/alpha/vtophys.cc: arch/alpha/vtophys.hh: base/bitfield.hh: base/callback.hh: base/circlebuf.cc: base/circlebuf.hh: base/cprintf.cc: base/cprintf.hh: base/cprintf_formats.hh: base/crc.hh: base/date.cc: base/dbl_list.hh: base/endian.hh: base/fast_alloc.cc: base/fast_alloc.hh: base/fifo_buffer.cc: base/fifo_buffer.hh: base/hashmap.hh: base/hostinfo.cc: base/hostinfo.hh: base/hybrid_pred.cc: base/hybrid_pred.hh: base/inet.cc: base/inet.hh: base/inifile.cc: base/inifile.hh: base/intmath.cc: base/intmath.hh: base/match.cc: base/match.hh: base/misc.cc: base/misc.hh: base/mod_num.hh: base/mysql.cc: base/mysql.hh: base/output.cc: base/output.hh: base/pollevent.cc: base/pollevent.hh: base/predictor.hh: base/random.cc: base/random.hh: base/range.cc: base/range.hh: base/refcnt.hh: base/remote_gdb.cc: base/remote_gdb.hh: base/res_list.hh: base/sat_counter.cc: base/sat_counter.hh: base/sched_list.hh: base/socket.cc: base/socket.hh: base/statistics.cc: base/statistics.hh: base/compression/lzss_compression.cc: base/compression/lzss_compression.hh: base/compression/null_compression.hh: base/loader/aout_object.cc: base/loader/aout_object.hh: base/loader/ecoff_object.cc: base/loader/ecoff_object.hh: base/loader/elf_object.cc: base/loader/elf_object.hh: base/loader/object_file.cc: base/loader/object_file.hh: base/loader/symtab.cc: base/loader/symtab.hh: base/stats/events.cc: base/stats/events.hh: base/stats/flags.hh: base/stats/mysql.cc: base/stats/mysql.hh: base/stats/mysql_run.hh: base/stats/output.hh: base/stats/statdb.cc: base/stats/statdb.hh: base/stats/text.cc: base/stats/text.hh: base/stats/types.hh: base/stats/visit.cc: base/stats/visit.hh: base/str.cc: base/str.hh: base/time.cc: base/time.hh: base/timebuf.hh: base/trace.cc: base/trace.hh: base/userinfo.cc: base/userinfo.hh: build/SConstruct: cpu/base.cc: cpu/base.hh: cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: cpu/exec_context.cc: cpu/exec_context.hh: cpu/exetrace.cc: cpu/exetrace.hh: cpu/inst_seq.hh: cpu/intr_control.cc: cpu/intr_control.hh: cpu/memtest/memtest.cc: cpu/pc_event.cc: cpu/pc_event.hh: cpu/smt.hh: cpu/static_inst.cc: cpu/static_inst.hh: cpu/memtest/memtest.hh: cpu/o3/sat_counter.cc: cpu/o3/sat_counter.hh: cpu/ozone/cpu.hh: cpu/simple/cpu.cc: cpu/simple/cpu.hh: cpu/trace/opt_cpu.cc: cpu/trace/opt_cpu.hh: cpu/trace/reader/ibm_reader.cc: cpu/trace/reader/ibm_reader.hh: cpu/trace/reader/itx_reader.cc: cpu/trace/reader/itx_reader.hh: cpu/trace/reader/m5_reader.cc: cpu/trace/reader/m5_reader.hh: cpu/trace/reader/mem_trace_reader.cc: cpu/trace/reader/mem_trace_reader.hh: cpu/trace/trace_cpu.cc: cpu/trace/trace_cpu.hh: dev/alpha_access.h: dev/alpha_console.cc: dev/alpha_console.hh: dev/baddev.cc: dev/baddev.hh: dev/disk_image.cc: dev/disk_image.hh: dev/etherbus.cc: dev/etherbus.hh: dev/etherdump.cc: dev/etherdump.hh: dev/etherint.cc: dev/etherint.hh: dev/etherlink.cc: dev/etherlink.hh: dev/etherpkt.cc: dev/etherpkt.hh: dev/ethertap.cc: dev/ethertap.hh: dev/ide_ctrl.cc: dev/ide_ctrl.hh: dev/ide_disk.cc: dev/ide_disk.hh: dev/io_device.cc: dev/io_device.hh: dev/ns_gige.cc: dev/ns_gige.hh: dev/ns_gige_reg.h: dev/pciconfigall.cc: dev/pciconfigall.hh: dev/pcidev.cc: dev/pcidev.hh: dev/pcireg.h: dev/pktfifo.cc: dev/pktfifo.hh: dev/platform.cc: dev/platform.hh: dev/simconsole.cc: dev/simconsole.hh: dev/simple_disk.cc: dev/simple_disk.hh: dev/sinic.cc: dev/sinic.hh: dev/sinicreg.hh: dev/tsunami.cc: dev/tsunami.hh: dev/tsunami_cchip.cc: dev/tsunami_cchip.hh: dev/tsunami_io.cc: dev/tsunami_io.hh: dev/tsunami_pchip.cc: dev/tsunami_pchip.hh: dev/tsunamireg.h: dev/uart.cc: dev/uart.hh: dev/uart8250.cc: dev/uart8250.hh: docs/stl.hh: encumbered/cpu/full/op_class.hh: kern/kernel_stats.cc: kern/kernel_stats.hh: kern/linux/linux.hh: kern/linux/linux_syscalls.cc: kern/linux/linux_syscalls.hh: kern/linux/linux_system.cc: kern/linux/linux_system.hh: kern/linux/linux_threadinfo.hh: kern/linux/printk.cc: kern/linux/printk.hh: kern/system_events.cc: kern/system_events.hh: kern/tru64/dump_mbuf.cc: kern/tru64/dump_mbuf.hh: kern/tru64/mbuf.hh: kern/tru64/printf.cc: kern/tru64/printf.hh: kern/tru64/tru64.hh: kern/tru64/tru64_events.cc: kern/tru64/tru64_events.hh: kern/tru64/tru64_syscalls.cc: kern/tru64/tru64_syscalls.hh: kern/tru64/tru64_system.cc: kern/tru64/tru64_system.hh: python/SConscript: python/m5/__init__.py: python/m5/config.py: python/m5/convert.py: python/m5/multidict.py: python/m5/smartdict.py: sim/async.hh: sim/builder.cc: sim/builder.hh: sim/debug.cc: sim/debug.hh: sim/eventq.cc: sim/eventq.hh: sim/host.hh: sim/main.cc: sim/param.cc: sim/param.hh: sim/process.cc: sim/process.hh: sim/root.cc: sim/serialize.cc: sim/serialize.hh: sim/sim_events.cc: sim/sim_events.hh: sim/sim_exit.hh: sim/sim_object.cc: sim/sim_object.hh: sim/startup.cc: sim/startup.hh: sim/stat_control.cc: sim/stat_control.hh: sim/stats.hh: sim/syscall_emul.cc: sim/syscall_emul.hh: sim/system.cc: sim/system.hh: test/bitvectest.cc: test/circletest.cc: test/cprintftest.cc: test/genini.py: test/initest.cc: test/lru_test.cc: test/nmtest.cc: test/offtest.cc: test/paramtest.cc: test/rangetest.cc: test/sized_test.cc: test/stattest.cc: test/strnumtest.cc: test/symtest.cc: test/tokentest.cc: test/tracetest.cc: util/ccdrv/devtime.c: util/m5/m5.c: util/oprofile-top.py: util/rundiff: util/m5/m5op.h: util/m5/m5op.s: util/stats/db.py: util/stats/dbinit.py: util/stats/display.py: util/stats/info.py: util/stats/print.py: util/stats/stats.py: util/tap/tap.cc: Update copyright dates and author list --HG-- extra : convert_revision : 0faba08fc0fc0146f1efb7f61e4b043c020ff9e4
2005-06-05 11:16:00 +02:00
# Copyright (c) 2004-2005 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import os
import sys
from os.path import isdir
# This file defines how to build a particular configuration of M5
# based on variable settings in the 'env' build environment.
# Import build environment variable from SConstruct.
Import('env')
###################################################
#
# Define needed sources.
#
###################################################
# Base sources used by all configurations.
base_sources = Split('''
base/circlebuf.cc
base/copyright.cc
base/cprintf.cc
New and improved configuration mechanism. No more writing of wierd ini files. The ini files are still used as an intermediate step, but a sophisticated python library exists to help build them more easily. SConscript: add the new embedded file stuff remove all of the old object description junk base/inifile.cc: base/inifile.hh: get rid of findDefault and findAppend since they were the source of much evil. base/trace.cc: For now, if we don't have the dprintf_stream set up, dump to standard out. We probably want a command line option for this. dev/alpha_console.cc: PioDevice now takes a platform parameter. All PioDevices must have a pio_latency parameter. We stick a dummy parameter in here for now until we get rid of the builder stuff. dev/alpha_console.hh: don't need Platform anymore dev/baddev.cc: PioDevice now takes a platform parameter. All PioDevices must have a pio_latency parameter. We stick a dummy parameter in here for now until we get rid of the builder stuff. Same for the platform parameter, though we just pass the PioDevice a null parameter since it isn't used by this device and it's quicker. dev/baddev.hh: fix #include guards dev/etherlink.cc: rename parameters. dev/ethertap.cc: rename parameters dev/ide_ctrl.cc: All devices need an address even if it will get overwritten later. dev/ide_disk.cc: use an enum for the drive ID stuff. rename disk_delay -> delay Actually, I think that we should implement "cable select" and have the controller tell the drive what it is. dev/io_device.cc: dev/io_device.hh: All IO devices take a Platform * dev/ns_gige.cc: all devices need an io_bus. rename header_bus to io_bus We don't need stuff for the interrupt controller since it's all in the platform now. dev/ns_gige.hh: We don't need stuff for the interrupt controller now since it's all in the platform. dev/pciconfigall.cc: Pass a dummy NULL to the PioDevice for the platform since we don't need one. dev/pcidev.cc: Move a bunch of common functionality into the PciDev dev/platform.hh: remove unneeded code dev/tsunami.cc: remove unused param dev/tsunami_cchip.cc: pass platform pointer dev/tsunami_io.cc: dev/tsunami_pchip.cc: dev/uart.cc: pass platform variable dev/uart.hh: don't need to keep a platform pointer. it's in the base class kern/linux/linux_system.cc: kern/tru64/tru64_system.cc: rename some parameters sim/builder.cc: clean up builder code. use more parameters from the config node. all sections with a type= are now created, the old mechanisms no longer work sim/builder.hh: remove some extra variables since they are found in the ConfigNode sim/main.cc: add a quick hack command line argument -X to dump out the embedded files. (probably should be fixed up a little.) accept .mpy files printing to the streams has to happen after the hierarchy is built since we're moving away from param contexts sim/param.cc: add parsing support for ranges sim/process.cc: isValid isn't very useful anymore. interpret the names stdout, stderr, cout, cerr for the file descriptors sim/pyconfig/SConscript: Add Action handlers for creating an embedded python file and for creating an embedded C file. use these action handlers to embed all objects found in the objects tree into the binary along with the importer and the m5config stuff sim/pyconfig/m5config.py: Major changes to the original configuration file generator. These changes largely involve implementing copy-on-write like semantics for all of the SimObjects. Real documentation must be written. sim/universe.cc: Universe becomes a SimObject since we don't really have the notion of param contexts in the python code. --HG-- rename : sim/pyconfig/m5configbase.py => sim/pyconfig/m5config.py extra : convert_revision : c353453e5beb91c37f15755998fc0d8858c6829a
2005-01-15 10:12:25 +01:00
base/embedfile.cc
base/fast_alloc.cc
base/fifo_buffer.cc
base/hostinfo.cc
base/hybrid_pred.cc
base/inifile.cc
base/intmath.cc
base/match.cc
base/misc.cc
base/output.cc
base/pollevent.cc
base/range.cc
base/random.cc
base/sat_counter.cc
base/socket.cc
base/statistics.cc
base/str.cc
base/time.cc
base/trace.cc
base/traceflags.cc
base/userinfo.cc
base/compression/lzss_compression.cc
base/loader/aout_object.cc
base/loader/ecoff_object.cc
base/loader/elf_object.cc
base/loader/object_file.cc
base/loader/symtab.cc
base/stats/events.cc
base/stats/statdb.cc
base/stats/visit.cc
base/stats/text.cc
shuffle files around for new directory structure --HG-- rename : cpu/base_cpu.cc => cpu/base.cc rename : cpu/base_cpu.hh => cpu/base.hh rename : cpu/beta_cpu/2bit_local_pred.cc => cpu/o3/2bit_local_pred.cc rename : cpu/beta_cpu/2bit_local_pred.hh => cpu/o3/2bit_local_pred.hh rename : cpu/beta_cpu/alpha_full_cpu.cc => cpu/o3/alpha_cpu.cc rename : cpu/beta_cpu/alpha_full_cpu.hh => cpu/o3/alpha_cpu.hh rename : cpu/beta_cpu/alpha_full_cpu_builder.cc => cpu/o3/alpha_cpu_builder.cc rename : cpu/beta_cpu/alpha_full_cpu_impl.hh => cpu/o3/alpha_cpu_impl.hh rename : cpu/beta_cpu/alpha_dyn_inst.cc => cpu/o3/alpha_dyn_inst.cc rename : cpu/beta_cpu/alpha_dyn_inst.hh => cpu/o3/alpha_dyn_inst.hh rename : cpu/beta_cpu/alpha_dyn_inst_impl.hh => cpu/o3/alpha_dyn_inst_impl.hh rename : cpu/beta_cpu/alpha_impl.hh => cpu/o3/alpha_impl.hh rename : cpu/beta_cpu/alpha_params.hh => cpu/o3/alpha_params.hh rename : cpu/beta_cpu/bpred_unit.cc => cpu/o3/bpred_unit.cc rename : cpu/beta_cpu/bpred_unit.hh => cpu/o3/bpred_unit.hh rename : cpu/beta_cpu/bpred_unit_impl.hh => cpu/o3/bpred_unit_impl.hh rename : cpu/beta_cpu/btb.cc => cpu/o3/btb.cc rename : cpu/beta_cpu/btb.hh => cpu/o3/btb.hh rename : cpu/beta_cpu/comm.hh => cpu/o3/comm.hh rename : cpu/beta_cpu/commit.cc => cpu/o3/commit.cc rename : cpu/beta_cpu/commit.hh => cpu/o3/commit.hh rename : cpu/beta_cpu/commit_impl.hh => cpu/o3/commit_impl.hh rename : cpu/beta_cpu/full_cpu.cc => cpu/o3/cpu.cc rename : cpu/beta_cpu/full_cpu.hh => cpu/o3/cpu.hh rename : cpu/beta_cpu/cpu_policy.hh => cpu/o3/cpu_policy.hh rename : cpu/beta_cpu/decode.cc => cpu/o3/decode.cc rename : cpu/beta_cpu/decode.hh => cpu/o3/decode.hh rename : cpu/beta_cpu/decode_impl.hh => cpu/o3/decode_impl.hh rename : cpu/beta_cpu/fetch.cc => cpu/o3/fetch.cc rename : cpu/beta_cpu/fetch.hh => cpu/o3/fetch.hh rename : cpu/beta_cpu/fetch_impl.hh => cpu/o3/fetch_impl.hh rename : cpu/beta_cpu/free_list.cc => cpu/o3/free_list.cc rename : cpu/beta_cpu/free_list.hh => cpu/o3/free_list.hh rename : cpu/beta_cpu/iew.cc => cpu/o3/iew.cc rename : cpu/beta_cpu/iew.hh => cpu/o3/iew.hh rename : cpu/beta_cpu/iew_impl.hh => cpu/o3/iew_impl.hh rename : cpu/beta_cpu/inst_queue.cc => cpu/o3/inst_queue.cc rename : cpu/beta_cpu/inst_queue.hh => cpu/o3/inst_queue.hh rename : cpu/beta_cpu/inst_queue_impl.hh => cpu/o3/inst_queue_impl.hh rename : cpu/beta_cpu/mem_dep_unit.cc => cpu/o3/mem_dep_unit.cc rename : cpu/beta_cpu/mem_dep_unit.hh => cpu/o3/mem_dep_unit.hh rename : cpu/beta_cpu/mem_dep_unit_impl.hh => cpu/o3/mem_dep_unit_impl.hh rename : cpu/beta_cpu/ras.cc => cpu/o3/ras.cc rename : cpu/beta_cpu/ras.hh => cpu/o3/ras.hh rename : cpu/beta_cpu/regfile.hh => cpu/o3/regfile.hh rename : cpu/beta_cpu/rename.cc => cpu/o3/rename.cc rename : cpu/beta_cpu/rename.hh => cpu/o3/rename.hh rename : cpu/beta_cpu/rename_impl.hh => cpu/o3/rename_impl.hh rename : cpu/beta_cpu/rename_map.cc => cpu/o3/rename_map.cc rename : cpu/beta_cpu/rename_map.hh => cpu/o3/rename_map.hh rename : cpu/beta_cpu/rob.cc => cpu/o3/rob.cc rename : cpu/beta_cpu/rob.hh => cpu/o3/rob.hh rename : cpu/beta_cpu/rob_impl.hh => cpu/o3/rob_impl.hh rename : cpu/beta_cpu/sat_counter.cc => cpu/o3/sat_counter.cc rename : cpu/beta_cpu/sat_counter.hh => cpu/o3/sat_counter.hh rename : cpu/beta_cpu/store_set.cc => cpu/o3/store_set.cc rename : cpu/beta_cpu/store_set.hh => cpu/o3/store_set.hh rename : cpu/beta_cpu/tournament_pred.cc => cpu/o3/tournament_pred.cc rename : cpu/beta_cpu/tournament_pred.hh => cpu/o3/tournament_pred.hh rename : cpu/ooo_cpu/ooo_cpu.cc => cpu/ozone/cpu.cc rename : cpu/ooo_cpu/ooo_cpu.hh => cpu/ozone/cpu.hh rename : cpu/ooo_cpu/ooo_impl.hh => cpu/ozone/cpu_impl.hh rename : cpu/ooo_cpu/ea_list.cc => cpu/ozone/ea_list.cc rename : cpu/ooo_cpu/ea_list.hh => cpu/ozone/ea_list.hh rename : cpu/simple_cpu/simple_cpu.cc => cpu/simple/cpu.cc rename : cpu/simple_cpu/simple_cpu.hh => cpu/simple/cpu.hh rename : cpu/full_cpu/smt.hh => cpu/smt.hh rename : cpu/full_cpu/op_class.hh => encumbered/cpu/full/op_class.hh extra : convert_revision : c4a891d8d6d3e0e9e5ea56be47d851da44d8c032
2005-06-05 02:50:10 +02:00
cpu/base.cc
cpu/base_dyn_inst.cc
cpu/exec_context.cc
cpu/exetrace.cc
cpu/pc_event.cc
cpu/static_inst.cc
shuffle files around for new directory structure --HG-- rename : cpu/base_cpu.cc => cpu/base.cc rename : cpu/base_cpu.hh => cpu/base.hh rename : cpu/beta_cpu/2bit_local_pred.cc => cpu/o3/2bit_local_pred.cc rename : cpu/beta_cpu/2bit_local_pred.hh => cpu/o3/2bit_local_pred.hh rename : cpu/beta_cpu/alpha_full_cpu.cc => cpu/o3/alpha_cpu.cc rename : cpu/beta_cpu/alpha_full_cpu.hh => cpu/o3/alpha_cpu.hh rename : cpu/beta_cpu/alpha_full_cpu_builder.cc => cpu/o3/alpha_cpu_builder.cc rename : cpu/beta_cpu/alpha_full_cpu_impl.hh => cpu/o3/alpha_cpu_impl.hh rename : cpu/beta_cpu/alpha_dyn_inst.cc => cpu/o3/alpha_dyn_inst.cc rename : cpu/beta_cpu/alpha_dyn_inst.hh => cpu/o3/alpha_dyn_inst.hh rename : cpu/beta_cpu/alpha_dyn_inst_impl.hh => cpu/o3/alpha_dyn_inst_impl.hh rename : cpu/beta_cpu/alpha_impl.hh => cpu/o3/alpha_impl.hh rename : cpu/beta_cpu/alpha_params.hh => cpu/o3/alpha_params.hh rename : cpu/beta_cpu/bpred_unit.cc => cpu/o3/bpred_unit.cc rename : cpu/beta_cpu/bpred_unit.hh => cpu/o3/bpred_unit.hh rename : cpu/beta_cpu/bpred_unit_impl.hh => cpu/o3/bpred_unit_impl.hh rename : cpu/beta_cpu/btb.cc => cpu/o3/btb.cc rename : cpu/beta_cpu/btb.hh => cpu/o3/btb.hh rename : cpu/beta_cpu/comm.hh => cpu/o3/comm.hh rename : cpu/beta_cpu/commit.cc => cpu/o3/commit.cc rename : cpu/beta_cpu/commit.hh => cpu/o3/commit.hh rename : cpu/beta_cpu/commit_impl.hh => cpu/o3/commit_impl.hh rename : cpu/beta_cpu/full_cpu.cc => cpu/o3/cpu.cc rename : cpu/beta_cpu/full_cpu.hh => cpu/o3/cpu.hh rename : cpu/beta_cpu/cpu_policy.hh => cpu/o3/cpu_policy.hh rename : cpu/beta_cpu/decode.cc => cpu/o3/decode.cc rename : cpu/beta_cpu/decode.hh => cpu/o3/decode.hh rename : cpu/beta_cpu/decode_impl.hh => cpu/o3/decode_impl.hh rename : cpu/beta_cpu/fetch.cc => cpu/o3/fetch.cc rename : cpu/beta_cpu/fetch.hh => cpu/o3/fetch.hh rename : cpu/beta_cpu/fetch_impl.hh => cpu/o3/fetch_impl.hh rename : cpu/beta_cpu/free_list.cc => cpu/o3/free_list.cc rename : cpu/beta_cpu/free_list.hh => cpu/o3/free_list.hh rename : cpu/beta_cpu/iew.cc => cpu/o3/iew.cc rename : cpu/beta_cpu/iew.hh => cpu/o3/iew.hh rename : cpu/beta_cpu/iew_impl.hh => cpu/o3/iew_impl.hh rename : cpu/beta_cpu/inst_queue.cc => cpu/o3/inst_queue.cc rename : cpu/beta_cpu/inst_queue.hh => cpu/o3/inst_queue.hh rename : cpu/beta_cpu/inst_queue_impl.hh => cpu/o3/inst_queue_impl.hh rename : cpu/beta_cpu/mem_dep_unit.cc => cpu/o3/mem_dep_unit.cc rename : cpu/beta_cpu/mem_dep_unit.hh => cpu/o3/mem_dep_unit.hh rename : cpu/beta_cpu/mem_dep_unit_impl.hh => cpu/o3/mem_dep_unit_impl.hh rename : cpu/beta_cpu/ras.cc => cpu/o3/ras.cc rename : cpu/beta_cpu/ras.hh => cpu/o3/ras.hh rename : cpu/beta_cpu/regfile.hh => cpu/o3/regfile.hh rename : cpu/beta_cpu/rename.cc => cpu/o3/rename.cc rename : cpu/beta_cpu/rename.hh => cpu/o3/rename.hh rename : cpu/beta_cpu/rename_impl.hh => cpu/o3/rename_impl.hh rename : cpu/beta_cpu/rename_map.cc => cpu/o3/rename_map.cc rename : cpu/beta_cpu/rename_map.hh => cpu/o3/rename_map.hh rename : cpu/beta_cpu/rob.cc => cpu/o3/rob.cc rename : cpu/beta_cpu/rob.hh => cpu/o3/rob.hh rename : cpu/beta_cpu/rob_impl.hh => cpu/o3/rob_impl.hh rename : cpu/beta_cpu/sat_counter.cc => cpu/o3/sat_counter.cc rename : cpu/beta_cpu/sat_counter.hh => cpu/o3/sat_counter.hh rename : cpu/beta_cpu/store_set.cc => cpu/o3/store_set.cc rename : cpu/beta_cpu/store_set.hh => cpu/o3/store_set.hh rename : cpu/beta_cpu/tournament_pred.cc => cpu/o3/tournament_pred.cc rename : cpu/beta_cpu/tournament_pred.hh => cpu/o3/tournament_pred.hh rename : cpu/ooo_cpu/ooo_cpu.cc => cpu/ozone/cpu.cc rename : cpu/ooo_cpu/ooo_cpu.hh => cpu/ozone/cpu.hh rename : cpu/ooo_cpu/ooo_impl.hh => cpu/ozone/cpu_impl.hh rename : cpu/ooo_cpu/ea_list.cc => cpu/ozone/ea_list.cc rename : cpu/ooo_cpu/ea_list.hh => cpu/ozone/ea_list.hh rename : cpu/simple_cpu/simple_cpu.cc => cpu/simple/cpu.cc rename : cpu/simple_cpu/simple_cpu.hh => cpu/simple/cpu.hh rename : cpu/full_cpu/smt.hh => cpu/smt.hh rename : cpu/full_cpu/op_class.hh => encumbered/cpu/full/op_class.hh extra : convert_revision : c4a891d8d6d3e0e9e5ea56be47d851da44d8c032
2005-06-05 02:50:10 +02:00
cpu/sampler/sampler.cc
Initial light-weight OoO CPU checkin, along with gcc-3.4 fixes. SConscript: Include new files. arch/alpha/isa_desc: Make the eaCompPtr and memAccPtr non-const so that execute() can be called on them. arch/alpha/isa_traits.hh: Add enum for total number of data registers. arch/isa_parser.py: base/traceflags.py: Include new light-weight OoO CPU model. cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: Changes to abstract more away from the base dyn inst class. cpu/beta_cpu/2bit_local_pred.cc: cpu/beta_cpu/2bit_local_pred.hh: cpu/beta_cpu/tournament_pred.cc: cpu/beta_cpu/tournament_pred.hh: Remove redundant SatCounter class. cpu/beta_cpu/alpha_dyn_inst.cc: cpu/beta_cpu/alpha_full_cpu.cc: cpu/beta_cpu/alpha_full_cpu.hh: cpu/beta_cpu/bpred_unit.cc: cpu/beta_cpu/inst_queue.cc: cpu/beta_cpu/mem_dep_unit.cc: cpu/beta_cpu/ras.cc: cpu/beta_cpu/rename_map.cc: cpu/beta_cpu/rename_map.hh: cpu/beta_cpu/rob.cc: Fix for gcc-3.4 cpu/beta_cpu/alpha_dyn_inst.hh: cpu/beta_cpu/alpha_dyn_inst_impl.hh: Fixes for gcc-3.4. Include more variables and functions that are specific to AlphaDynInst which were once in BaseDynInst. cpu/beta_cpu/alpha_full_cpu_builder.cc: Make params match the current params inherited from BaseCPU. cpu/beta_cpu/alpha_full_cpu_impl.hh: Fixes for gcc-3.4 cpu/beta_cpu/full_cpu.cc: Use new params pointer in BaseCPU. Fix for gcc-3.4. cpu/beta_cpu/full_cpu.hh: Use new params class from BaseCPU. cpu/beta_cpu/iew_impl.hh: Remove unused function. cpu/simple_cpu/simple_cpu.cc: Remove unused global variable. cpu/static_inst.hh: Include OoODynInst for new lightweight OoO CPU --HG-- extra : convert_revision : 34d9f2e64ca0313377391e0d059bf09c040286fa
2005-02-26 00:00:49 +01:00
cpu/trace/reader/mem_trace_reader.cc
cpu/trace/reader/ibm_reader.cc
cpu/trace/reader/itx_reader.cc
cpu/trace/reader/m5_reader.cc
cpu/trace/opt_cpu.cc
cpu/trace/trace_cpu.cc
shuffle files around for new directory structure --HG-- rename : cpu/base_cpu.cc => cpu/base.cc rename : cpu/base_cpu.hh => cpu/base.hh rename : cpu/beta_cpu/2bit_local_pred.cc => cpu/o3/2bit_local_pred.cc rename : cpu/beta_cpu/2bit_local_pred.hh => cpu/o3/2bit_local_pred.hh rename : cpu/beta_cpu/alpha_full_cpu.cc => cpu/o3/alpha_cpu.cc rename : cpu/beta_cpu/alpha_full_cpu.hh => cpu/o3/alpha_cpu.hh rename : cpu/beta_cpu/alpha_full_cpu_builder.cc => cpu/o3/alpha_cpu_builder.cc rename : cpu/beta_cpu/alpha_full_cpu_impl.hh => cpu/o3/alpha_cpu_impl.hh rename : cpu/beta_cpu/alpha_dyn_inst.cc => cpu/o3/alpha_dyn_inst.cc rename : cpu/beta_cpu/alpha_dyn_inst.hh => cpu/o3/alpha_dyn_inst.hh rename : cpu/beta_cpu/alpha_dyn_inst_impl.hh => cpu/o3/alpha_dyn_inst_impl.hh rename : cpu/beta_cpu/alpha_impl.hh => cpu/o3/alpha_impl.hh rename : cpu/beta_cpu/alpha_params.hh => cpu/o3/alpha_params.hh rename : cpu/beta_cpu/bpred_unit.cc => cpu/o3/bpred_unit.cc rename : cpu/beta_cpu/bpred_unit.hh => cpu/o3/bpred_unit.hh rename : cpu/beta_cpu/bpred_unit_impl.hh => cpu/o3/bpred_unit_impl.hh rename : cpu/beta_cpu/btb.cc => cpu/o3/btb.cc rename : cpu/beta_cpu/btb.hh => cpu/o3/btb.hh rename : cpu/beta_cpu/comm.hh => cpu/o3/comm.hh rename : cpu/beta_cpu/commit.cc => cpu/o3/commit.cc rename : cpu/beta_cpu/commit.hh => cpu/o3/commit.hh rename : cpu/beta_cpu/commit_impl.hh => cpu/o3/commit_impl.hh rename : cpu/beta_cpu/full_cpu.cc => cpu/o3/cpu.cc rename : cpu/beta_cpu/full_cpu.hh => cpu/o3/cpu.hh rename : cpu/beta_cpu/cpu_policy.hh => cpu/o3/cpu_policy.hh rename : cpu/beta_cpu/decode.cc => cpu/o3/decode.cc rename : cpu/beta_cpu/decode.hh => cpu/o3/decode.hh rename : cpu/beta_cpu/decode_impl.hh => cpu/o3/decode_impl.hh rename : cpu/beta_cpu/fetch.cc => cpu/o3/fetch.cc rename : cpu/beta_cpu/fetch.hh => cpu/o3/fetch.hh rename : cpu/beta_cpu/fetch_impl.hh => cpu/o3/fetch_impl.hh rename : cpu/beta_cpu/free_list.cc => cpu/o3/free_list.cc rename : cpu/beta_cpu/free_list.hh => cpu/o3/free_list.hh rename : cpu/beta_cpu/iew.cc => cpu/o3/iew.cc rename : cpu/beta_cpu/iew.hh => cpu/o3/iew.hh rename : cpu/beta_cpu/iew_impl.hh => cpu/o3/iew_impl.hh rename : cpu/beta_cpu/inst_queue.cc => cpu/o3/inst_queue.cc rename : cpu/beta_cpu/inst_queue.hh => cpu/o3/inst_queue.hh rename : cpu/beta_cpu/inst_queue_impl.hh => cpu/o3/inst_queue_impl.hh rename : cpu/beta_cpu/mem_dep_unit.cc => cpu/o3/mem_dep_unit.cc rename : cpu/beta_cpu/mem_dep_unit.hh => cpu/o3/mem_dep_unit.hh rename : cpu/beta_cpu/mem_dep_unit_impl.hh => cpu/o3/mem_dep_unit_impl.hh rename : cpu/beta_cpu/ras.cc => cpu/o3/ras.cc rename : cpu/beta_cpu/ras.hh => cpu/o3/ras.hh rename : cpu/beta_cpu/regfile.hh => cpu/o3/regfile.hh rename : cpu/beta_cpu/rename.cc => cpu/o3/rename.cc rename : cpu/beta_cpu/rename.hh => cpu/o3/rename.hh rename : cpu/beta_cpu/rename_impl.hh => cpu/o3/rename_impl.hh rename : cpu/beta_cpu/rename_map.cc => cpu/o3/rename_map.cc rename : cpu/beta_cpu/rename_map.hh => cpu/o3/rename_map.hh rename : cpu/beta_cpu/rob.cc => cpu/o3/rob.cc rename : cpu/beta_cpu/rob.hh => cpu/o3/rob.hh rename : cpu/beta_cpu/rob_impl.hh => cpu/o3/rob_impl.hh rename : cpu/beta_cpu/sat_counter.cc => cpu/o3/sat_counter.cc rename : cpu/beta_cpu/sat_counter.hh => cpu/o3/sat_counter.hh rename : cpu/beta_cpu/store_set.cc => cpu/o3/store_set.cc rename : cpu/beta_cpu/store_set.hh => cpu/o3/store_set.hh rename : cpu/beta_cpu/tournament_pred.cc => cpu/o3/tournament_pred.cc rename : cpu/beta_cpu/tournament_pred.hh => cpu/o3/tournament_pred.hh rename : cpu/ooo_cpu/ooo_cpu.cc => cpu/ozone/cpu.cc rename : cpu/ooo_cpu/ooo_cpu.hh => cpu/ozone/cpu.hh rename : cpu/ooo_cpu/ooo_impl.hh => cpu/ozone/cpu_impl.hh rename : cpu/ooo_cpu/ea_list.cc => cpu/ozone/ea_list.cc rename : cpu/ooo_cpu/ea_list.hh => cpu/ozone/ea_list.hh rename : cpu/simple_cpu/simple_cpu.cc => cpu/simple/cpu.cc rename : cpu/simple_cpu/simple_cpu.hh => cpu/simple/cpu.hh rename : cpu/full_cpu/smt.hh => cpu/smt.hh rename : cpu/full_cpu/op_class.hh => encumbered/cpu/full/op_class.hh extra : convert_revision : c4a891d8d6d3e0e9e5ea56be47d851da44d8c032
2005-06-05 02:50:10 +02:00
encumbered/mem/functional/main.cc
mem/base_hier.cc
mem/base_mem.cc
mem/hier_params.cc
mem/mem_cmd.cc
mem/mem_debug.cc
mem/mem_req.cc
mem/memory_interface.cc
mem/bus/base_interface.cc
mem/bus/bus.cc
mem/bus/bus_bridge.cc
mem/bus/bus_bridge_master.cc
mem/bus/bus_bridge_slave.cc
mem/bus/bus_interface.cc
mem/bus/dma_bus_interface.cc
mem/bus/dma_interface.cc
mem/bus/master_interface.cc
mem/bus/slave_interface.cc
mem/cache/base_cache.cc
mem/cache/cache.cc
mem/cache/cache_builder.cc
mem/cache/coherence/coherence_protocol.cc
mem/cache/coherence/uni_coherence.cc
mem/cache/miss/blocking_buffer.cc
mem/cache/miss/miss_queue.cc
mem/cache/miss/mshr.cc
mem/cache/miss/mshr_queue.cc
mem/cache/prefetch/base_prefetcher.cc
mem/cache/prefetch/prefetcher.cc
mem/cache/prefetch/tagged_prefetcher.cc
mem/cache/tags/base_tags.cc
mem/cache/tags/cache_tags.cc
mem/cache/tags/fa_lru.cc
mem/cache/tags/iic.cc
mem/cache/tags/lru.cc
mem/cache/tags/repl/gen.cc
mem/cache/tags/repl/repl.cc
mem/cache/tags/split.cc
mem/cache/tags/split_lru.cc
mem/cache/tags/split_lifo.cc
shuffle files around for new directory structure --HG-- rename : cpu/base_cpu.cc => cpu/base.cc rename : cpu/base_cpu.hh => cpu/base.hh rename : cpu/beta_cpu/2bit_local_pred.cc => cpu/o3/2bit_local_pred.cc rename : cpu/beta_cpu/2bit_local_pred.hh => cpu/o3/2bit_local_pred.hh rename : cpu/beta_cpu/alpha_full_cpu.cc => cpu/o3/alpha_cpu.cc rename : cpu/beta_cpu/alpha_full_cpu.hh => cpu/o3/alpha_cpu.hh rename : cpu/beta_cpu/alpha_full_cpu_builder.cc => cpu/o3/alpha_cpu_builder.cc rename : cpu/beta_cpu/alpha_full_cpu_impl.hh => cpu/o3/alpha_cpu_impl.hh rename : cpu/beta_cpu/alpha_dyn_inst.cc => cpu/o3/alpha_dyn_inst.cc rename : cpu/beta_cpu/alpha_dyn_inst.hh => cpu/o3/alpha_dyn_inst.hh rename : cpu/beta_cpu/alpha_dyn_inst_impl.hh => cpu/o3/alpha_dyn_inst_impl.hh rename : cpu/beta_cpu/alpha_impl.hh => cpu/o3/alpha_impl.hh rename : cpu/beta_cpu/alpha_params.hh => cpu/o3/alpha_params.hh rename : cpu/beta_cpu/bpred_unit.cc => cpu/o3/bpred_unit.cc rename : cpu/beta_cpu/bpred_unit.hh => cpu/o3/bpred_unit.hh rename : cpu/beta_cpu/bpred_unit_impl.hh => cpu/o3/bpred_unit_impl.hh rename : cpu/beta_cpu/btb.cc => cpu/o3/btb.cc rename : cpu/beta_cpu/btb.hh => cpu/o3/btb.hh rename : cpu/beta_cpu/comm.hh => cpu/o3/comm.hh rename : cpu/beta_cpu/commit.cc => cpu/o3/commit.cc rename : cpu/beta_cpu/commit.hh => cpu/o3/commit.hh rename : cpu/beta_cpu/commit_impl.hh => cpu/o3/commit_impl.hh rename : cpu/beta_cpu/full_cpu.cc => cpu/o3/cpu.cc rename : cpu/beta_cpu/full_cpu.hh => cpu/o3/cpu.hh rename : cpu/beta_cpu/cpu_policy.hh => cpu/o3/cpu_policy.hh rename : cpu/beta_cpu/decode.cc => cpu/o3/decode.cc rename : cpu/beta_cpu/decode.hh => cpu/o3/decode.hh rename : cpu/beta_cpu/decode_impl.hh => cpu/o3/decode_impl.hh rename : cpu/beta_cpu/fetch.cc => cpu/o3/fetch.cc rename : cpu/beta_cpu/fetch.hh => cpu/o3/fetch.hh rename : cpu/beta_cpu/fetch_impl.hh => cpu/o3/fetch_impl.hh rename : cpu/beta_cpu/free_list.cc => cpu/o3/free_list.cc rename : cpu/beta_cpu/free_list.hh => cpu/o3/free_list.hh rename : cpu/beta_cpu/iew.cc => cpu/o3/iew.cc rename : cpu/beta_cpu/iew.hh => cpu/o3/iew.hh rename : cpu/beta_cpu/iew_impl.hh => cpu/o3/iew_impl.hh rename : cpu/beta_cpu/inst_queue.cc => cpu/o3/inst_queue.cc rename : cpu/beta_cpu/inst_queue.hh => cpu/o3/inst_queue.hh rename : cpu/beta_cpu/inst_queue_impl.hh => cpu/o3/inst_queue_impl.hh rename : cpu/beta_cpu/mem_dep_unit.cc => cpu/o3/mem_dep_unit.cc rename : cpu/beta_cpu/mem_dep_unit.hh => cpu/o3/mem_dep_unit.hh rename : cpu/beta_cpu/mem_dep_unit_impl.hh => cpu/o3/mem_dep_unit_impl.hh rename : cpu/beta_cpu/ras.cc => cpu/o3/ras.cc rename : cpu/beta_cpu/ras.hh => cpu/o3/ras.hh rename : cpu/beta_cpu/regfile.hh => cpu/o3/regfile.hh rename : cpu/beta_cpu/rename.cc => cpu/o3/rename.cc rename : cpu/beta_cpu/rename.hh => cpu/o3/rename.hh rename : cpu/beta_cpu/rename_impl.hh => cpu/o3/rename_impl.hh rename : cpu/beta_cpu/rename_map.cc => cpu/o3/rename_map.cc rename : cpu/beta_cpu/rename_map.hh => cpu/o3/rename_map.hh rename : cpu/beta_cpu/rob.cc => cpu/o3/rob.cc rename : cpu/beta_cpu/rob.hh => cpu/o3/rob.hh rename : cpu/beta_cpu/rob_impl.hh => cpu/o3/rob_impl.hh rename : cpu/beta_cpu/sat_counter.cc => cpu/o3/sat_counter.cc rename : cpu/beta_cpu/sat_counter.hh => cpu/o3/sat_counter.hh rename : cpu/beta_cpu/store_set.cc => cpu/o3/store_set.cc rename : cpu/beta_cpu/store_set.hh => cpu/o3/store_set.hh rename : cpu/beta_cpu/tournament_pred.cc => cpu/o3/tournament_pred.cc rename : cpu/beta_cpu/tournament_pred.hh => cpu/o3/tournament_pred.hh rename : cpu/ooo_cpu/ooo_cpu.cc => cpu/ozone/cpu.cc rename : cpu/ooo_cpu/ooo_cpu.hh => cpu/ozone/cpu.hh rename : cpu/ooo_cpu/ooo_impl.hh => cpu/ozone/cpu_impl.hh rename : cpu/ooo_cpu/ea_list.cc => cpu/ozone/ea_list.cc rename : cpu/ooo_cpu/ea_list.hh => cpu/ozone/ea_list.hh rename : cpu/simple_cpu/simple_cpu.cc => cpu/simple/cpu.cc rename : cpu/simple_cpu/simple_cpu.hh => cpu/simple/cpu.hh rename : cpu/full_cpu/smt.hh => cpu/smt.hh rename : cpu/full_cpu/op_class.hh => encumbered/cpu/full/op_class.hh extra : convert_revision : c4a891d8d6d3e0e9e5ea56be47d851da44d8c032
2005-06-05 02:50:10 +02:00
mem/functional/functional.cc
mem/timing/base_memory.cc
mem/timing/memory_builder.cc
mem/timing/simple_mem_bank.cc
mem/trace/itx_writer.cc
mem/trace/mem_trace_writer.cc
mem/trace/m5_writer.cc
stick all python stuff into a top level python directory. create an m5 package in python/m5 move the objects package into the m5 package move the m5config into the m5 package as config leave both importers outside of the package. SConscript: sim/main.cc: move sim/pyconfig/* -> python python/SConscript: m5config.py -> m5/config.py (now automatically embedded) objects -> python/m5/objects embed all python files in python/m5 python/m5/config.py: importer renamed mpy_importer move code to m5/__init__.py test/genini.py: deal with new python organization keep track of paths we want to add and add them after parameters are parsed. --HG-- rename : sim/pyconfig/SConscript => python/SConscript rename : sim/pyconfig/m5config.py => python/m5/config.py rename : objects/AlphaConsole.mpy => python/m5/objects/AlphaConsole.mpy rename : objects/AlphaTLB.mpy => python/m5/objects/AlphaTLB.mpy rename : objects/BadDevice.mpy => python/m5/objects/BadDevice.mpy rename : objects/BaseCPU.mpy => python/m5/objects/BaseCPU.mpy rename : objects/BaseCache.mpy => python/m5/objects/BaseCache.mpy rename : objects/BaseSystem.mpy => python/m5/objects/BaseSystem.mpy rename : objects/Bus.mpy => python/m5/objects/Bus.mpy rename : objects/CoherenceProtocol.mpy => python/m5/objects/CoherenceProtocol.mpy rename : objects/Device.mpy => python/m5/objects/Device.mpy rename : objects/DiskImage.mpy => python/m5/objects/DiskImage.mpy rename : objects/Ethernet.mpy => python/m5/objects/Ethernet.mpy rename : objects/Ide.mpy => python/m5/objects/Ide.mpy rename : objects/IntrControl.mpy => python/m5/objects/IntrControl.mpy rename : objects/MemTest.mpy => python/m5/objects/MemTest.mpy rename : objects/Pci.mpy => python/m5/objects/Pci.mpy rename : objects/PhysicalMemory.mpy => python/m5/objects/PhysicalMemory.mpy rename : objects/Platform.mpy => python/m5/objects/Platform.mpy rename : objects/Process.mpy => python/m5/objects/Process.mpy rename : objects/Repl.mpy => python/m5/objects/Repl.mpy rename : objects/Root.mpy => python/m5/objects/Root.mpy rename : objects/SimConsole.mpy => python/m5/objects/SimConsole.mpy rename : objects/SimpleDisk.mpy => python/m5/objects/SimpleDisk.mpy rename : objects/Tsunami.mpy => python/m5/objects/Tsunami.mpy rename : objects/Uart.mpy => python/m5/objects/Uart.mpy extra : convert_revision : aebf6ccda33028b1125974ca8b6aeab6f7570f30
2005-03-12 00:28:38 +01:00
python/pyconfig.cc
python/embedded_py.cc
sim/builder.cc
sim/configfile.cc
sim/debug.cc
sim/eventq.cc
Changed the fault enum into a class, and fixed everything up to work with it. Next, the faults need to be pulled out of all the other code so that they are only used to communicate between the CPU and the ISA. SConscript: The new faults.cc file in sim allocates the system wide faults. When these faults are generated through a function interface in the ISA, this file may go away. arch/alpha/alpha_memory.cc: Changed Fault to Fault * and took the underscores out of fault names. arch/alpha/alpha_memory.hh: Changed Fault to Fault *. Also, added an include for the alpha faults. arch/alpha/ev5.cc: Changed the fault_addr array into a fault_addr function. Once all of the faults can be expected to have the same type, fault_addr can go away completely and the info it provided will come from the fault itself. Also, Fault was changed to Fault *, and underscores were taken out of fault names. arch/alpha/isa/decoder.isa: Changed Fault to Fault * and took the underscores out fault names. arch/alpha/isa/fp.isa: Changed Fault to Fault *, and took the underscores out of fault names. arch/alpha/isa/main.isa: Changed Fault to Fault *, removed underscores from fault names, and made an include of the alpha faults show up in all the generated files. arch/alpha/isa/mem.isa: Changed Fault to Fault * and removed underscores from fault names. arch/alpha/isa/unimp.isa: arch/alpha/isa/unknown.isa: cpu/exec_context.hh: cpu/ozone/cpu.hh: cpu/simple/cpu.cc: dev/alpha_console.cc: dev/ide_ctrl.cc: dev/isa_fake.cc: dev/pciconfigall.cc: dev/pcidev.cc: dev/pcidev.hh: dev/tsunami_cchip.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: Changed Fault to Fault *, and removed underscores from fault names. arch/alpha/isa_traits.hh: Changed the include of arch/alpha/faults.hh to sim/faults.hh, since the alpha faults weren't needed. cpu/base_dyn_inst.cc: Changed Fault to Fault *, and removed underscores from fault names. This file probably shouldn't use the Unimplemented Opcode fault. cpu/base_dyn_inst.hh: Changed Fault to Fault * and took the underscores out of the fault names. cpu/exec_context.cc: cpu/o3/alpha_dyn_inst.hh: cpu/o3/alpha_dyn_inst_impl.hh: cpu/o3/fetch.hh: dev/alpha_console.hh: dev/baddev.hh: dev/ide_ctrl.hh: dev/isa_fake.hh: dev/ns_gige.hh: dev/pciconfigall.hh: dev/sinic.hh: dev/tsunami_cchip.hh: dev/tsunami_io.hh: dev/tsunami_pchip.hh: dev/uart.hh: dev/uart8250.hh: Changed Fault to Fault *. cpu/o3/alpha_cpu.hh: Changed Fault to Fault *, removed underscores from fault names. cpu/o3/alpha_cpu_impl.hh: Changed Fault to Fault *, removed underscores from fault names, and changed the fault_addr array to the fault_addr function. Once all faults are from the ISA, this function will probably go away. cpu/o3/commit_impl.hh: cpu/o3/fetch_impl.hh: dev/baddev.cc: Changed Fault to Fault *, and removed underscores from the fault names. cpu/o3/regfile.hh: Added an include for the alpha specific faults which will hopefully go away once the ipr stuff is moved, changed Fault to Fault *, and removed the underscores from fault names. cpu/simple/cpu.hh: Changed Fault to Fault * dev/ns_gige.cc: Changed Fault to Fault *, and removdd underscores from fault names. dev/sinic.cc: Changed Fault to Fault *, and removed the underscores from fault names. dev/uart8250.cc: Chanted Fault to Fault *, and removed underscores from fault names. kern/kernel_stats.cc: Removed underscores from fault names, and from NumFaults. kern/kernel_stats.hh: Changed the predeclaration of Fault from an enum to a class, and changd the "fault" function to work with the classes instead of the enum. Once there are no system wide faults anymore, this code will simplify back to something like it was originally. sim/faults.cc: This allocates the system wide faults. sim/faults.hh: This declares the system wide faults. sim/syscall_emul.cc: sim/syscall_emul.hh: Removed the underscores from fault names. --HG-- rename : arch/alpha/faults.cc => sim/faults.cc rename : arch/alpha/faults.hh => sim/faults.hh extra : convert_revision : 253d39258237333ae8ec4d8047367cb3ea68569d
2006-02-16 07:22:51 +01:00
sim/faults.cc
sim/main.cc
sim/param.cc
sim/profile.cc
sim/root.cc
sim/serialize.cc
sim/sim_events.cc
sim/sim_exit.cc
sim/sim_object.cc
sim/startup.cc
sim/stat_context.cc
sim/stat_control.cc
sim/trace_context.cc
''')
# Old FullCPU sources
full_cpu_sources = Split('''
encumbered/cpu/full/bpred.cc
encumbered/cpu/full/commit.cc
encumbered/cpu/full/cpu.cc
encumbered/cpu/full/create_vector.cc
encumbered/cpu/full/cv_spec_state.cc
encumbered/cpu/full/dd_queue.cc
encumbered/cpu/full/dep_link.cc
encumbered/cpu/full/dispatch.cc
encumbered/cpu/full/dyn_inst.cc
encumbered/cpu/full/execute.cc
encumbered/cpu/full/fetch.cc
encumbered/cpu/full/floss_reasons.cc
encumbered/cpu/full/fu_pool.cc
encumbered/cpu/full/inst_fifo.cc
encumbered/cpu/full/instpipe.cc
encumbered/cpu/full/issue.cc
encumbered/cpu/full/ls_queue.cc
encumbered/cpu/full/machine_queue.cc
encumbered/cpu/full/pipetrace.cc
encumbered/cpu/full/readyq.cc
encumbered/cpu/full/reg_info.cc
encumbered/cpu/full/rob_station.cc
encumbered/cpu/full/spec_memory.cc
encumbered/cpu/full/spec_state.cc
encumbered/cpu/full/storebuffer.cc
encumbered/cpu/full/writeback.cc
encumbered/cpu/full/iq/iq_station.cc
encumbered/cpu/full/iq/iqueue.cc
encumbered/cpu/full/iq/segmented/chain_info.cc
encumbered/cpu/full/iq/segmented/chain_wire.cc
encumbered/cpu/full/iq/segmented/iq_seg.cc
encumbered/cpu/full/iq/segmented/iq_segmented.cc
encumbered/cpu/full/iq/segmented/seg_chain.cc
encumbered/cpu/full/iq/seznec/iq_seznec.cc
encumbered/cpu/full/iq/standard/iq_standard.cc
''')
# MySql sources
mysql_sources = Split('''
base/mysql.cc
base/stats/mysql.cc
''')
# Full-system sources
full_system_sources = Split('''
Clean up network header stuff and make it more generic. Use libdnet when we can instead of our own home grown stuff. SConscript: separate the crc code into its own file base/inet.cc: move the crc stuff to crc.cc add generic code for calculating ip/tcp/udp checksums base/inet.hh: - move crc stuff to crc.hh - #include all of the libdnet stuff. (this makes base/inet.hh the only file you need to include if you want to use this kind of stuff.) - Wrap some of the libdnet structs to get easier access to structure members. These wrappers will automatically deal with masking/shifting/ byte-swapping. base/refcnt.hh: If one derives from RefCountingPtr, they should have access to the internal data pointer. build/SConstruct: make #include of dnet stuff work dev/etherlink.cc: dev/ethertap.cc: dev/ethertap.hh: EtherPacket -> PacketData dev/etherpkt.cc: EtherPacket -> PacketData add a function for populating extra info about a packet. Basically just gives pointers to ethernet/ip/tcp/udp headers if they exist. dev/etherpkt.hh: EtherPacket -> PacketData remove most of the packet header stuff from teh PacketData class and just add a few generic functions for grabbing various headers that may exist in the packet. The old functionality is contained in the headers. dev/ns_gige.cc: - IP -> Ip, UDP -> Udp, TCP ->Tcp when used in variable names - get rid of our own byte swapping functions. - whack checksum code and use libdnet version. - Get pointers to the various packet headers and grab info from those headers. (The byte swapping in the headers now.) - Add stats for Udp Checksums dev/ns_gige.hh: use libdnet for checksum code. IP -> Ip, TCP -> Tcp in variable names add stats for UDP checksums --HG-- extra : convert_revision : 96c4160e1967b7c0090acd456df4a76e1f3aab53
2004-09-20 16:43:53 +02:00
base/crc.cc
base/inet.cc
base/remote_gdb.cc
cpu/intr_control.cc
cpu/profile.cc
dev/alpha_console.cc
dev/baddev.cc
dev/simconsole.cc
dev/disk_image.cc
dev/etherbus.cc
dev/etherdump.cc
dev/etherint.cc
dev/etherlink.cc
dev/etherpkt.cc
dev/ethertap.cc
dev/ide_ctrl.cc
dev/ide_disk.cc
dev/io_device.cc
dev/ns_gige.cc
dev/pciconfigall.cc
dev/pcidev.cc
dev/pcifake.cc
dev/pktfifo.cc
dev/platform.cc
dev/sinic.cc
dev/simple_disk.cc
dev/tsunami.cc
dev/tsunami_cchip.cc
Changes for getting FreeBSD to run. SConscript: Added more files to compile: dev/pcifake.cc, dev/isa_fake.cc, kern/freebsd/freebsd_system.cc, kern/freebsd/freebsd_events.cc. arch/alpha/isa_traits.hh: Added constant for argument register 2 as it is needed by FreebsdSystem::doCalibrateClocks(). cpu/exec_context.hh: cpu/o3/alpha_cpu.hh: Replaced htoa()s with gtoh() and htog(). cpu/o3/fetch_impl.hh: cpu/simple/cpu.cc: Replaced htoa() with gtoh(). dev/disk_image.cc: Replaced htoa()s with letoh()s. dev/ide_ctrl.cc: Got rid of magic numbers. Added IdeChannel and IdeRegType type names where necessary. dev/ide_ctrl.hh: Got rid of unnecessary macros. Changed RegType_t to IdeRegType. Changed bmi_regs to allow accessing registers by name instead of just by array index. Added IdeChannel enum type to use in place of bool variables which were used to specify IDE channel. dev/ide_disk.cc: Rewrote IdeDisk::read and IdeDisk::write functions to specify registers by name instead of indexing through an array. dev/ide_disk.hh: Updated command register struct. dev/ns_gige.cc: dev/ns_gige.hh: Made ReadConfig and WriteConfig begin with a lower-case letter. writeConfig() now takes a pointer to data as a parameter instead of a copy of data. dev/pciconfigall.cc: writeConfig() now takes a pointer to data as a parameter instead of a copy of data. dev/pcidev.cc: Cleaned up readConfig() and writeConfig() functions. dev/pcidev.hh: Added macros to make code that works with the BARs (base adress registers) more readable. writeConfig() now takes a pointer to data. dev/pcireg.h: Changed PCIConfig struct to make accessing elements more straight forward. Removed type 1 (for PCI-to-PCI bridges) PCI configuration space struct since it is not used. dev/rtcreg.h: Added macros for bit fields in RTC status registers A & B. dev/sinic.cc: Function name change: WriteConfig --> writeConfig. writeConfig() now takes a pointer to data instead of a copy of data. The accessing of elements of PCIConfig structure is updated. dev/sinic.hh: Function name change: WriteConfig --> writeConfig. writeConfig() now takes a pointer to data instead of a copy of data. dev/tsunami_io.cc: Added implementation of new RTC and PIT classes. dev/tsunami_io.hh: Added classes for RTC and PIT modules. dev/tsunamireg.h: Added macros for DMA ports used by Tsunami-Tru64. dev/uart8250.cc: Got rid of a magic number. Transmit (Tx) interrupts should clear upon a read of the Interrupt ID register. dev/uart8250.hh: Added comments and macros dealing with the UART Interrupt ID register. kern/linux/linux_system.cc: Replaced htoa() with htog(). python/m5/objects/Pci.py: PciFake is a python class for Pci Devices that do nothing. python/m5/objects/Tsunami.py: TsunamiFake was renamed as IsaFake. sim/system.cc: Replaced htoa()s with htog()s. dev/isa_fake.cc: New BitKeeper file ``dev/isa_fake.cc'' TsunamiFake was renamed as IsaFake. dev/isa_fake.hh: New BitKeeper file ``dev/isa_fake.hh'' TsunmaiFake was renamed as IsaFake. dev/pitreg.h: New BitKeeper file ``dev/pitreg.h'' Useful macros for working with PIT (Periodic Interval Timer) registers. --HG-- extra : convert_revision : 33f3a8a1034af4f6c71b32dd743e371c8613e780
2005-08-15 22:59:58 +02:00
dev/isa_fake.cc
dev/tsunami_io.cc
dev/tsunami_pchip.cc
dev/uart.cc
dev/uart8250.cc
- Clean up and factor out all of the binning code into a single place so it's easier to work with. - Add support for binning kernel/user/idle time separately from lisa's binning stuff, but make the two compatible. - KernelStats used to directly implement the pImpl idiom, but it makes more sense to just remove the level of indirection and make the exec context have a pointer to the stats. - Factor common code out of LinuxSystem and Tru64System and put it into the System base class. While doing that, make all constructors take a pointer to a parameter struct instead of naming the parameters individually to make it much easier to add parameters to these classes. SConscript: Move the function tracking and binning stuff around. arch/alpha/ev5.cc: kernelStats is now a pointer arch/alpha/pseudo_inst.cc: kernelStats is now a pointer the parameters to the system have been moved into their own struct base/trace.hh: provide a little functor class for wrapping a string that can allow you to define name() in any scope very simply for use with DPRINTF cpu/base_cpu.cc: New order of arguments for consistency. cpu/exec_context.cc: kernelStats no longer has the level of indirection in it, execContext has the indirection now. so, kernelStats is a pointer. We also need a pointer to the kernelBinning stuff from the system and we need to figure out if we want to do binning or not. Move a whole bunch of code into kern_binning.cc so it's all in the same place. cpu/exec_context.hh: We want pointers to the kernel binning/stats stuff and we'll have the exec_context and system have the level of indirection instead of having the extra layer in the kernel stats class. cpu/simple_cpu/simple_cpu.cc: call through the exec context to do the special binning stuff. kern/kernel_stats.cc: kern/kernel_stats.hh: Re-organize the stats stuff and remove the level of indirection (that was there to simplify building) and move the binning stuff into its own class/file. kern/linux/linux_system.cc: kern/linux/linux_system.hh: kern/tru64/tru64_system.cc: kern/tru64/tru64_system.hh: sim/system.cc: sim/system.hh: move lots of common system code into the base system class so that it can be shared between linux, tru64, and whatever else we decide to support in the future. Make the constructor take a pointer to a parameter struct so that it is easier to pass parameters to the parent. kern/system_events.cc: move the majority of the binning code into the Kernel::Binning class in the kern_binning file kern/system_events.hh: FnEvents only need to know the bin create the Idle start event to find the PCBB of the idle process when it starts. kern/tru64/tru64_events.cc: memCtrl -> memctrl sim/process.cc: sim/process.hh: re-order args for consistency --HG-- extra : convert_revision : 86cb39738c41fcd680f2aad125c9dde000227b2b
2004-08-20 17:35:31 +02:00
kern/kernel_binning.cc
kern/kernel_stats.cc
kern/system_events.cc
kern/freebsd/freebsd_system.cc
kern/linux/linux_syscalls.cc
kern/linux/linux_system.cc
kern/linux/printk.cc
kern/tru64/dump_mbuf.cc
kern/tru64/printf.cc
kern/tru64/tru64_events.cc
kern/tru64/tru64_syscalls.cc
kern/tru64/tru64_system.cc
shuffle files around for new directory structure --HG-- rename : cpu/base_cpu.cc => cpu/base.cc rename : cpu/base_cpu.hh => cpu/base.hh rename : cpu/beta_cpu/2bit_local_pred.cc => cpu/o3/2bit_local_pred.cc rename : cpu/beta_cpu/2bit_local_pred.hh => cpu/o3/2bit_local_pred.hh rename : cpu/beta_cpu/alpha_full_cpu.cc => cpu/o3/alpha_cpu.cc rename : cpu/beta_cpu/alpha_full_cpu.hh => cpu/o3/alpha_cpu.hh rename : cpu/beta_cpu/alpha_full_cpu_builder.cc => cpu/o3/alpha_cpu_builder.cc rename : cpu/beta_cpu/alpha_full_cpu_impl.hh => cpu/o3/alpha_cpu_impl.hh rename : cpu/beta_cpu/alpha_dyn_inst.cc => cpu/o3/alpha_dyn_inst.cc rename : cpu/beta_cpu/alpha_dyn_inst.hh => cpu/o3/alpha_dyn_inst.hh rename : cpu/beta_cpu/alpha_dyn_inst_impl.hh => cpu/o3/alpha_dyn_inst_impl.hh rename : cpu/beta_cpu/alpha_impl.hh => cpu/o3/alpha_impl.hh rename : cpu/beta_cpu/alpha_params.hh => cpu/o3/alpha_params.hh rename : cpu/beta_cpu/bpred_unit.cc => cpu/o3/bpred_unit.cc rename : cpu/beta_cpu/bpred_unit.hh => cpu/o3/bpred_unit.hh rename : cpu/beta_cpu/bpred_unit_impl.hh => cpu/o3/bpred_unit_impl.hh rename : cpu/beta_cpu/btb.cc => cpu/o3/btb.cc rename : cpu/beta_cpu/btb.hh => cpu/o3/btb.hh rename : cpu/beta_cpu/comm.hh => cpu/o3/comm.hh rename : cpu/beta_cpu/commit.cc => cpu/o3/commit.cc rename : cpu/beta_cpu/commit.hh => cpu/o3/commit.hh rename : cpu/beta_cpu/commit_impl.hh => cpu/o3/commit_impl.hh rename : cpu/beta_cpu/full_cpu.cc => cpu/o3/cpu.cc rename : cpu/beta_cpu/full_cpu.hh => cpu/o3/cpu.hh rename : cpu/beta_cpu/cpu_policy.hh => cpu/o3/cpu_policy.hh rename : cpu/beta_cpu/decode.cc => cpu/o3/decode.cc rename : cpu/beta_cpu/decode.hh => cpu/o3/decode.hh rename : cpu/beta_cpu/decode_impl.hh => cpu/o3/decode_impl.hh rename : cpu/beta_cpu/fetch.cc => cpu/o3/fetch.cc rename : cpu/beta_cpu/fetch.hh => cpu/o3/fetch.hh rename : cpu/beta_cpu/fetch_impl.hh => cpu/o3/fetch_impl.hh rename : cpu/beta_cpu/free_list.cc => cpu/o3/free_list.cc rename : cpu/beta_cpu/free_list.hh => cpu/o3/free_list.hh rename : cpu/beta_cpu/iew.cc => cpu/o3/iew.cc rename : cpu/beta_cpu/iew.hh => cpu/o3/iew.hh rename : cpu/beta_cpu/iew_impl.hh => cpu/o3/iew_impl.hh rename : cpu/beta_cpu/inst_queue.cc => cpu/o3/inst_queue.cc rename : cpu/beta_cpu/inst_queue.hh => cpu/o3/inst_queue.hh rename : cpu/beta_cpu/inst_queue_impl.hh => cpu/o3/inst_queue_impl.hh rename : cpu/beta_cpu/mem_dep_unit.cc => cpu/o3/mem_dep_unit.cc rename : cpu/beta_cpu/mem_dep_unit.hh => cpu/o3/mem_dep_unit.hh rename : cpu/beta_cpu/mem_dep_unit_impl.hh => cpu/o3/mem_dep_unit_impl.hh rename : cpu/beta_cpu/ras.cc => cpu/o3/ras.cc rename : cpu/beta_cpu/ras.hh => cpu/o3/ras.hh rename : cpu/beta_cpu/regfile.hh => cpu/o3/regfile.hh rename : cpu/beta_cpu/rename.cc => cpu/o3/rename.cc rename : cpu/beta_cpu/rename.hh => cpu/o3/rename.hh rename : cpu/beta_cpu/rename_impl.hh => cpu/o3/rename_impl.hh rename : cpu/beta_cpu/rename_map.cc => cpu/o3/rename_map.cc rename : cpu/beta_cpu/rename_map.hh => cpu/o3/rename_map.hh rename : cpu/beta_cpu/rob.cc => cpu/o3/rob.cc rename : cpu/beta_cpu/rob.hh => cpu/o3/rob.hh rename : cpu/beta_cpu/rob_impl.hh => cpu/o3/rob_impl.hh rename : cpu/beta_cpu/sat_counter.cc => cpu/o3/sat_counter.cc rename : cpu/beta_cpu/sat_counter.hh => cpu/o3/sat_counter.hh rename : cpu/beta_cpu/store_set.cc => cpu/o3/store_set.cc rename : cpu/beta_cpu/store_set.hh => cpu/o3/store_set.hh rename : cpu/beta_cpu/tournament_pred.cc => cpu/o3/tournament_pred.cc rename : cpu/beta_cpu/tournament_pred.hh => cpu/o3/tournament_pred.hh rename : cpu/ooo_cpu/ooo_cpu.cc => cpu/ozone/cpu.cc rename : cpu/ooo_cpu/ooo_cpu.hh => cpu/ozone/cpu.hh rename : cpu/ooo_cpu/ooo_impl.hh => cpu/ozone/cpu_impl.hh rename : cpu/ooo_cpu/ea_list.cc => cpu/ozone/ea_list.cc rename : cpu/ooo_cpu/ea_list.hh => cpu/ozone/ea_list.hh rename : cpu/simple_cpu/simple_cpu.cc => cpu/simple/cpu.cc rename : cpu/simple_cpu/simple_cpu.hh => cpu/simple/cpu.hh rename : cpu/full_cpu/smt.hh => cpu/smt.hh rename : cpu/full_cpu/op_class.hh => encumbered/cpu/full/op_class.hh extra : convert_revision : c4a891d8d6d3e0e9e5ea56be47d851da44d8c032
2005-06-05 02:50:10 +02:00
mem/functional/memory_control.cc
mem/functional/physical.cc
sim/system.cc
sim/pseudo_inst.cc
''')
# turbolaser encumbered sources
turbolaser_sources = Split('''
encumbered/dev/dma.cc
encumbered/dev/etherdev.cc
encumbered/dev/scsi.cc
encumbered/dev/scsi_ctrl.cc
encumbered/dev/scsi_disk.cc
encumbered/dev/scsi_none.cc
encumbered/dev/tlaser_clock.cc
encumbered/dev/tlaser_ipi.cc
encumbered/dev/tlaser_mbox.cc
encumbered/dev/tlaser_mc146818.cc
encumbered/dev/tlaser_node.cc
encumbered/dev/tlaser_pcia.cc
encumbered/dev/tlaser_pcidev.cc
encumbered/dev/tlaser_serial.cc
encumbered/dev/turbolaser.cc
encumbered/dev/uart8530.cc
''')
# Syscall emulation (non-full-system) sources
syscall_emulation_sources = Split('''
cpu/memtest/memtest.cc
encumbered/eio/eio.cc
encumbered/eio/exolex.cc
encumbered/eio/libexo.cc
kern/linux/linux.cc
kern/tru64/tru64.cc
sim/process.cc
sim/syscall_emul.cc
''')
# The following stuff (targetarch code and global define of THE_ISA)
# are legacy things that assume we're only compiling one ISA at a
# time. These will have to go away if we want to build a binary that
# supports multiple ISAs.
#targetarch_files = Split('''
# alpha_linux_process.hh
# alpha_memory.hh
# alpha_tru64_process.hh
# aout_machdep.h
# arguments.hh
# ecoff_machdep.h
# ev5.hh
# faults.hh
# stacktrace.hh
# vtophys.hh
# ''')
# Set up bridging headers to the architecture specific versions
#for f in targetarch_files:
# env.Command('targetarch/' + f, 'arch/%s/%s' % (env['TARGET_ISA'], f),
# '''echo '#include "arch/%s/%s"' > $TARGET''' % (env['TARGET_ISA'], f))
# Add a flag defining what THE_ISA should be for all compilation
env.Append(CPPDEFINES=[('THE_ISA','%s_ISA' % env['TARGET_ISA'].upper())])
arch_sources = SConscript('arch/SConscript',
exports = 'env', duplicate = False)
cpu_sources = SConscript('cpu/SConscript',
exports = 'env', duplicate = False)
# This is outside of cpu/SConscript since the source directory isn't
# underneath 'cpu'.
if 'FullCPU' in env['CPU_MODELS']:
cpu_sources += full_cpu_sources
# Set up complete list of sources based on configuration.
sources = base_sources + arch_sources + cpu_sources
if env['FULL_SYSTEM']:
sources += full_system_sources
if env['ALPHA_TLASER']:
sources += turbolaser_sources
else:
sources += syscall_emulation_sources
Build options are set via a build_options file in the build directory instead of being inferred from the name of the build directory. Options are passed to C++ via config/*.hh files instead of via the command line. Build option flags are now always defined to 0 or 1, so checks must use '#if' rather than '#ifdef'. SConscript: MySQL detection moved to SConstruct. Add config/*.hh files (via ConfigFile builder). arch/alpha/alpha_memory.cc: arch/alpha/ev5.cc: arch/alpha/ev5.hh: arch/alpha/isa_traits.hh: base/fast_alloc.hh: base/statistics.cc: base/statistics.hh: base/stats/events.cc: base/stats/events.hh: cpu/base.cc: cpu/base.hh: cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: cpu/exec_context.cc: cpu/exec_context.hh: cpu/o3/alpha_cpu.hh: cpu/o3/alpha_cpu_builder.cc: cpu/o3/alpha_cpu_impl.hh: cpu/o3/alpha_dyn_inst.hh: cpu/o3/alpha_dyn_inst_impl.hh: cpu/o3/alpha_params.hh: cpu/o3/commit_impl.hh: cpu/o3/cpu.cc: cpu/o3/cpu.hh: cpu/o3/fetch_impl.hh: cpu/o3/iew.hh: cpu/o3/iew_impl.hh: cpu/o3/regfile.hh: cpu/o3/rename_impl.hh: cpu/o3/rob_impl.hh: cpu/ozone/cpu.hh: cpu/pc_event.cc: cpu/simple/cpu.cc: cpu/simple/cpu.hh: sim/process.cc: sim/process.hh: Convert compile flags from def/undef to 0/1. Set via #include config/*.hh instead of command line. arch/alpha/isa_desc: Convert compile flags from def/undef to 0/1. Set via #include config/*.hh instead of command line. Revamp fenv.h support... most of the ugliness is hidden in base/fenv.hh now. base/mysql.hh: Fix typo in #ifndef guard. build/SConstruct: Build options are set via a build_options file in the build directory instead of being inferred from the name of the build directory. Options are passed to C++ via config/*.hh files instead of via the command line. python/SConscript: Generate m5_build_env directly from scons options instead of indirectly via CPPDEFINES. python/m5/convert.py: Allow '0' and '1' for booleans. Rewrite toBool to use dict. base/fenv.hh: Revamp <fenv.h> support to make it a compile option (so we can test w/o it even if it's present) and to make isa_desc cleaner. --HG-- extra : convert_revision : 8f97dc11185bef5e1865b3269c7341df8525c9ad
2005-08-30 19:18:54 +02:00
if env['USE_MYSQL']:
sources += mysql_sources
Build options are set via a build_options file in the build directory instead of being inferred from the name of the build directory. Options are passed to C++ via config/*.hh files instead of via the command line. Build option flags are now always defined to 0 or 1, so checks must use '#if' rather than '#ifdef'. SConscript: MySQL detection moved to SConstruct. Add config/*.hh files (via ConfigFile builder). arch/alpha/alpha_memory.cc: arch/alpha/ev5.cc: arch/alpha/ev5.hh: arch/alpha/isa_traits.hh: base/fast_alloc.hh: base/statistics.cc: base/statistics.hh: base/stats/events.cc: base/stats/events.hh: cpu/base.cc: cpu/base.hh: cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: cpu/exec_context.cc: cpu/exec_context.hh: cpu/o3/alpha_cpu.hh: cpu/o3/alpha_cpu_builder.cc: cpu/o3/alpha_cpu_impl.hh: cpu/o3/alpha_dyn_inst.hh: cpu/o3/alpha_dyn_inst_impl.hh: cpu/o3/alpha_params.hh: cpu/o3/commit_impl.hh: cpu/o3/cpu.cc: cpu/o3/cpu.hh: cpu/o3/fetch_impl.hh: cpu/o3/iew.hh: cpu/o3/iew_impl.hh: cpu/o3/regfile.hh: cpu/o3/rename_impl.hh: cpu/o3/rob_impl.hh: cpu/ozone/cpu.hh: cpu/pc_event.cc: cpu/simple/cpu.cc: cpu/simple/cpu.hh: sim/process.cc: sim/process.hh: Convert compile flags from def/undef to 0/1. Set via #include config/*.hh instead of command line. arch/alpha/isa_desc: Convert compile flags from def/undef to 0/1. Set via #include config/*.hh instead of command line. Revamp fenv.h support... most of the ugliness is hidden in base/fenv.hh now. base/mysql.hh: Fix typo in #ifndef guard. build/SConstruct: Build options are set via a build_options file in the build directory instead of being inferred from the name of the build directory. Options are passed to C++ via config/*.hh files instead of via the command line. python/SConscript: Generate m5_build_env directly from scons options instead of indirectly via CPPDEFINES. python/m5/convert.py: Allow '0' and '1' for booleans. Rewrite toBool to use dict. base/fenv.hh: Revamp <fenv.h> support to make it a compile option (so we can test w/o it even if it's present) and to make isa_desc cleaner. --HG-- extra : convert_revision : 8f97dc11185bef5e1865b3269c7341df8525c9ad
2005-08-30 19:18:54 +02:00
for opt in env.ExportOptions:
env.ConfigFile(opt)
###################################################
#
# Special build rules.
#
###################################################
# base/traceflags.{cc,hh} are generated from base/traceflags.py.
# $TARGET.base will expand to "<build-dir>/base/traceflags".
env.Command(Split('base/traceflags.hh base/traceflags.cc'),
'base/traceflags.py',
'python $SOURCE $TARGET.base')
# libelf build is described in its own SConscript file.
# SConscript-local is the per-config build, which just copies some
# header files into a place where they can be found.
SConscript('libelf/SConscript-local', exports = 'env', duplicate=0)
stick all python stuff into a top level python directory. create an m5 package in python/m5 move the objects package into the m5 package move the m5config into the m5 package as config leave both importers outside of the package. SConscript: sim/main.cc: move sim/pyconfig/* -> python python/SConscript: m5config.py -> m5/config.py (now automatically embedded) objects -> python/m5/objects embed all python files in python/m5 python/m5/config.py: importer renamed mpy_importer move code to m5/__init__.py test/genini.py: deal with new python organization keep track of paths we want to add and add them after parameters are parsed. --HG-- rename : sim/pyconfig/SConscript => python/SConscript rename : sim/pyconfig/m5config.py => python/m5/config.py rename : objects/AlphaConsole.mpy => python/m5/objects/AlphaConsole.mpy rename : objects/AlphaTLB.mpy => python/m5/objects/AlphaTLB.mpy rename : objects/BadDevice.mpy => python/m5/objects/BadDevice.mpy rename : objects/BaseCPU.mpy => python/m5/objects/BaseCPU.mpy rename : objects/BaseCache.mpy => python/m5/objects/BaseCache.mpy rename : objects/BaseSystem.mpy => python/m5/objects/BaseSystem.mpy rename : objects/Bus.mpy => python/m5/objects/Bus.mpy rename : objects/CoherenceProtocol.mpy => python/m5/objects/CoherenceProtocol.mpy rename : objects/Device.mpy => python/m5/objects/Device.mpy rename : objects/DiskImage.mpy => python/m5/objects/DiskImage.mpy rename : objects/Ethernet.mpy => python/m5/objects/Ethernet.mpy rename : objects/Ide.mpy => python/m5/objects/Ide.mpy rename : objects/IntrControl.mpy => python/m5/objects/IntrControl.mpy rename : objects/MemTest.mpy => python/m5/objects/MemTest.mpy rename : objects/Pci.mpy => python/m5/objects/Pci.mpy rename : objects/PhysicalMemory.mpy => python/m5/objects/PhysicalMemory.mpy rename : objects/Platform.mpy => python/m5/objects/Platform.mpy rename : objects/Process.mpy => python/m5/objects/Process.mpy rename : objects/Repl.mpy => python/m5/objects/Repl.mpy rename : objects/Root.mpy => python/m5/objects/Root.mpy rename : objects/SimConsole.mpy => python/m5/objects/SimConsole.mpy rename : objects/SimpleDisk.mpy => python/m5/objects/SimpleDisk.mpy rename : objects/Tsunami.mpy => python/m5/objects/Tsunami.mpy rename : objects/Uart.mpy => python/m5/objects/Uart.mpy extra : convert_revision : aebf6ccda33028b1125974ca8b6aeab6f7570f30
2005-03-12 00:28:38 +01:00
SConscript('python/SConscript', exports = ['env'], duplicate=0)
# This function adds the specified sources to the given build
# environment, and returns a list of all the corresponding SCons
# Object nodes (including an extra one for date.cc). We explicitly
# add the Object nodes so we can set up special dependencies for
# date.cc.
def make_objs(sources, env):
objs = [env.Object(s) for s in sources]
# make date.cc depend on all other objects so it always gets
# recompiled whenever anything else does
date_obj = env.Object('base/date.cc')
env.Depends(date_obj, objs)
objs.append(date_obj)
return objs
###################################################
#
# Define binaries. Each different build type (debug, opt, etc.) gets
# a slightly different build environment.
#
###################################################
# Include file paths are rooted in this directory. SCons will
# automatically expand '.' to refer to both the source directory and
# the corresponding build directory to pick up generated include
# files.
env.Append(CPPPATH='.')
# Debug binary
debugEnv = env.Copy(OBJSUFFIX='.do')
debugEnv.Label = 'debug'
debugEnv.Append(CCFLAGS=Split('-g -gstabs+ -O0'))
debugEnv.Append(CPPDEFINES='DEBUG')
tlist = debugEnv.Program(target = 'm5.debug',
source = make_objs(sources, debugEnv))
debugEnv.M5Binary = tlist[0]
# Optimized binary
optEnv = env.Copy()
optEnv.Label = 'opt'
optEnv.Append(CCFLAGS=Split('-g -O5'))
tlist = optEnv.Program(target = 'm5.opt',
source = make_objs(sources, optEnv))
optEnv.M5Binary = tlist[0]
# "Fast" binary
fastEnv = env.Copy(OBJSUFFIX='.fo')
fastEnv.Label = 'fast'
fastEnv.Append(CCFLAGS=Split('-O5'))
fastEnv.Append(CPPDEFINES='NDEBUG')
fastEnv.Program(target = 'm5.fast.unstripped',
source = make_objs(sources, fastEnv))
tlist = fastEnv.Command(target = 'm5.fast',
source = 'm5.fast.unstripped',
action = 'strip $SOURCE -o $TARGET')
fastEnv.M5Binary = tlist[0]
# Profiled binary
profEnv = env.Copy(OBJSUFFIX='.po')
profEnv.Label = 'prof'
profEnv.Append(CCFLAGS=Split('-O5 -g -pg'), LINKFLAGS='-pg')
tlist = profEnv.Program(target = 'm5.prof',
source = make_objs(sources, profEnv))
profEnv.M5Binary = tlist[0]
envList = [debugEnv, optEnv, fastEnv, profEnv]
Return('envList')