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Various changes to I/O, addition of PciFake device to improve FreeBSD compatibility.

Browse source 
SConscript:
    Include pcifake.cc, fix spacing.
dev/ide_ctrl.cc:
    Consolidate switch-case blocks.
dev/ide_disk.cc:
    Add comments.
dev/pciconfigall.cc:
    Adjust spacing.
dev/pcidev.cc:
    Adjust spacing, rearrange code.
dev/tsunami_io.cc:
    Rearrange code.
dev/uart8250.cc:
    Switch uart interrupt interval back to original value.
python/m5/objects/Pci.py:
    Add PciFake class to be used as a PCI-ISA bridge device.

--HG--
extra : convert_revision : 8aea94318510079a310377f297aa161ba5f7864c
This commit is contained in:
Benjamin Nash 2005-07-26 12:28:33 -04:00
parent 32b52fe712
commit 6e0ad62fdc
8 changed files with 52 additions and 50 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
SConscript
View file

@ -265,8 +265,9 @@ full_system_sources = Split('''
dev/ns_gige.cc
dev/pciconfigall.cc
dev/pcidev.cc
dev/pcifake.cc
dev/pktfifo.cc
dev/platform.cc
dev/platform.cc
dev/sinic.cc
dev/simple_disk.cc
dev/tsunami.cc

46
dev/ide_ctrl.cc
View file

@ -268,25 +268,19 @@ IdeController::ReadConfig(int offset, int size, uint8_t *data)
switch (size) {
case sizeof(uint8_t):
case sizeof(uint16_t):
case sizeof(uint32_t):
memcpy(&byte, &pci_config_regs.data[config_offset], size);
break;
default:
panic("Invalid PCI configuration read size!\n");
}
switch (size) {
case sizeof(uint8_t):
*data = byte;
break;
case sizeof(uint16_t):
memcpy(&byte, &pci_config_regs.data[config_offset], size);
*(uint16_t*)data = htoa(word);
break;
case sizeof(uint32_t):
memcpy(&byte, &pci_config_regs.data[config_offset], size);
*(uint32_t*)data = htoa(dword);
break;
default:
panic("Invalid PCI configuration read size!\n");
}
DPRINTF(IdeCtrl, "PCI read offset: %#x size: %#x data: %#x\n",
@ -407,40 +401,48 @@ IdeController::read(MemReqPtr &req, uint8_t *data)
RegType_t type;
int disk;
/* union
* +-- --+-- --+-- --+-- --+
* | 0 | 1 | 2 | 3 |
* +-- --+-- --+-- --+-- --+
* | byte | .. | .. | .. |
* +-- --+-- --+-- --+-- --+
* | word0 | word1 |
* +-- --+-- --+
* | dword |
* +-- --+
*/
union {
uint8_t byte;
uint16_t word[2];
uint32_t dword;
};
dword = 0;
parseAddr(req->paddr, offset, primary, type);
if (!io_enabled)
return No_Fault;
// sanity check the size (allows byte, word, or dword access)
switch (req->size) {
case sizeof(uint8_t):
case sizeof(uint16_t):
case sizeof(uint32_t):
break;
default:
panic("IDE controller read of invalid size: %#x\n", req->size);
}
switch (type) {
case BMI_BLOCK:
memcpy(&byte, &bmi_regs[offset], req->size);
switch (req->size) {
case sizeof(uint8_t):
memcpy(&byte, &bmi_regs[offset], sizeof(uint8_t));
*data = byte;
break;
case sizeof(uint16_t):
memcpy(&byte, &bmi_regs[offset], sizeof(uint16_t));
*(uint16_t*)data = htoa(word[0]);
break;
case sizeof(uint32_t):
memcpy(&byte, &bmi_regs[offset], sizeof(uint32_t));
*(uint32_t*)data = htoa(dword);
break;
default:
panic("IDE read of BMI reg invalid size: %#x\n", req->size);
}
break;
@ -499,7 +501,7 @@ IdeController::write(MemReqPtr &req, const uint8_t *data)
byte = (req->size == sizeof(uint8_t)) ? true : false;
cmdBlk = (type == COMMAND_BLOCK) ? true : false;
DPRINTF(IdeCtrl, "write from offset: %#x size: %#x data: %#x\n",
DPRINTF(IdeCtrl, "write to offset: %#x size: %#x data: %#x\n",
offset, req->size,
(*(uint32_t *)data) & (0xffffffff >> 8 * (4 - req->size)));

4
dev/ide_disk.cc
View file

@ -226,10 +226,10 @@ IdeDisk::read(const Addr &offset, RegType_t type, uint8_t *data)
switch (offset) {
// Data transfers occur 16 bits at a time
case DATA_OFFSET:
// use memcpy to preserve little-endianess
// use memcpy to preserve IDE's little-endianess
memcpy(data, &cmdReg.data, sizeof(uint16_t));
break;
// All other transfers are 8 bit
// All other transfers are 8-bit
case ERROR_OFFSET:
*data = cmdReg.error;
break;

4
dev/pciconfigall.cc
View file

@ -159,10 +159,10 @@ PciConfigAll::write(MemReqPtr &req, const uint8_t *data)
else {
switch (req->size) {
case sizeof(uint8_t):
word_value = *(uint8_t*)data & 0x000000FF;
word_value = *(uint8_t*)data;
break;
case sizeof(uint16_t):
word_value = *(uint16_t*)data & 0x0000FFFF;
word_value = *(uint16_t*)data;
break;
case sizeof(uint32_t):
word_value = *(uint32_t*)data;

33
dev/pcidev.cc
View file

@ -74,37 +74,31 @@ void
PciDev::ReadConfig(int offset, int size, uint8_t *data)
{
union {
uint8_t byte;
uint16_t word;
uint32_t dword;
uint8_t byte;
uint16_t word;
uint32_t dword;
};
dword = 0;
if (offset >= PCI_DEVICE_SPECIFIC)
panic("Device specific PCI config space not implemented!\n");
dword = 0;
switch(size) {
case sizeof(uint8_t):
case sizeof(uint16_t):
case sizeof(uint32_t):
memcpy(&byte, &config.data[offset], size);
break;
default:
panic("Invalid PCI configuration read size!\n");
}
switch(size) {
case sizeof(uint8_t):
*data = byte;
break;
case sizeof(uint16_t):
memcpy(&byte, &config.data[offset], size);
*(uint16_t*)data = htoa(word);
break;
case sizeof(uint32_t):
memcpy(&byte, &config.data[offset], size);
*(uint32_t*)data = htoa(dword);
break;
default:
panic("Invalid PCI configuration read size!\n");
}
DPRINTF(PCIDEV,
@ -121,9 +115,9 @@ PciDev::WriteConfig(int offset, int size, uint32_t data)
uint32_t barnum;
uint8_t byte_value = data;
uint16_t half_value = data;
uint32_t word_value = data;
uint8_t byte_value;
uint16_t half_value;
uint32_t word_value;
DPRINTF(PCIDEV,
"write device: %#x function: %#x reg: %#x size: %d data: %#x\n",
@ -134,6 +128,7 @@ PciDev::WriteConfig(int offset, int size, uint32_t data)
switch (size) {
case sizeof(uint8_t): // 1-byte access
byte_value = data;
switch (offset) {
case PCI0_INTERRUPT_LINE:
case PCI_CACHE_LINE_SIZE:
@ -153,6 +148,7 @@ PciDev::WriteConfig(int offset, int size, uint32_t data)
break;
case sizeof(uint16_t): // 2-byte access
half_value = data;
switch (offset) {
case PCI_COMMAND:
case PCI_STATUS:
@ -166,6 +162,7 @@ PciDev::WriteConfig(int offset, int size, uint32_t data)
break;
case sizeof(uint32_t): // 4-byte access
word_value = data;
switch (offset) {
case PCI0_BASE_ADDR0:
case PCI0_BASE_ADDR1:

7
dev/tsunami_io.cc
View file

@ -75,7 +75,6 @@ TsunamiIO::RTCEvent::process()
tm.tm_sec = (tm.tm_sec + 1) % 60;
intr_count = (intr_count + 1) % 1024;
}
const char *
@ -316,15 +315,15 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data)
return No_Fault;
case RTC_CNTRL_REGD:
panic("RTC Control Register D not implemented");
case RTC_SEC:
*(uint8_t *)data = tm.tm_sec;
return No_Fault;
case RTC_SEC_ALRM:
case RTC_MIN_ALRM:
case RTC_HR_ALRM:
// RTC alarm functionality is not currently implemented
*(uint8_t *)data = 0x00;
return No_Fault;
case RTC_SEC:
*(uint8_t *)data = tm.tm_sec;
return No_Fault;
case RTC_MIN:
*(uint8_t *)data = tm.tm_min;
return No_Fault;

2
dev/uart8250.cc
View file

@ -88,7 +88,7 @@ Uart8250::IntrEvent::process()
void
Uart8250::IntrEvent::scheduleIntr()
{
static const Tick interval = (Tick)((Clock::Float::s / 2e9) * 600);
static const Tick interval = (Tick)((Clock::Float::s / 2e9) * 450);
DPRINTF(Uart, "Scheduling IER interrupt for %#x, at cycle %lld\n", intrBit,
curTick + interval);
if (!scheduled())

3
python/m5/objects/Pci.py
View file

@ -50,3 +50,6 @@ class PciDevice(DmaDevice):
pci_func = Param.Int("PCI function code")
configdata = Param.PciConfigData(Parent.any, "PCI Config data")
configspace = Param.PciConfigAll(Parent.any, "PCI Configspace")
class PciFake(PciDevice):
type = 'PciFake'