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gem5/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt

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Add short memtest run to quick regressions. Caveats: - Even though memtest is ISA-independent, it will only run for the Alpha builds, since there's no way to specify ISA-independent reference files and I didn't want to commit 3 copies since I'm not sure we want to run it for all the different ISAs anyway. - Reference outputs were generated on my laptop, so performance numbers will be low compared to zizzer. --HG-- extra : convert_revision : 210fe4abecc19fbab0b15402c6cb4863650bab66
2007-02-07 06:16:33 +01:00
---------- Begin Simulation Statistics ----------
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
sim_seconds 0.000667 # Number of seconds simulated
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
sim_ticks 667077000 # Number of ticks simulated
final_tick 667077000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
host_tick_rate 152389795 # Simulator tick rate (ticks/s)
host_mem_usage 222064 # Number of bytes of host memory used
host_seconds 4.38 # Real time elapsed on the host
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.physmem.bytes_read::cpu0 82891 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1 81142 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2 81431 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3 77551 # Number of bytes read from this memory
system.physmem.bytes_read::cpu4 82816 # Number of bytes read from this memory
system.physmem.bytes_read::cpu5 77581 # Number of bytes read from this memory
system.physmem.bytes_read::cpu6 78240 # Number of bytes read from this memory
system.physmem.bytes_read::cpu7 78400 # Number of bytes read from this memory
system.physmem.bytes_read::total 640052 # Number of bytes read from this memory
system.physmem.bytes_written::writebacks 398656 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0 5460 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1 5632 # Number of bytes written to this memory
system.physmem.bytes_written::cpu2 5599 # Number of bytes written to this memory
system.physmem.bytes_written::cpu3 5418 # Number of bytes written to this memory
system.physmem.bytes_written::cpu4 5496 # Number of bytes written to this memory
system.physmem.bytes_written::cpu5 5436 # Number of bytes written to this memory
system.physmem.bytes_written::cpu6 5531 # Number of bytes written to this memory
system.physmem.bytes_written::cpu7 5426 # Number of bytes written to this memory
system.physmem.bytes_written::total 442654 # Number of bytes written to this memory
system.physmem.num_reads::cpu0 11008 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1 10834 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2 10745 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3 10897 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu4 10996 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu5 10990 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu6 10956 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu7 10927 # Number of read requests responded to by this memory
system.physmem.num_reads::total 87353 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 6229 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0 5460 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1 5632 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu2 5599 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu3 5418 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu4 5496 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu5 5436 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu6 5531 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu7 5426 # Number of write requests responded to by this memory
system.physmem.num_writes::total 50227 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0 124260018 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1 121638132 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2 122071365 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3 116254945 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu4 124147587 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu5 116299917 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu6 117287809 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu7 117527662 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 959487435 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 597616167 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0 8184962 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1 8442803 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu2 8393334 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu3 8122001 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu4 8238929 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu5 8148984 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu6 8291397 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu7 8133994 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 663572571 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 597616167 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0 132444980 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1 130080935 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2 130464699 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3 124376946 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu4 132386516 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu5 124448902 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu6 125579206 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu7 125661655 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1623060007 # Total bandwidth to/from this memory (bytes/s)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu0.num_reads 100000 # number of read accesses completed
system.cpu0.num_writes 55151 # number of write accesses completed
system.cpu0.l1c.tags.replacements 22523 # number of replacements
system.cpu0.l1c.tags.tagsinuse 393.206747 # Cycle average of tags in use
system.cpu0.l1c.tags.total_refs 13668 # Total number of references to valid blocks.
system.cpu0.l1c.tags.sampled_refs 22921 # Sample count of references to valid blocks.
system.cpu0.l1c.tags.avg_refs 0.596309 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu0.l1c.tags.occ_blocks::cpu0 393.206747 # Average occupied blocks per requestor
system.cpu0.l1c.tags.occ_percent::cpu0 0.767982 # Average percentage of cache occupancy
system.cpu0.l1c.tags.occ_percent::total 0.767982 # Average percentage of cache occupancy
system.cpu0.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id
system.cpu0.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id
system.cpu0.l1c.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
system.cpu0.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id
system.cpu0.l1c.tags.tag_accesses 338453 # Number of tag accesses
system.cpu0.l1c.tags.data_accesses 338453 # Number of data accesses
system.cpu0.l1c.ReadReq_hits::cpu0 8785 # number of ReadReq hits
system.cpu0.l1c.ReadReq_hits::total 8785 # number of ReadReq hits
system.cpu0.l1c.WriteReq_hits::cpu0 1208 # number of WriteReq hits
system.cpu0.l1c.WriteReq_hits::total 1208 # number of WriteReq hits
system.cpu0.l1c.demand_hits::cpu0 9993 # number of demand (read+write) hits
system.cpu0.l1c.demand_hits::total 9993 # number of demand (read+write) hits
system.cpu0.l1c.overall_hits::cpu0 9993 # number of overall hits
system.cpu0.l1c.overall_hits::total 9993 # number of overall hits
system.cpu0.l1c.ReadReq_misses::cpu0 36702 # number of ReadReq misses
system.cpu0.l1c.ReadReq_misses::total 36702 # number of ReadReq misses
system.cpu0.l1c.WriteReq_misses::cpu0 23741 # number of WriteReq misses
system.cpu0.l1c.WriteReq_misses::total 23741 # number of WriteReq misses
system.cpu0.l1c.demand_misses::cpu0 60443 # number of demand (read+write) misses
system.cpu0.l1c.demand_misses::total 60443 # number of demand (read+write) misses
system.cpu0.l1c.overall_misses::cpu0 60443 # number of overall misses
system.cpu0.l1c.overall_misses::total 60443 # number of overall misses
system.cpu0.l1c.ReadReq_miss_latency::cpu0 964033198 # number of ReadReq miss cycles
system.cpu0.l1c.ReadReq_miss_latency::total 964033198 # number of ReadReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::cpu0 878854454 # number of WriteReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::total 878854454 # number of WriteReq miss cycles
system.cpu0.l1c.demand_miss_latency::cpu0 1842887652 # number of demand (read+write) miss cycles
system.cpu0.l1c.demand_miss_latency::total 1842887652 # number of demand (read+write) miss cycles
system.cpu0.l1c.overall_miss_latency::cpu0 1842887652 # number of overall miss cycles
system.cpu0.l1c.overall_miss_latency::total 1842887652 # number of overall miss cycles
system.cpu0.l1c.ReadReq_accesses::cpu0 45487 # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.ReadReq_accesses::total 45487 # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::cpu0 24949 # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::total 24949 # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.demand_accesses::cpu0 70436 # number of demand (read+write) accesses
system.cpu0.l1c.demand_accesses::total 70436 # number of demand (read+write) accesses
system.cpu0.l1c.overall_accesses::cpu0 70436 # number of overall (read+write) accesses
system.cpu0.l1c.overall_accesses::total 70436 # number of overall (read+write) accesses
system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.806868 # miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_miss_rate::total 0.806868 # miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.951581 # miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_miss_rate::total 0.951581 # miss rate for WriteReq accesses
system.cpu0.l1c.demand_miss_rate::cpu0 0.858127 # miss rate for demand accesses
system.cpu0.l1c.demand_miss_rate::total 0.858127 # miss rate for demand accesses
system.cpu0.l1c.overall_miss_rate::cpu0 0.858127 # miss rate for overall accesses
system.cpu0.l1c.overall_miss_rate::total 0.858127 # miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 26266.503133 # average ReadReq miss latency
system.cpu0.l1c.ReadReq_avg_miss_latency::total 26266.503133 # average ReadReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 37018.426098 # average WriteReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::total 37018.426098 # average WriteReq miss latency
system.cpu0.l1c.demand_avg_miss_latency::cpu0 30489.678739 # average overall miss latency
system.cpu0.l1c.demand_avg_miss_latency::total 30489.678739 # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::cpu0 30489.678739 # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::total 30489.678739 # average overall miss latency
system.cpu0.l1c.blocked_cycles::no_mshrs 1018774 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu0.l1c.blocked::no_mshrs 63007 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu0.l1c.avg_blocked_cycles::no_mshrs 16.169219 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.l1c.fast_writes 0 # number of fast writes performed
system.cpu0.l1c.cache_copies 0 # number of cache copies performed
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu0.l1c.writebacks::writebacks 9806 # number of writebacks
system.cpu0.l1c.writebacks::total 9806 # number of writebacks
system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36702 # number of ReadReq MSHR misses
system.cpu0.l1c.ReadReq_mshr_misses::total 36702 # number of ReadReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23741 # number of WriteReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::total 23741 # number of WriteReq MSHR misses
system.cpu0.l1c.demand_mshr_misses::cpu0 60443 # number of demand (read+write) MSHR misses
system.cpu0.l1c.demand_mshr_misses::total 60443 # number of demand (read+write) MSHR misses
system.cpu0.l1c.overall_mshr_misses::cpu0 60443 # number of overall MSHR misses
system.cpu0.l1c.overall_mshr_misses::total 60443 # number of overall MSHR misses
system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 885636434 # number of ReadReq MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_miss_latency::total 885636434 # number of ReadReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 828679478 # number of WriteReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::total 828679478 # number of WriteReq MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1714315912 # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::total 1714315912 # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1714315912 # number of overall MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::total 1714315912 # number of overall MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 700887059 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 700887059 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 1711925608 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 1711925608 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2412812667 # number of overall MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2412812667 # number of overall MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.806868 # mshr miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.806868 # mshr miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.951581 # mshr miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.951581 # mshr miss rate for WriteReq accesses
system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.858127 # mshr miss rate for demand accesses
system.cpu0.l1c.demand_mshr_miss_rate::total 0.858127 # mshr miss rate for demand accesses
system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.858127 # mshr miss rate for overall accesses
system.cpu0.l1c.overall_mshr_miss_rate::total 0.858127 # mshr miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 24130.467931 # average ReadReq mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 24130.467931 # average ReadReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 34904.994651 # average WriteReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 34904.994651 # average WriteReq mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 28362.521913 # average overall mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::total 28362.521913 # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 28362.521913 # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::total 28362.521913 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu1.num_reads 99761 # number of read accesses completed
system.cpu1.num_writes 55328 # number of write accesses completed
system.cpu1.l1c.tags.replacements 22642 # number of replacements
system.cpu1.l1c.tags.tagsinuse 394.589952 # Cycle average of tags in use
system.cpu1.l1c.tags.total_refs 13581 # Total number of references to valid blocks.
system.cpu1.l1c.tags.sampled_refs 23033 # Sample count of references to valid blocks.
system.cpu1.l1c.tags.avg_refs 0.589632 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu1.l1c.tags.occ_blocks::cpu1 394.589952 # Average occupied blocks per requestor
system.cpu1.l1c.tags.occ_percent::cpu1 0.770684 # Average percentage of cache occupancy
system.cpu1.l1c.tags.occ_percent::total 0.770684 # Average percentage of cache occupancy
system.cpu1.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id
system.cpu1.l1c.tags.age_task_id_blocks_1024::0 376 # Occupied blocks per task id
system.cpu1.l1c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id
system.cpu1.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id
system.cpu1.l1c.tags.tag_accesses 339246 # Number of tag accesses
system.cpu1.l1c.tags.data_accesses 339246 # Number of data accesses
system.cpu1.l1c.ReadReq_hits::cpu1 8788 # number of ReadReq hits
system.cpu1.l1c.ReadReq_hits::total 8788 # number of ReadReq hits
system.cpu1.l1c.WriteReq_hits::cpu1 1121 # number of WriteReq hits
system.cpu1.l1c.WriteReq_hits::total 1121 # number of WriteReq hits
system.cpu1.l1c.demand_hits::cpu1 9909 # number of demand (read+write) hits
system.cpu1.l1c.demand_hits::total 9909 # number of demand (read+write) hits
system.cpu1.l1c.overall_hits::cpu1 9909 # number of overall hits
system.cpu1.l1c.overall_hits::total 9909 # number of overall hits
system.cpu1.l1c.ReadReq_misses::cpu1 36866 # number of ReadReq misses
system.cpu1.l1c.ReadReq_misses::total 36866 # number of ReadReq misses
system.cpu1.l1c.WriteReq_misses::cpu1 23806 # number of WriteReq misses
system.cpu1.l1c.WriteReq_misses::total 23806 # number of WriteReq misses
system.cpu1.l1c.demand_misses::cpu1 60672 # number of demand (read+write) misses
system.cpu1.l1c.demand_misses::total 60672 # number of demand (read+write) misses
system.cpu1.l1c.overall_misses::cpu1 60672 # number of overall misses
system.cpu1.l1c.overall_misses::total 60672 # number of overall misses
system.cpu1.l1c.ReadReq_miss_latency::cpu1 969094954 # number of ReadReq miss cycles
system.cpu1.l1c.ReadReq_miss_latency::total 969094954 # number of ReadReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::cpu1 879252966 # number of WriteReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::total 879252966 # number of WriteReq miss cycles
system.cpu1.l1c.demand_miss_latency::cpu1 1848347920 # number of demand (read+write) miss cycles
system.cpu1.l1c.demand_miss_latency::total 1848347920 # number of demand (read+write) miss cycles
system.cpu1.l1c.overall_miss_latency::cpu1 1848347920 # number of overall miss cycles
system.cpu1.l1c.overall_miss_latency::total 1848347920 # number of overall miss cycles
system.cpu1.l1c.ReadReq_accesses::cpu1 45654 # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.ReadReq_accesses::total 45654 # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::cpu1 24927 # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::total 24927 # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.demand_accesses::cpu1 70581 # number of demand (read+write) accesses
system.cpu1.l1c.demand_accesses::total 70581 # number of demand (read+write) accesses
system.cpu1.l1c.overall_accesses::cpu1 70581 # number of overall (read+write) accesses
system.cpu1.l1c.overall_accesses::total 70581 # number of overall (read+write) accesses
system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.807509 # miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_miss_rate::total 0.807509 # miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.955029 # miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_miss_rate::total 0.955029 # miss rate for WriteReq accesses
system.cpu1.l1c.demand_miss_rate::cpu1 0.859608 # miss rate for demand accesses
system.cpu1.l1c.demand_miss_rate::total 0.859608 # miss rate for demand accesses
system.cpu1.l1c.overall_miss_rate::cpu1 0.859608 # miss rate for overall accesses
system.cpu1.l1c.overall_miss_rate::total 0.859608 # miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 26286.956925 # average ReadReq miss latency
system.cpu1.l1c.ReadReq_avg_miss_latency::total 26286.956925 # average ReadReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 36934.090817 # average WriteReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::total 36934.090817 # average WriteReq miss latency
system.cpu1.l1c.demand_avg_miss_latency::cpu1 30464.595200 # average overall miss latency
system.cpu1.l1c.demand_avg_miss_latency::total 30464.595200 # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::cpu1 30464.595200 # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::total 30464.595200 # average overall miss latency
system.cpu1.l1c.blocked_cycles::no_mshrs 1015089 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu1.l1c.blocked::no_mshrs 62996 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu1.l1c.avg_blocked_cycles::no_mshrs 16.113547 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.l1c.fast_writes 0 # number of fast writes performed
system.cpu1.l1c.cache_copies 0 # number of cache copies performed
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu1.l1c.writebacks::writebacks 9956 # number of writebacks
system.cpu1.l1c.writebacks::total 9956 # number of writebacks
system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36866 # number of ReadReq MSHR misses
system.cpu1.l1c.ReadReq_mshr_misses::total 36866 # number of ReadReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23806 # number of WriteReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::total 23806 # number of WriteReq MSHR misses
system.cpu1.l1c.demand_mshr_misses::cpu1 60672 # number of demand (read+write) MSHR misses
system.cpu1.l1c.demand_mshr_misses::total 60672 # number of demand (read+write) MSHR misses
system.cpu1.l1c.overall_mshr_misses::cpu1 60672 # number of overall MSHR misses
system.cpu1.l1c.overall_mshr_misses::total 60672 # number of overall MSHR misses
system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 890415084 # number of ReadReq MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_miss_latency::total 890415084 # number of ReadReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 828850208 # number of WriteReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::total 828850208 # number of WriteReq MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1719265292 # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::total 1719265292 # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1719265292 # number of overall MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::total 1719265292 # number of overall MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 690509167 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 690509167 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 1720529946 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 1720529946 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2411039113 # number of overall MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2411039113 # number of overall MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.807509 # mshr miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.807509 # mshr miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.955029 # mshr miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.955029 # mshr miss rate for WriteReq accesses
system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.859608 # mshr miss rate for demand accesses
system.cpu1.l1c.demand_mshr_miss_rate::total 0.859608 # mshr miss rate for demand accesses
system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859608 # mshr miss rate for overall accesses
system.cpu1.l1c.overall_mshr_miss_rate::total 0.859608 # mshr miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 24152.744643 # average ReadReq mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 24152.744643 # average ReadReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 34816.861632 # average WriteReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 34816.861632 # average WriteReq mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 28337.046611 # average overall mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::total 28337.046611 # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 28337.046611 # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::total 28337.046611 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu2.num_reads 99243 # number of read accesses completed
system.cpu2.num_writes 55132 # number of write accesses completed
system.cpu2.l1c.tags.replacements 22573 # number of replacements
system.cpu2.l1c.tags.tagsinuse 394.676253 # Cycle average of tags in use
system.cpu2.l1c.tags.total_refs 13694 # Total number of references to valid blocks.
system.cpu2.l1c.tags.sampled_refs 22978 # Sample count of references to valid blocks.
system.cpu2.l1c.tags.avg_refs 0.595961 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu2.l1c.tags.occ_blocks::cpu2 394.676253 # Average occupied blocks per requestor
system.cpu2.l1c.tags.occ_percent::cpu2 0.770852 # Average percentage of cache occupancy
system.cpu2.l1c.tags.occ_percent::total 0.770852 # Average percentage of cache occupancy
system.cpu2.l1c.tags.occ_task_id_blocks::1024 405 # Occupied blocks per task id
system.cpu2.l1c.tags.age_task_id_blocks_1024::0 383 # Occupied blocks per task id
system.cpu2.l1c.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
system.cpu2.l1c.tags.occ_task_id_percent::1024 0.791016 # Percentage of cache occupancy per task id
system.cpu2.l1c.tags.tag_accesses 338823 # Number of tag accesses
system.cpu2.l1c.tags.data_accesses 338823 # Number of data accesses
system.cpu2.l1c.ReadReq_hits::cpu2 8940 # number of ReadReq hits
system.cpu2.l1c.ReadReq_hits::total 8940 # number of ReadReq hits
system.cpu2.l1c.WriteReq_hits::cpu2 1180 # number of WriteReq hits
system.cpu2.l1c.WriteReq_hits::total 1180 # number of WriteReq hits
system.cpu2.l1c.demand_hits::cpu2 10120 # number of demand (read+write) hits
system.cpu2.l1c.demand_hits::total 10120 # number of demand (read+write) hits
system.cpu2.l1c.overall_hits::cpu2 10120 # number of overall hits
system.cpu2.l1c.overall_hits::total 10120 # number of overall hits
system.cpu2.l1c.ReadReq_misses::cpu2 36529 # number of ReadReq misses
system.cpu2.l1c.ReadReq_misses::total 36529 # number of ReadReq misses
system.cpu2.l1c.WriteReq_misses::cpu2 23864 # number of WriteReq misses
system.cpu2.l1c.WriteReq_misses::total 23864 # number of WriteReq misses
system.cpu2.l1c.demand_misses::cpu2 60393 # number of demand (read+write) misses
system.cpu2.l1c.demand_misses::total 60393 # number of demand (read+write) misses
system.cpu2.l1c.overall_misses::cpu2 60393 # number of overall misses
system.cpu2.l1c.overall_misses::total 60393 # number of overall misses
system.cpu2.l1c.ReadReq_miss_latency::cpu2 963156898 # number of ReadReq miss cycles
system.cpu2.l1c.ReadReq_miss_latency::total 963156898 # number of ReadReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::cpu2 890183991 # number of WriteReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::total 890183991 # number of WriteReq miss cycles
system.cpu2.l1c.demand_miss_latency::cpu2 1853340889 # number of demand (read+write) miss cycles
system.cpu2.l1c.demand_miss_latency::total 1853340889 # number of demand (read+write) miss cycles
system.cpu2.l1c.overall_miss_latency::cpu2 1853340889 # number of overall miss cycles
system.cpu2.l1c.overall_miss_latency::total 1853340889 # number of overall miss cycles
system.cpu2.l1c.ReadReq_accesses::cpu2 45469 # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.ReadReq_accesses::total 45469 # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::cpu2 25044 # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::total 25044 # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.demand_accesses::cpu2 70513 # number of demand (read+write) accesses
system.cpu2.l1c.demand_accesses::total 70513 # number of demand (read+write) accesses
system.cpu2.l1c.overall_accesses::cpu2 70513 # number of overall (read+write) accesses
system.cpu2.l1c.overall_accesses::total 70513 # number of overall (read+write) accesses
system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.803383 # miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_miss_rate::total 0.803383 # miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.952883 # miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_miss_rate::total 0.952883 # miss rate for WriteReq accesses
system.cpu2.l1c.demand_miss_rate::cpu2 0.856480 # miss rate for demand accesses
system.cpu2.l1c.demand_miss_rate::total 0.856480 # miss rate for demand accesses
system.cpu2.l1c.overall_miss_rate::cpu2 0.856480 # miss rate for overall accesses
system.cpu2.l1c.overall_miss_rate::total 0.856480 # miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 26366.911166 # average ReadReq miss latency
system.cpu2.l1c.ReadReq_avg_miss_latency::total 26366.911166 # average ReadReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 37302.379777 # average WriteReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::total 37302.379777 # average WriteReq miss latency
system.cpu2.l1c.demand_avg_miss_latency::cpu2 30688.008362 # average overall miss latency
system.cpu2.l1c.demand_avg_miss_latency::total 30688.008362 # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::cpu2 30688.008362 # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::total 30688.008362 # average overall miss latency
system.cpu2.l1c.blocked_cycles::no_mshrs 1016015 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu2.l1c.blocked::no_mshrs 62631 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu2.l1c.avg_blocked_cycles::no_mshrs 16.222238 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu2.l1c.fast_writes 0 # number of fast writes performed
system.cpu2.l1c.cache_copies 0 # number of cache copies performed
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu2.l1c.writebacks::writebacks 9915 # number of writebacks
system.cpu2.l1c.writebacks::total 9915 # number of writebacks
system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36529 # number of ReadReq MSHR misses
system.cpu2.l1c.ReadReq_mshr_misses::total 36529 # number of ReadReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23864 # number of WriteReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::total 23864 # number of WriteReq MSHR misses
system.cpu2.l1c.demand_mshr_misses::cpu2 60393 # number of demand (read+write) MSHR misses
system.cpu2.l1c.demand_mshr_misses::total 60393 # number of demand (read+write) MSHR misses
system.cpu2.l1c.overall_mshr_misses::cpu2 60393 # number of overall MSHR misses
system.cpu2.l1c.overall_mshr_misses::total 60393 # number of overall MSHR misses
system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 885079158 # number of ReadReq MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_miss_latency::total 885079158 # number of ReadReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 839760037 # number of WriteReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::total 839760037 # number of WriteReq MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1724839195 # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::total 1724839195 # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1724839195 # number of overall MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::total 1724839195 # number of overall MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 685753748 # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 685753748 # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 1712116464 # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 1712116464 # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2397870212 # number of overall MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2397870212 # number of overall MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.803383 # mshr miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.803383 # mshr miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.952883 # mshr miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.952883 # mshr miss rate for WriteReq accesses
system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.856480 # mshr miss rate for demand accesses
system.cpu2.l1c.demand_mshr_miss_rate::total 0.856480 # mshr miss rate for demand accesses
system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.856480 # mshr miss rate for overall accesses
system.cpu2.l1c.overall_mshr_miss_rate::total 0.856480 # mshr miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 24229.493225 # average ReadReq mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 24229.493225 # average ReadReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 35189.408188 # average WriteReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 35189.408188 # average WriteReq mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 28560.250277 # average overall mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::total 28560.250277 # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 28560.250277 # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::total 28560.250277 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu3.num_reads 99256 # number of read accesses completed
system.cpu3.num_writes 54955 # number of write accesses completed
system.cpu3.l1c.tags.replacements 22662 # number of replacements
system.cpu3.l1c.tags.tagsinuse 394.489449 # Cycle average of tags in use
system.cpu3.l1c.tags.total_refs 13390 # Total number of references to valid blocks.
system.cpu3.l1c.tags.sampled_refs 23054 # Sample count of references to valid blocks.
system.cpu3.l1c.tags.avg_refs 0.580810 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu3.l1c.tags.occ_blocks::cpu3 394.489449 # Average occupied blocks per requestor
system.cpu3.l1c.tags.occ_percent::cpu3 0.770487 # Average percentage of cache occupancy
system.cpu3.l1c.tags.occ_percent::total 0.770487 # Average percentage of cache occupancy
system.cpu3.l1c.tags.occ_task_id_blocks::1024 392 # Occupied blocks per task id
system.cpu3.l1c.tags.age_task_id_blocks_1024::0 371 # Occupied blocks per task id
system.cpu3.l1c.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
system.cpu3.l1c.tags.occ_task_id_percent::1024 0.765625 # Percentage of cache occupancy per task id
system.cpu3.l1c.tags.tag_accesses 337690 # Number of tag accesses
system.cpu3.l1c.tags.data_accesses 337690 # Number of data accesses
system.cpu3.l1c.ReadReq_hits::cpu3 8629 # number of ReadReq hits
system.cpu3.l1c.ReadReq_hits::total 8629 # number of ReadReq hits
system.cpu3.l1c.WriteReq_hits::cpu3 1137 # number of WriteReq hits
system.cpu3.l1c.WriteReq_hits::total 1137 # number of WriteReq hits
system.cpu3.l1c.demand_hits::cpu3 9766 # number of demand (read+write) hits
system.cpu3.l1c.demand_hits::total 9766 # number of demand (read+write) hits
system.cpu3.l1c.overall_hits::cpu3 9766 # number of overall hits
system.cpu3.l1c.overall_hits::total 9766 # number of overall hits
system.cpu3.l1c.ReadReq_misses::cpu3 36563 # number of ReadReq misses
system.cpu3.l1c.ReadReq_misses::total 36563 # number of ReadReq misses
system.cpu3.l1c.WriteReq_misses::cpu3 23903 # number of WriteReq misses
system.cpu3.l1c.WriteReq_misses::total 23903 # number of WriteReq misses
system.cpu3.l1c.demand_misses::cpu3 60466 # number of demand (read+write) misses
system.cpu3.l1c.demand_misses::total 60466 # number of demand (read+write) misses
system.cpu3.l1c.overall_misses::cpu3 60466 # number of overall misses
system.cpu3.l1c.overall_misses::total 60466 # number of overall misses
system.cpu3.l1c.ReadReq_miss_latency::cpu3 960736157 # number of ReadReq miss cycles
system.cpu3.l1c.ReadReq_miss_latency::total 960736157 # number of ReadReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::cpu3 887839747 # number of WriteReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::total 887839747 # number of WriteReq miss cycles
system.cpu3.l1c.demand_miss_latency::cpu3 1848575904 # number of demand (read+write) miss cycles
system.cpu3.l1c.demand_miss_latency::total 1848575904 # number of demand (read+write) miss cycles
system.cpu3.l1c.overall_miss_latency::cpu3 1848575904 # number of overall miss cycles
system.cpu3.l1c.overall_miss_latency::total 1848575904 # number of overall miss cycles
system.cpu3.l1c.ReadReq_accesses::cpu3 45192 # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.ReadReq_accesses::total 45192 # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::cpu3 25040 # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::total 25040 # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.demand_accesses::cpu3 70232 # number of demand (read+write) accesses
system.cpu3.l1c.demand_accesses::total 70232 # number of demand (read+write) accesses
system.cpu3.l1c.overall_accesses::cpu3 70232 # number of overall (read+write) accesses
system.cpu3.l1c.overall_accesses::total 70232 # number of overall (read+write) accesses
system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.809059 # miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_miss_rate::total 0.809059 # miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954593 # miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_miss_rate::total 0.954593 # miss rate for WriteReq accesses
system.cpu3.l1c.demand_miss_rate::cpu3 0.860947 # miss rate for demand accesses
system.cpu3.l1c.demand_miss_rate::total 0.860947 # miss rate for demand accesses
system.cpu3.l1c.overall_miss_rate::cpu3 0.860947 # miss rate for overall accesses
system.cpu3.l1c.overall_miss_rate::total 0.860947 # miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 26276.185133 # average ReadReq miss latency
system.cpu3.l1c.ReadReq_avg_miss_latency::total 26276.185133 # average ReadReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 37143.444212 # average WriteReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::total 37143.444212 # average WriteReq miss latency
system.cpu3.l1c.demand_avg_miss_latency::cpu3 30572.154665 # average overall miss latency
system.cpu3.l1c.demand_avg_miss_latency::total 30572.154665 # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::cpu3 30572.154665 # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::total 30572.154665 # average overall miss latency
system.cpu3.l1c.blocked_cycles::no_mshrs 1022448 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu3.l1c.blocked::no_mshrs 63227 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu3.l1c.avg_blocked_cycles::no_mshrs 16.171066 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu3.l1c.fast_writes 0 # number of fast writes performed
system.cpu3.l1c.cache_copies 0 # number of cache copies performed
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu3.l1c.writebacks::writebacks 9928 # number of writebacks
system.cpu3.l1c.writebacks::total 9928 # number of writebacks
system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36563 # number of ReadReq MSHR misses
system.cpu3.l1c.ReadReq_mshr_misses::total 36563 # number of ReadReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23903 # number of WriteReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::total 23903 # number of WriteReq MSHR misses
system.cpu3.l1c.demand_mshr_misses::cpu3 60466 # number of demand (read+write) MSHR misses
system.cpu3.l1c.demand_mshr_misses::total 60466 # number of demand (read+write) MSHR misses
system.cpu3.l1c.overall_mshr_misses::cpu3 60466 # number of overall MSHR misses
system.cpu3.l1c.overall_mshr_misses::total 60466 # number of overall MSHR misses
system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 882571457 # number of ReadReq MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_miss_latency::total 882571457 # number of ReadReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 837312821 # number of WriteReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::total 837312821 # number of WriteReq MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1719884278 # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::total 1719884278 # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1719884278 # number of overall MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::total 1719884278 # number of overall MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 700068981 # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 700068981 # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 1667398980 # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 1667398980 # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2367467961 # number of overall MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2367467961 # number of overall MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.809059 # mshr miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.809059 # mshr miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954593 # mshr miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954593 # mshr miss rate for WriteReq accesses
system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.860947 # mshr miss rate for demand accesses
system.cpu3.l1c.demand_mshr_miss_rate::total 0.860947 # mshr miss rate for demand accesses
system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.860947 # mshr miss rate for overall accesses
system.cpu3.l1c.overall_mshr_miss_rate::total 0.860947 # mshr miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 24138.376419 # average ReadReq mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 24138.376419 # average ReadReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 35029.612224 # average WriteReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 35029.612224 # average WriteReq mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 28443.824265 # average overall mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::total 28443.824265 # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 28443.824265 # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::total 28443.824265 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu4.num_reads 99292 # number of read accesses completed
system.cpu4.num_writes 54781 # number of write accesses completed
system.cpu4.l1c.tags.replacements 22192 # number of replacements
system.cpu4.l1c.tags.tagsinuse 393.392100 # Cycle average of tags in use
system.cpu4.l1c.tags.total_refs 13471 # Total number of references to valid blocks.
system.cpu4.l1c.tags.sampled_refs 22589 # Sample count of references to valid blocks.
system.cpu4.l1c.tags.avg_refs 0.596352 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu4.l1c.tags.occ_blocks::cpu4 393.392100 # Average occupied blocks per requestor
system.cpu4.l1c.tags.occ_percent::cpu4 0.768344 # Average percentage of cache occupancy
system.cpu4.l1c.tags.occ_percent::total 0.768344 # Average percentage of cache occupancy
system.cpu4.l1c.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id
system.cpu4.l1c.tags.age_task_id_blocks_1024::0 369 # Occupied blocks per task id
system.cpu4.l1c.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
system.cpu4.l1c.tags.occ_task_id_percent::1024 0.775391 # Percentage of cache occupancy per task id
system.cpu4.l1c.tags.tag_accesses 336466 # Number of tag accesses
system.cpu4.l1c.tags.data_accesses 336466 # Number of data accesses
system.cpu4.l1c.ReadReq_hits::cpu4 8698 # number of ReadReq hits
system.cpu4.l1c.ReadReq_hits::total 8698 # number of ReadReq hits
system.cpu4.l1c.WriteReq_hits::cpu4 1159 # number of WriteReq hits
system.cpu4.l1c.WriteReq_hits::total 1159 # number of WriteReq hits
system.cpu4.l1c.demand_hits::cpu4 9857 # number of demand (read+write) hits
system.cpu4.l1c.demand_hits::total 9857 # number of demand (read+write) hits
system.cpu4.l1c.overall_hits::cpu4 9857 # number of overall hits
system.cpu4.l1c.overall_hits::total 9857 # number of overall hits
system.cpu4.l1c.ReadReq_misses::cpu4 36438 # number of ReadReq misses
system.cpu4.l1c.ReadReq_misses::total 36438 # number of ReadReq misses
system.cpu4.l1c.WriteReq_misses::cpu4 23701 # number of WriteReq misses
system.cpu4.l1c.WriteReq_misses::total 23701 # number of WriteReq misses
system.cpu4.l1c.demand_misses::cpu4 60139 # number of demand (read+write) misses
system.cpu4.l1c.demand_misses::total 60139 # number of demand (read+write) misses
system.cpu4.l1c.overall_misses::cpu4 60139 # number of overall misses
system.cpu4.l1c.overall_misses::total 60139 # number of overall misses
system.cpu4.l1c.ReadReq_miss_latency::cpu4 959750489 # number of ReadReq miss cycles
system.cpu4.l1c.ReadReq_miss_latency::total 959750489 # number of ReadReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::cpu4 883613878 # number of WriteReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::total 883613878 # number of WriteReq miss cycles
system.cpu4.l1c.demand_miss_latency::cpu4 1843364367 # number of demand (read+write) miss cycles
system.cpu4.l1c.demand_miss_latency::total 1843364367 # number of demand (read+write) miss cycles
system.cpu4.l1c.overall_miss_latency::cpu4 1843364367 # number of overall miss cycles
system.cpu4.l1c.overall_miss_latency::total 1843364367 # number of overall miss cycles
system.cpu4.l1c.ReadReq_accesses::cpu4 45136 # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.ReadReq_accesses::total 45136 # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::cpu4 24860 # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::total 24860 # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.demand_accesses::cpu4 69996 # number of demand (read+write) accesses
system.cpu4.l1c.demand_accesses::total 69996 # number of demand (read+write) accesses
system.cpu4.l1c.overall_accesses::cpu4 69996 # number of overall (read+write) accesses
system.cpu4.l1c.overall_accesses::total 69996 # number of overall (read+write) accesses
system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807294 # miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_miss_rate::total 0.807294 # miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953379 # miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_miss_rate::total 0.953379 # miss rate for WriteReq accesses
system.cpu4.l1c.demand_miss_rate::cpu4 0.859178 # miss rate for demand accesses
system.cpu4.l1c.demand_miss_rate::total 0.859178 # miss rate for demand accesses
system.cpu4.l1c.overall_miss_rate::cpu4 0.859178 # miss rate for overall accesses
system.cpu4.l1c.overall_miss_rate::total 0.859178 # miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 26339.274631 # average ReadReq miss latency
system.cpu4.l1c.ReadReq_avg_miss_latency::total 26339.274631 # average ReadReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 37281.712924 # average WriteReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::total 37281.712924 # average WriteReq miss latency
system.cpu4.l1c.demand_avg_miss_latency::cpu4 30651.729610 # average overall miss latency
system.cpu4.l1c.demand_avg_miss_latency::total 30651.729610 # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::cpu4 30651.729610 # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::total 30651.729610 # average overall miss latency
system.cpu4.l1c.blocked_cycles::no_mshrs 1023771 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu4.l1c.blocked::no_mshrs 62867 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu4.l1c.avg_blocked_cycles::no_mshrs 16.284712 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu4.l1c.fast_writes 0 # number of fast writes performed
system.cpu4.l1c.cache_copies 0 # number of cache copies performed
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu4.l1c.writebacks::writebacks 9698 # number of writebacks
system.cpu4.l1c.writebacks::total 9698 # number of writebacks
system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36438 # number of ReadReq MSHR misses
system.cpu4.l1c.ReadReq_mshr_misses::total 36438 # number of ReadReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23701 # number of WriteReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::total 23701 # number of WriteReq MSHR misses
system.cpu4.l1c.demand_mshr_misses::cpu4 60139 # number of demand (read+write) MSHR misses
system.cpu4.l1c.demand_mshr_misses::total 60139 # number of demand (read+write) MSHR misses
system.cpu4.l1c.overall_mshr_misses::cpu4 60139 # number of overall MSHR misses
system.cpu4.l1c.overall_mshr_misses::total 60139 # number of overall MSHR misses
system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 881959493 # number of ReadReq MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_miss_latency::total 881959493 # number of ReadReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 833428166 # number of WriteReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::total 833428166 # number of WriteReq MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1715387659 # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::total 1715387659 # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1715387659 # number of overall MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::total 1715387659 # number of overall MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 703007482 # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 703007482 # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 1705988496 # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 1705988496 # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2408995978 # number of overall MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2408995978 # number of overall MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807294 # mshr miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807294 # mshr miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953379 # mshr miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953379 # mshr miss rate for WriteReq accesses
system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859178 # mshr miss rate for demand accesses
system.cpu4.l1c.demand_mshr_miss_rate::total 0.859178 # mshr miss rate for demand accesses
system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859178 # mshr miss rate for overall accesses
system.cpu4.l1c.overall_mshr_miss_rate::total 0.859178 # mshr miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 24204.388084 # average ReadReq mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 24204.388084 # average ReadReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 35164.261677 # average WriteReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 35164.261677 # average WriteReq mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 28523.714378 # average overall mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::total 28523.714378 # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 28523.714378 # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::total 28523.714378 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu5.num_reads 99672 # number of read accesses completed
system.cpu5.num_writes 54824 # number of write accesses completed
system.cpu5.l1c.tags.replacements 22459 # number of replacements
system.cpu5.l1c.tags.tagsinuse 393.671106 # Cycle average of tags in use
system.cpu5.l1c.tags.total_refs 13533 # Total number of references to valid blocks.
system.cpu5.l1c.tags.sampled_refs 22853 # Sample count of references to valid blocks.
system.cpu5.l1c.tags.avg_refs 0.592176 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu5.l1c.tags.occ_blocks::cpu5 393.671106 # Average occupied blocks per requestor
system.cpu5.l1c.tags.occ_percent::cpu5 0.768889 # Average percentage of cache occupancy
system.cpu5.l1c.tags.occ_percent::total 0.768889 # Average percentage of cache occupancy
system.cpu5.l1c.tags.occ_task_id_blocks::1024 394 # Occupied blocks per task id
system.cpu5.l1c.tags.age_task_id_blocks_1024::0 371 # Occupied blocks per task id
system.cpu5.l1c.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id
system.cpu5.l1c.tags.occ_task_id_percent::1024 0.769531 # Percentage of cache occupancy per task id
system.cpu5.l1c.tags.tag_accesses 337969 # Number of tag accesses
system.cpu5.l1c.tags.data_accesses 337969 # Number of data accesses
system.cpu5.l1c.ReadReq_hits::cpu5 8696 # number of ReadReq hits
system.cpu5.l1c.ReadReq_hits::total 8696 # number of ReadReq hits
system.cpu5.l1c.WriteReq_hits::cpu5 1170 # number of WriteReq hits
system.cpu5.l1c.WriteReq_hits::total 1170 # number of WriteReq hits
system.cpu5.l1c.demand_hits::cpu5 9866 # number of demand (read+write) hits
system.cpu5.l1c.demand_hits::total 9866 # number of demand (read+write) hits
system.cpu5.l1c.overall_hits::cpu5 9866 # number of overall hits
system.cpu5.l1c.overall_hits::total 9866 # number of overall hits
system.cpu5.l1c.ReadReq_misses::cpu5 36658 # number of ReadReq misses
system.cpu5.l1c.ReadReq_misses::total 36658 # number of ReadReq misses
system.cpu5.l1c.WriteReq_misses::cpu5 23786 # number of WriteReq misses
system.cpu5.l1c.WriteReq_misses::total 23786 # number of WriteReq misses
system.cpu5.l1c.demand_misses::cpu5 60444 # number of demand (read+write) misses
system.cpu5.l1c.demand_misses::total 60444 # number of demand (read+write) misses
system.cpu5.l1c.overall_misses::cpu5 60444 # number of overall misses
system.cpu5.l1c.overall_misses::total 60444 # number of overall misses
system.cpu5.l1c.ReadReq_miss_latency::cpu5 958216057 # number of ReadReq miss cycles
system.cpu5.l1c.ReadReq_miss_latency::total 958216057 # number of ReadReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::cpu5 885896912 # number of WriteReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::total 885896912 # number of WriteReq miss cycles
system.cpu5.l1c.demand_miss_latency::cpu5 1844112969 # number of demand (read+write) miss cycles
system.cpu5.l1c.demand_miss_latency::total 1844112969 # number of demand (read+write) miss cycles
system.cpu5.l1c.overall_miss_latency::cpu5 1844112969 # number of overall miss cycles
system.cpu5.l1c.overall_miss_latency::total 1844112969 # number of overall miss cycles
system.cpu5.l1c.ReadReq_accesses::cpu5 45354 # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.ReadReq_accesses::total 45354 # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::cpu5 24956 # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::total 24956 # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.demand_accesses::cpu5 70310 # number of demand (read+write) accesses
system.cpu5.l1c.demand_accesses::total 70310 # number of demand (read+write) accesses
system.cpu5.l1c.overall_accesses::cpu5 70310 # number of overall (read+write) accesses
system.cpu5.l1c.overall_accesses::total 70310 # number of overall (read+write) accesses
system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.808264 # miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_miss_rate::total 0.808264 # miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.953117 # miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_miss_rate::total 0.953117 # miss rate for WriteReq accesses
system.cpu5.l1c.demand_miss_rate::cpu5 0.859679 # miss rate for demand accesses
system.cpu5.l1c.demand_miss_rate::total 0.859679 # miss rate for demand accesses
system.cpu5.l1c.overall_miss_rate::cpu5 0.859679 # miss rate for overall accesses
system.cpu5.l1c.overall_miss_rate::total 0.859679 # miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 26139.343581 # average ReadReq miss latency
system.cpu5.l1c.ReadReq_avg_miss_latency::total 26139.343581 # average ReadReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 37244.467838 # average WriteReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::total 37244.467838 # average WriteReq miss latency
system.cpu5.l1c.demand_avg_miss_latency::cpu5 30509.446248 # average overall miss latency
system.cpu5.l1c.demand_avg_miss_latency::total 30509.446248 # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::cpu5 30509.446248 # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::total 30509.446248 # average overall miss latency
system.cpu5.l1c.blocked_cycles::no_mshrs 1026604 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu5.l1c.blocked::no_mshrs 63359 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu5.l1c.avg_blocked_cycles::no_mshrs 16.202970 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu5.l1c.fast_writes 0 # number of fast writes performed
system.cpu5.l1c.cache_copies 0 # number of cache copies performed
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu5.l1c.writebacks::writebacks 9812 # number of writebacks
system.cpu5.l1c.writebacks::total 9812 # number of writebacks
system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36658 # number of ReadReq MSHR misses
system.cpu5.l1c.ReadReq_mshr_misses::total 36658 # number of ReadReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23786 # number of WriteReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::total 23786 # number of WriteReq MSHR misses
system.cpu5.l1c.demand_mshr_misses::cpu5 60444 # number of demand (read+write) MSHR misses
system.cpu5.l1c.demand_mshr_misses::total 60444 # number of demand (read+write) MSHR misses
system.cpu5.l1c.overall_mshr_misses::cpu5 60444 # number of overall MSHR misses
system.cpu5.l1c.overall_mshr_misses::total 60444 # number of overall MSHR misses
system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 879872261 # number of ReadReq MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_miss_latency::total 879872261 # number of ReadReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 835586106 # number of WriteReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::total 835586106 # number of WriteReq MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1715458367 # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::total 1715458367 # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1715458367 # number of overall MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::total 1715458367 # number of overall MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 707107291 # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 707107291 # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 1680181552 # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 1680181552 # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2387288843 # number of overall MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2387288843 # number of overall MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.808264 # mshr miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808264 # mshr miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.953117 # mshr miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.953117 # mshr miss rate for WriteReq accesses
system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.859679 # mshr miss rate for demand accesses
system.cpu5.l1c.demand_mshr_miss_rate::total 0.859679 # mshr miss rate for demand accesses
system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.859679 # mshr miss rate for overall accesses
system.cpu5.l1c.overall_mshr_miss_rate::total 0.859679 # mshr miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 24002.189454 # average ReadReq mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 24002.189454 # average ReadReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 35129.324224 # average WriteReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 35129.324224 # average WriteReq mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 28380.953726 # average overall mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::total 28380.953726 # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 28380.953726 # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::total 28380.953726 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu6.num_reads 99511 # number of read accesses completed
system.cpu6.num_writes 54977 # number of write accesses completed
system.cpu6.l1c.tags.replacements 22541 # number of replacements
system.cpu6.l1c.tags.tagsinuse 393.448229 # Cycle average of tags in use
system.cpu6.l1c.tags.total_refs 13464 # Total number of references to valid blocks.
system.cpu6.l1c.tags.sampled_refs 22939 # Sample count of references to valid blocks.
system.cpu6.l1c.tags.avg_refs 0.586948 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu6.l1c.tags.occ_blocks::cpu6 393.448229 # Average occupied blocks per requestor
system.cpu6.l1c.tags.occ_percent::cpu6 0.768454 # Average percentage of cache occupancy
system.cpu6.l1c.tags.occ_percent::total 0.768454 # Average percentage of cache occupancy
system.cpu6.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id
system.cpu6.l1c.tags.age_task_id_blocks_1024::0 372 # Occupied blocks per task id
system.cpu6.l1c.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
system.cpu6.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id
system.cpu6.l1c.tags.tag_accesses 337704 # Number of tag accesses
system.cpu6.l1c.tags.data_accesses 337704 # Number of data accesses
system.cpu6.l1c.ReadReq_hits::cpu6 8641 # number of ReadReq hits
system.cpu6.l1c.ReadReq_hits::total 8641 # number of ReadReq hits
system.cpu6.l1c.WriteReq_hits::cpu6 1220 # number of WriteReq hits
system.cpu6.l1c.WriteReq_hits::total 1220 # number of WriteReq hits
system.cpu6.l1c.demand_hits::cpu6 9861 # number of demand (read+write) hits
system.cpu6.l1c.demand_hits::total 9861 # number of demand (read+write) hits
system.cpu6.l1c.overall_hits::cpu6 9861 # number of overall hits
system.cpu6.l1c.overall_hits::total 9861 # number of overall hits
system.cpu6.l1c.ReadReq_misses::cpu6 36671 # number of ReadReq misses
system.cpu6.l1c.ReadReq_misses::total 36671 # number of ReadReq misses
system.cpu6.l1c.WriteReq_misses::cpu6 23713 # number of WriteReq misses
system.cpu6.l1c.WriteReq_misses::total 23713 # number of WriteReq misses
system.cpu6.l1c.demand_misses::cpu6 60384 # number of demand (read+write) misses
system.cpu6.l1c.demand_misses::total 60384 # number of demand (read+write) misses
system.cpu6.l1c.overall_misses::cpu6 60384 # number of overall misses
system.cpu6.l1c.overall_misses::total 60384 # number of overall misses
system.cpu6.l1c.ReadReq_miss_latency::cpu6 960694665 # number of ReadReq miss cycles
system.cpu6.l1c.ReadReq_miss_latency::total 960694665 # number of ReadReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::cpu6 879536054 # number of WriteReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::total 879536054 # number of WriteReq miss cycles
system.cpu6.l1c.demand_miss_latency::cpu6 1840230719 # number of demand (read+write) miss cycles
system.cpu6.l1c.demand_miss_latency::total 1840230719 # number of demand (read+write) miss cycles
system.cpu6.l1c.overall_miss_latency::cpu6 1840230719 # number of overall miss cycles
system.cpu6.l1c.overall_miss_latency::total 1840230719 # number of overall miss cycles
system.cpu6.l1c.ReadReq_accesses::cpu6 45312 # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.ReadReq_accesses::total 45312 # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::cpu6 24933 # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::total 24933 # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.demand_accesses::cpu6 70245 # number of demand (read+write) accesses
system.cpu6.l1c.demand_accesses::total 70245 # number of demand (read+write) accesses
system.cpu6.l1c.overall_accesses::cpu6 70245 # number of overall (read+write) accesses
system.cpu6.l1c.overall_accesses::total 70245 # number of overall (read+write) accesses
system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.809300 # miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_miss_rate::total 0.809300 # miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.951069 # miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_miss_rate::total 0.951069 # miss rate for WriteReq accesses
system.cpu6.l1c.demand_miss_rate::cpu6 0.859620 # miss rate for demand accesses
system.cpu6.l1c.demand_miss_rate::total 0.859620 # miss rate for demand accesses
system.cpu6.l1c.overall_miss_rate::cpu6 0.859620 # miss rate for overall accesses
system.cpu6.l1c.overall_miss_rate::total 0.859620 # miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 26197.667503 # average ReadReq miss latency
system.cpu6.l1c.ReadReq_avg_miss_latency::total 26197.667503 # average ReadReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 37090.880698 # average WriteReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::total 37090.880698 # average WriteReq miss latency
system.cpu6.l1c.demand_avg_miss_latency::cpu6 30475.468982 # average overall miss latency
system.cpu6.l1c.demand_avg_miss_latency::total 30475.468982 # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::cpu6 30475.468982 # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::total 30475.468982 # average overall miss latency
system.cpu6.l1c.blocked_cycles::no_mshrs 1019991 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu6.l1c.blocked::no_mshrs 62969 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu6.l1c.avg_blocked_cycles::no_mshrs 16.198304 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu6.l1c.fast_writes 0 # number of fast writes performed
system.cpu6.l1c.cache_copies 0 # number of cache copies performed
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu6.l1c.writebacks::writebacks 9771 # number of writebacks
system.cpu6.l1c.writebacks::total 9771 # number of writebacks
system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36671 # number of ReadReq MSHR misses
system.cpu6.l1c.ReadReq_mshr_misses::total 36671 # number of ReadReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23713 # number of WriteReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::total 23713 # number of WriteReq MSHR misses
system.cpu6.l1c.demand_mshr_misses::cpu6 60384 # number of demand (read+write) MSHR misses
system.cpu6.l1c.demand_mshr_misses::total 60384 # number of demand (read+write) MSHR misses
system.cpu6.l1c.overall_mshr_misses::cpu6 60384 # number of overall MSHR misses
system.cpu6.l1c.overall_mshr_misses::total 60384 # number of overall MSHR misses
system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 882425777 # number of ReadReq MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_miss_latency::total 882425777 # number of ReadReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 829351266 # number of WriteReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::total 829351266 # number of WriteReq MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1711777043 # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::total 1711777043 # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1711777043 # number of overall MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::total 1711777043 # number of overall MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 702299487 # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 702299487 # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 1717296024 # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 1717296024 # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2419595511 # number of overall MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2419595511 # number of overall MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.809300 # mshr miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.809300 # mshr miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.951069 # mshr miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.951069 # mshr miss rate for WriteReq accesses
system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859620 # mshr miss rate for demand accesses
system.cpu6.l1c.demand_mshr_miss_rate::total 0.859620 # mshr miss rate for demand accesses
system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859620 # mshr miss rate for overall accesses
system.cpu6.l1c.overall_mshr_miss_rate::total 0.859620 # mshr miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 24063.313708 # average ReadReq mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 24063.313708 # average ReadReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 34974.539957 # average WriteReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 34974.539957 # average WriteReq mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 28348.188974 # average overall mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::total 28348.188974 # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 28348.188974 # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::total 28348.188974 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu7.num_reads 98836 # number of read accesses completed
system.cpu7.num_writes 54806 # number of write accesses completed
system.cpu7.l1c.tags.replacements 22352 # number of replacements
system.cpu7.l1c.tags.tagsinuse 393.572142 # Cycle average of tags in use
system.cpu7.l1c.tags.total_refs 13400 # Total number of references to valid blocks.
system.cpu7.l1c.tags.sampled_refs 22745 # Sample count of references to valid blocks.
system.cpu7.l1c.tags.avg_refs 0.589140 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu7.l1c.tags.occ_blocks::cpu7 393.572142 # Average occupied blocks per requestor
system.cpu7.l1c.tags.occ_percent::cpu7 0.768696 # Average percentage of cache occupancy
system.cpu7.l1c.tags.occ_percent::total 0.768696 # Average percentage of cache occupancy
system.cpu7.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id
system.cpu7.l1c.tags.age_task_id_blocks_1024::0 363 # Occupied blocks per task id
system.cpu7.l1c.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id
system.cpu7.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id
system.cpu7.l1c.tags.tag_accesses 336509 # Number of tag accesses
system.cpu7.l1c.tags.data_accesses 336509 # Number of data accesses
system.cpu7.l1c.ReadReq_hits::cpu7 8699 # number of ReadReq hits
system.cpu7.l1c.ReadReq_hits::total 8699 # number of ReadReq hits
system.cpu7.l1c.WriteReq_hits::cpu7 1106 # number of WriteReq hits
system.cpu7.l1c.WriteReq_hits::total 1106 # number of WriteReq hits
system.cpu7.l1c.demand_hits::cpu7 9805 # number of demand (read+write) hits
system.cpu7.l1c.demand_hits::total 9805 # number of demand (read+write) hits
system.cpu7.l1c.overall_hits::cpu7 9805 # number of overall hits
system.cpu7.l1c.overall_hits::total 9805 # number of overall hits
system.cpu7.l1c.ReadReq_misses::cpu7 36228 # number of ReadReq misses
system.cpu7.l1c.ReadReq_misses::total 36228 # number of ReadReq misses
system.cpu7.l1c.WriteReq_misses::cpu7 23958 # number of WriteReq misses
system.cpu7.l1c.WriteReq_misses::total 23958 # number of WriteReq misses
system.cpu7.l1c.demand_misses::cpu7 60186 # number of demand (read+write) misses
system.cpu7.l1c.demand_misses::total 60186 # number of demand (read+write) misses
system.cpu7.l1c.overall_misses::cpu7 60186 # number of overall misses
system.cpu7.l1c.overall_misses::total 60186 # number of overall misses
system.cpu7.l1c.ReadReq_miss_latency::cpu7 952764751 # number of ReadReq miss cycles
system.cpu7.l1c.ReadReq_miss_latency::total 952764751 # number of ReadReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::cpu7 890612165 # number of WriteReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::total 890612165 # number of WriteReq miss cycles
system.cpu7.l1c.demand_miss_latency::cpu7 1843376916 # number of demand (read+write) miss cycles
system.cpu7.l1c.demand_miss_latency::total 1843376916 # number of demand (read+write) miss cycles
system.cpu7.l1c.overall_miss_latency::cpu7 1843376916 # number of overall miss cycles
system.cpu7.l1c.overall_miss_latency::total 1843376916 # number of overall miss cycles
system.cpu7.l1c.ReadReq_accesses::cpu7 44927 # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.ReadReq_accesses::total 44927 # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::cpu7 25064 # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::total 25064 # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.demand_accesses::cpu7 69991 # number of demand (read+write) accesses
system.cpu7.l1c.demand_accesses::total 69991 # number of demand (read+write) accesses
system.cpu7.l1c.overall_accesses::cpu7 69991 # number of overall (read+write) accesses
system.cpu7.l1c.overall_accesses::total 69991 # number of overall (read+write) accesses
system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.806375 # miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_miss_rate::total 0.806375 # miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955873 # miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_miss_rate::total 0.955873 # miss rate for WriteReq accesses
system.cpu7.l1c.demand_miss_rate::cpu7 0.859911 # miss rate for demand accesses
system.cpu7.l1c.demand_miss_rate::total 0.859911 # miss rate for demand accesses
system.cpu7.l1c.overall_miss_rate::cpu7 0.859911 # miss rate for overall accesses
system.cpu7.l1c.overall_miss_rate::total 0.859911 # miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 26299.126394 # average ReadReq miss latency
system.cpu7.l1c.ReadReq_avg_miss_latency::total 26299.126394 # average ReadReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 37173.894524 # average WriteReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::total 37173.894524 # average WriteReq miss latency
system.cpu7.l1c.demand_avg_miss_latency::cpu7 30628.001794 # average overall miss latency
system.cpu7.l1c.demand_avg_miss_latency::total 30628.001794 # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::cpu7 30628.001794 # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::total 30628.001794 # average overall miss latency
system.cpu7.l1c.blocked_cycles::no_mshrs 1021665 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu7.l1c.blocked::no_mshrs 62785 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu7.l1c.avg_blocked_cycles::no_mshrs 16.272438 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu7.l1c.fast_writes 0 # number of fast writes performed
system.cpu7.l1c.cache_copies 0 # number of cache copies performed
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.cpu7.l1c.writebacks::writebacks 9931 # number of writebacks
system.cpu7.l1c.writebacks::total 9931 # number of writebacks
system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36228 # number of ReadReq MSHR misses
system.cpu7.l1c.ReadReq_mshr_misses::total 36228 # number of ReadReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23958 # number of WriteReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::total 23958 # number of WriteReq MSHR misses
system.cpu7.l1c.demand_mshr_misses::cpu7 60186 # number of demand (read+write) MSHR misses
system.cpu7.l1c.demand_mshr_misses::total 60186 # number of demand (read+write) MSHR misses
system.cpu7.l1c.overall_mshr_misses::cpu7 60186 # number of overall MSHR misses
system.cpu7.l1c.overall_mshr_misses::total 60186 # number of overall MSHR misses
system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 875407713 # number of ReadReq MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_miss_latency::total 875407713 # number of ReadReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 839967251 # number of WriteReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::total 839967251 # number of WriteReq MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1715374964 # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::total 1715374964 # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1715374964 # number of overall MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::total 1715374964 # number of overall MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 702238586 # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 702238586 # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 1694350083 # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 1694350083 # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2396588669 # number of overall MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2396588669 # number of overall MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.806375 # mshr miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.806375 # mshr miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.955873 # mshr miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.955873 # mshr miss rate for WriteReq accesses
system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859911 # mshr miss rate for demand accesses
system.cpu7.l1c.demand_mshr_miss_rate::total 0.859911 # mshr miss rate for demand accesses
system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859911 # mshr miss rate for overall accesses
system.cpu7.l1c.overall_mshr_miss_rate::total 0.859911 # mshr miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 24163.843243 # average ReadReq mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 24163.843243 # average ReadReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 35059.990442 # average WriteReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 35059.990442 # average WriteReq mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 28501.228924 # average overall mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::total 28501.228924 # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 28501.228924 # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::total 28501.228924 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.l2c.tags.replacements 13277 # number of replacements
system.l2c.tags.tagsinuse 783.059977 # Cycle average of tags in use
system.l2c.tags.total_refs 151520 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 14056 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 10.779738 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 729.095705 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0 7.040995 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1 7.066153 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2 6.783419 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3 7.143521 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu4 6.879919 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu5 6.083313 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu6 6.867349 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu7 6.099602 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.712008 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0 0.006876 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1 0.006901 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2 0.006624 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3 0.006976 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu4 0.006719 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu5 0.005941 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu6 0.006706 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu7 0.005957 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.764707 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024 779 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 598 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 181 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.760742 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 1976800 # Number of tag accesses
system.l2c.tags.data_accesses 1976800 # Number of data accesses
system.l2c.ReadReq_hits::cpu0 10744 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1 10861 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2 10871 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3 10670 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu4 10810 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu5 10859 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu6 10920 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu7 10735 # number of ReadReq hits
system.l2c.ReadReq_hits::total 86470 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 76237 # number of Writeback hits
system.l2c.Writeback_hits::total 76237 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0 344 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1 346 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2 369 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3 358 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu4 342 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu5 326 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu6 336 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu7 356 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 2777 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0 1900 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1 1915 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2 1982 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu3 1977 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu4 1900 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu5 1958 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu6 1937 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu7 1931 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 15500 # number of ReadExReq hits
system.l2c.demand_hits::cpu0 12644 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1 12776 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2 12853 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3 12647 # number of demand (read+write) hits
system.l2c.demand_hits::cpu4 12710 # number of demand (read+write) hits
system.l2c.demand_hits::cpu5 12817 # number of demand (read+write) hits
system.l2c.demand_hits::cpu6 12857 # number of demand (read+write) hits
system.l2c.demand_hits::cpu7 12666 # number of demand (read+write) hits
system.l2c.demand_hits::total 101970 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0 12644 # number of overall hits
system.l2c.overall_hits::cpu1 12776 # number of overall hits
system.l2c.overall_hits::cpu2 12853 # number of overall hits
system.l2c.overall_hits::cpu3 12647 # number of overall hits
system.l2c.overall_hits::cpu4 12710 # number of overall hits
system.l2c.overall_hits::cpu5 12817 # number of overall hits
system.l2c.overall_hits::cpu6 12857 # number of overall hits
system.l2c.overall_hits::cpu7 12666 # number of overall hits
system.l2c.overall_hits::total 101970 # number of overall hits
system.l2c.ReadReq_misses::cpu0 765 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1 729 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2 729 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3 708 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu4 735 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu5 684 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu6 695 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu7 674 # number of ReadReq misses
system.l2c.ReadReq_misses::total 5719 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0 1992 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1 1980 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2 1951 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3 2012 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu4 1975 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu5 1990 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu6 2015 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu7 1970 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 15885 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0 4350 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1 4268 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2 4371 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3 4368 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu4 4431 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu5 4387 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu6 4359 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu7 4476 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 35010 # number of ReadExReq misses
system.l2c.demand_misses::cpu0 5115 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1 4997 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2 5100 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3 5076 # number of demand (read+write) misses
system.l2c.demand_misses::cpu4 5166 # number of demand (read+write) misses
system.l2c.demand_misses::cpu5 5071 # number of demand (read+write) misses
system.l2c.demand_misses::cpu6 5054 # number of demand (read+write) misses
system.l2c.demand_misses::cpu7 5150 # number of demand (read+write) misses
system.l2c.demand_misses::total 40729 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0 5115 # number of overall misses
system.l2c.overall_misses::cpu1 4997 # number of overall misses
system.l2c.overall_misses::cpu2 5100 # number of overall misses
system.l2c.overall_misses::cpu3 5076 # number of overall misses
system.l2c.overall_misses::cpu4 5166 # number of overall misses
system.l2c.overall_misses::cpu5 5071 # number of overall misses
system.l2c.overall_misses::cpu6 5054 # number of overall misses
system.l2c.overall_misses::cpu7 5150 # number of overall misses
system.l2c.overall_misses::total 40729 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0 46620930 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1 44960918 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2 44432427 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3 43382432 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu4 44487433 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu5 41294425 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu6 42419930 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu7 41189936 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 348788431 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0 57711996 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1 58106496 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2 57659498 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu3 57666495 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu4 55433497 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu5 57841495 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu6 59041000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu7 57235498 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 460695975 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0 234061451 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1 229252453 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2 235963436 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3 234901447 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu4 238651447 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu5 236178452 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu6 234894949 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu7 241135947 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 1885039582 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0 280682381 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1 274213371 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2 280395863 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3 278283879 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu4 283138880 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu5 277472877 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu6 277314879 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu7 282325883 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 2233828013 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0 280682381 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1 274213371 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2 280395863 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3 278283879 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu4 283138880 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu5 277472877 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu6 277314879 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu7 282325883 # number of overall miss cycles
system.l2c.overall_miss_latency::total 2233828013 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0 11509 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1 11590 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2 11600 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3 11378 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu4 11545 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu5 11543 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu6 11615 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu7 11409 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 92189 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 76237 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 76237 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0 2336 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1 2326 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2 2320 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3 2370 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu4 2317 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu5 2316 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu6 2351 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu7 2326 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 18662 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0 6250 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1 6183 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2 6353 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3 6345 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu4 6331 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu5 6345 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu6 6296 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu7 6407 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 50510 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0 17759 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1 17773 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2 17953 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3 17723 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu4 17876 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu5 17888 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu6 17911 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu7 17816 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 142699 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0 17759 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1 17773 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2 17953 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3 17723 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu4 17876 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu5 17888 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu6 17911 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu7 17816 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 142699 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0 0.066470 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1 0.062899 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2 0.062845 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3 0.062225 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu4 0.063664 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu5 0.059257 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu6 0.059836 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu7 0.059076 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.062036 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0 0.852740 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1 0.851247 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2 0.840948 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3 0.848945 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu4 0.852395 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu5 0.859240 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu6 0.857082 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu7 0.846948 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.851195 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0 0.696000 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1 0.690280 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2 0.688021 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3 0.688416 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu4 0.699889 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu5 0.691411 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu6 0.692344 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu7 0.698611 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.693130 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0 0.288023 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1 0.281157 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2 0.284075 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3 0.286407 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu4 0.288991 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu5 0.283486 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu6 0.282173 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu7 0.289066 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.285419 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0 0.288023 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1 0.281157 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2 0.284075 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3 0.286407 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu4 0.288991 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu5 0.283486 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu6 0.282173 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu7 0.289066 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.285419 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0 60942.392157 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1 61674.784636 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2 60949.831276 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3 61274.621469 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu4 60527.119728 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu5 60371.966374 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu6 61035.870504 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu7 61112.664688 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 60987.660605 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0 28971.885542 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1 29346.715152 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2 29553.817529 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu3 28661.279821 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu4 28067.593418 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu5 29066.077889 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu6 29300.744417 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu7 29053.552284 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 29001.949953 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0 53807.230115 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1 53714.257966 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2 53983.856326 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3 53777.803800 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu4 53859.500564 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu5 53835.981764 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu6 53887.347786 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu7 53873.089142 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 53842.890089 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0 54874.365787 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1 54875.599560 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2 54979.580980 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3 54823.459220 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu4 54808.145567 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu5 54717.585683 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu6 54870.375742 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu7 54820.559806 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 54846.129613 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0 54874.365787 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1 54875.599560 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2 54979.580980 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3 54823.459220 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu4 54808.145567 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu5 54717.585683 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu6 54870.375742 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu7 54820.559806 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 54846.129613 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 11130 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 1567 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs 7.102744 # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 6229 # number of writebacks
system.l2c.writebacks::total 6229 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0 7 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1 7 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2 11 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu3 4 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu4 5 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu5 11 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu6 3 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu7 5 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 53 # number of ReadReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu4 1 # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu7 1 # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::total 2 # number of UpgradeReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu0 4 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu1 3 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu2 2 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu3 4 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu4 1 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu5 4 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu6 1 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu7 2 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::total 21 # number of ReadExReq MSHR hits
system.l2c.demand_mshr_hits::cpu0 11 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1 10 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2 13 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3 8 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu4 6 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu5 15 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu6 4 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu7 7 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0 11 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1 10 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2 13 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3 8 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu4 6 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu5 15 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu6 4 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu7 7 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 74 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0 758 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1 722 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2 718 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3 704 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu4 730 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu5 673 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu6 692 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu7 669 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 5666 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0 1992 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1 1980 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2 1951 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3 2012 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu4 1974 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu5 1990 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu6 2015 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu7 1969 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 15883 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0 4346 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1 4265 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2 4369 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3 4364 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu4 4430 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu5 4383 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu6 4358 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu7 4474 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 34989 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0 5104 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1 4987 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2 5087 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3 5068 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu4 5160 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu5 5056 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu6 5050 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu7 5143 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 40655 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0 5104 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1 4987 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2 5087 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3 5068 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu4 5160 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu5 5056 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu6 5050 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu7 5143 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 40655 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0 37179930 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1 35966920 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2 35314428 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3 34763932 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu4 35492434 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu5 32731425 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu6 33928930 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu7 32969437 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 278347436 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0 81798995 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1 81126494 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2 80135996 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3 82599489 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu4 81068996 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu5 81609993 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu6 82618495 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu7 80871496 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 651829954 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0 181281952 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1 177509453 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2 183001436 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3 181913947 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu4 184978447 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu5 182997452 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu6 182077949 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu7 186899447 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 1460660083 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0 218461882 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1 213476373 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2 218315864 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3 216677879 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu4 220470881 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu5 215728877 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu6 216006879 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu7 219868884 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 1739007519 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0 218461882 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1 213476373 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2 218315864 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3 216677879 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu4 220470881 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu5 215728877 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu6 216006879 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu7 219868884 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 1739007519 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 407707447 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 401123946 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 397019445 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 405812955 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 407128948 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 410535950 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 408564954 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 406637950 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 3244531595 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 230392811 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 237768794 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 237208468 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 229246463 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 232269476 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 230268468 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 234242974 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 227836970 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 1859234424 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0 638100258 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1 638892740 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2 634227913 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu3 635059418 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu4 639398424 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu5 640804418 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu6 642807928 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu7 634474920 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 5103766019 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0 0.065861 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1 0.062295 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2 0.061897 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3 0.061874 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu4 0.063231 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu5 0.058304 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu6 0.059578 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu7 0.058638 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.061461 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.852740 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.851247 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.840948 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.848945 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.851964 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.859240 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.857082 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.846518 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.851088 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.695360 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.689795 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.687707 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.687786 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.699731 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.690780 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.692186 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.698299 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.692714 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0 0.287404 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1 0.280594 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2 0.283351 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3 0.285956 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu4 0.288655 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu5 0.282648 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu6 0.281950 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu7 0.288673 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.284900 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0 0.287404 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1 0.280594 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2 0.283351 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3 0.285956 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu4 0.288655 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu5 0.282648 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu6 0.281950 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu7 0.288673 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.284900 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 49050.039578 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 49815.678670 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 49184.440111 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49380.585227 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 48619.772603 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 48635.104012 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49030.245665 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 49281.669656 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 49125.915284 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41063.752510 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 40972.976768 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41074.318811 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41053.423956 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41068.387031 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41010.046734 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41001.734491 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41072.369731 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41039.473273 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41712.368155 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41620.035873 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41886.343786 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41685.139093 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41755.857111 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41751.643167 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41780.162689 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41774.574654 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 41746.265483 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0 42802.092868 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1 42806.571686 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2 42916.426971 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3 42754.119771 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu4 42726.914922 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu5 42667.894976 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu6 42773.639406 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu7 42751.095470 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 42774.751420 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0 42802.092868 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1 42806.571686 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2 42916.426971 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3 42754.119771 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu4 42726.914922 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu5 42667.894976 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu6 42773.639406 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu7 42751.095470 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 42774.751420 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 84242 # Transaction distribution
system.membus.trans_dist::ReadResp 84239 # Transaction distribution
system.membus.trans_dist::WriteReq 43998 # Transaction distribution
system.membus.trans_dist::WriteResp 43998 # Transaction distribution
system.membus.trans_dist::Writeback 6229 # Transaction distribution
system.membus.trans_dist::UpgradeReq 58563 # Transaction distribution
system.membus.trans_dist::UpgradeResp 47765 # Transaction distribution
system.membus.trans_dist::ReadExReq 50044 # Transaction distribution
system.membus.trans_dist::ReadExResp 3111 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 422189 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 422189 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1082703 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 1082703 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 57731 # Total snoops (count)
system.membus.snoop_fanout::samples 123701 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 123701 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 123701 # Request fanout histogram
system.membus.reqLayer0.occupancy 290076020 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 43.5 # Layer utilization (%)
system.membus.respLayer0.occupancy 312416500 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 46.8 # Layer utilization (%)
system.toL2Bus.trans_dist::ReadReq 371224 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 371216 # Transaction distribution
system.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 43998 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 43997 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 76237 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 29460 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 29459 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 161009 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 161004 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120675 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 121112 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120676 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120671 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120387 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120891 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120940 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120505 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 965857 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1759071 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1770038 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1776630 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1763929 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1758071 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1768584 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1767034 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1770802 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 14134159 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 321748 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 561380 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::7 561380 100.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 561380 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 655414034 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 98.3 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 160915376 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 24.1 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 161401861 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 24.2 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 160885313 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 24.1 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 160977419 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 24.1 # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy 160313901 # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization 24.0 # Layer utilization (%)
system.toL2Bus.respLayer5.occupancy 161018393 # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization 24.1 # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy 160998320 # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization 24.1 # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy 160391036 # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization 24.0 # Layer utilization (%)
Add short memtest run to quick regressions. Caveats: - Even though memtest is ISA-independent, it will only run for the Alpha builds, since there's no way to specify ISA-independent reference files and I didn't want to commit 3 copies since I'm not sure we want to run it for all the different ISAs anyway. - Reference outputs were generated on my laptop, so performance numbers will be low compared to zizzer. --HG-- extra : convert_revision : 210fe4abecc19fbab0b15402c6cb4863650bab66
2007-02-07 06:16:33 +01:00
---------- End Simulation Statistics ----------
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