gem5/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt

---------- Begin Simulation Statistics ----------
host_inst_rate                                 860135                       # Simulator instruction rate (inst/s)
host_mem_usage                                 198216                       # Number of bytes of host memory used
host_seconds                                   463.49                       # Real time elapsed on the host
host_tick_rate                             1224083493                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                   398664609                       # Number of instructions simulated
sim_seconds                                  0.567352                       # Number of seconds simulated
sim_ticks                                567351850000                       # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses           94754490                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 50827.368421                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 47827.368421                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits               94753540                       # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency       48286000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate          0.000010                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses                  950                       # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency     45436000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate     0.000010                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses             950                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses          73520730                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency        56000                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency        53000                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits              73517416                       # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency     185584000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate         0.000045                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses                3314                       # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency    175642000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate     0.000045                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses           3314                       # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.dcache.avg_refs               40527.713873                       # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.demand_accesses           168275220                       # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 54847.560976                       # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 51847.560976                       # average overall mshr miss latency
system.cpu.dcache.demand_hits               168270956                       # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency       233870000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate           0.000025                       # miss rate for demand accesses
system.cpu.dcache.demand_misses                  4264                       # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency    221078000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate      0.000025                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses             4264                       # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0                   0.802954                       # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0           3288.899192                       # Average occupied blocks per context
system.cpu.dcache.overall_accesses          168275220                       # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 54847.560976                       # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 51847.560976                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits              168270956                       # number of overall hits
system.cpu.dcache.overall_miss_latency      233870000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_rate          0.000025                       # miss rate for overall accesses
system.cpu.dcache.overall_misses                 4264                       # number of overall misses
system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency    221078000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate     0.000025                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses            4264                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements                    764                       # number of replacements
system.cpu.dcache.sampled_refs                   4152                       # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse               3288.899192                       # Cycle average of tags in use
system.cpu.dcache.total_refs                168271068                       # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks                      625                       # number of writebacks
system.cpu.dtb.data_accesses                168275276                       # DTB accesses
system.cpu.dtb.data_acv                             0                       # DTB access violations
system.cpu.dtb.data_hits                    168275220                       # DTB hits
system.cpu.dtb.data_misses                         56                       # DTB misses
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.read_accesses                 94754511                       # DTB read accesses
system.cpu.dtb.read_acv                             0                       # DTB read access violations
system.cpu.dtb.read_hits                     94754490                       # DTB read hits
system.cpu.dtb.read_misses                         21                       # DTB read misses
system.cpu.dtb.write_accesses                73520765                       # DTB write accesses
system.cpu.dtb.write_acv                            0                       # DTB write access violations
system.cpu.dtb.write_hits                    73520730                       # DTB write hits
system.cpu.dtb.write_misses                        35                       # DTB write misses
system.cpu.icache.ReadReq_accesses          398664666                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 50648.516199                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 47648.516199                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits              398660993                       # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency      186032000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate          0.000009                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses                 3673                       # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency    175013000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate     0.000009                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses            3673                       # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.icache.avg_refs               108538.250204                       # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.demand_accesses           398664666                       # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 50648.516199                       # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 47648.516199                       # average overall mshr miss latency
system.cpu.icache.demand_hits               398660993                       # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency       186032000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate           0.000009                       # miss rate for demand accesses
system.cpu.icache.demand_misses                  3673                       # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency    175013000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate      0.000009                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses             3673                       # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.occ_%::0                   0.876526                       # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0           1795.124700                       # Average occupied blocks per context
system.cpu.icache.overall_accesses          398664666                       # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 50648.516199                       # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 47648.516199                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.icache.overall_hits              398660993                       # number of overall hits
system.cpu.icache.overall_miss_latency      186032000                       # number of overall miss cycles
system.cpu.icache.overall_miss_rate          0.000009                       # miss rate for overall accesses
system.cpu.icache.overall_misses                 3673                       # number of overall misses
system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency    175013000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate     0.000009                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses            3673                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.replacements                   1769                       # number of replacements
system.cpu.icache.sampled_refs                   3673                       # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse               1795.124700                       # Cycle average of tags in use
system.cpu.icache.total_refs                398660993                       # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks                        0                       # number of writebacks
system.cpu.idle_fraction                            0                       # Percentage of idle cycles
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.fetch_accesses               398664839                       # ITB accesses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_hits                   398664666                       # ITB hits
system.cpu.itb.fetch_misses                       173                       # ITB misses
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.l2cache.ReadExReq_accesses            3202                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency    166504000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses              3202                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency    128080000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses         3202                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses              4623                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits                   585                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency     209976000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate         0.873459                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses                4038                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency    161520000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate     0.873459                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses           4038                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses            112                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency        52000                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency      5824000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses              112                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency      4480000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses          112                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses             625                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits                 625                       # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs                  0.120240                       # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.demand_accesses               7825                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_hits                    585                       # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency      376480000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate          0.925240                       # miss rate for demand accesses
system.cpu.l2cache.demand_misses                 7240                       # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency    289600000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate     0.925240                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses            7240                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0                  0.101996                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1                  0.011352                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0          3342.203160                       # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1           371.972955                       # Average occupied blocks per context
system.cpu.l2cache.overall_accesses              7825                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits                   585                       # number of overall hits
system.cpu.l2cache.overall_miss_latency     376480000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate         0.925240                       # miss rate for overall accesses
system.cpu.l2cache.overall_misses                7240                       # number of overall misses
system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency    289600000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate     0.925240                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses           7240                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements                    15                       # number of replacements
system.cpu.l2cache.sampled_refs                  4491                       # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse              3714.176115                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                     540                       # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks                       0                       # number of writebacks
system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
system.cpu.numCycles                       1134703700                       # number of cpu cycles simulated
system.cpu.num_insts                        398664609                       # Number of instructions executed
system.cpu.num_refs                         174183455                       # Number of memory references
system.cpu.workload.PROG:num_syscalls             215                       # Number of system calls

---------- End Simulation Statistics   ----------