Update 30.eon simple-timing for 8k blk_size. It's strange this is necessary because simple-atomic doesn't seem affected.
--HG-- extra : convert_revision : 6a8c77f0ca76eb06ac7eb5216af6adba3759c4c7
This commit is contained in:
Gabe Black
parent
b2fd2a813d
commit
3d4fe3f459
4 changed files with 92 additions and 141 deletions
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@ -7,21 +7,6 @@ max_tick=0
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output_file=cout
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progress_interval=0
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[exetrace]
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intel_format=false
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legion_lockstep=false
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pc_symbol=true
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print_cpseq=false
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print_cycle=true
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print_data=true
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print_effaddr=true
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print_fetchseq=false
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print_iregs=false
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print_opclass=true
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print_thread=true
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speculative=true
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trace_system=client
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[serialize]
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count=10
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cycle=0
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@ -197,11 +182,11 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp
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[system.cpu.workload]
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type=LiveProcess
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cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
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cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/linux/simple-timing
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cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/linux/simple-timing
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egid=100
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env=
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euid=100
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executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
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executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/eon
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gid=100
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input=cin
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output=cout
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@ -223,14 +208,6 @@ type=PhysicalMemory
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file=
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latency=1
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range=0:134217727
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zero=false
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port=system.membus.port[0]
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[trace]
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bufsize=0
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cycle=0
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dump_on_exit=false
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file=cout
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flags=
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ignore=
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start=0
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@ -10,6 +10,7 @@ type=PhysicalMemory
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file=
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range=[0,134217727]
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latency=1
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zero=false
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[system]
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type=System
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@ -26,11 +27,11 @@ responder_set=false
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[system.cpu.workload]
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type=LiveProcess
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cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
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executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
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executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/eon
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input=cin
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output=cout
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env=
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cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/linux/simple-timing
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cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/linux/simple-timing
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system=system
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uid=100
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euid=100
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@ -178,15 +179,6 @@ prefetch_use_cpu_id=true
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prefetch_data_accesses_only=false
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hit_latency=1
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[trace]
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flags=
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start=0
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cycle=0
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bufsize=0
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file=cout
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dump_on_exit=false
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ignore=
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[stats]
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descriptions=true
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project_name=test
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@ -204,25 +196,6 @@ dump_cycle=0
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dump_period=0
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ignore_events=
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[random]
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seed=1
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[exetrace]
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speculative=true
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print_cycle=true
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print_opclass=true
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print_thread=true
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print_effaddr=true
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print_data=true
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print_iregs=false
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print_fetchseq=false
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print_cpseq=false
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print_reg_delta=false
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pc_symbol=true
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intel_format=false
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legion_lockstep=false
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trace_system=client
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[statsreset]
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reset_cycle=0
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@ -1,13 +1,13 @@
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---------- Begin Simulation Statistics ----------
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host_inst_rate 490401 # Simulator instruction rate (inst/s)
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host_mem_usage 178744 # Number of bytes of host memory used
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host_seconds 812.94 # Real time elapsed on the host
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host_tick_rate 734822 # Simulator tick rate (ticks/s)
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host_inst_rate 689508 # Simulator instruction rate (inst/s)
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host_mem_usage 185012 # Number of bytes of host memory used
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host_seconds 578.19 # Real time elapsed on the host
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host_tick_rate 1033135 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 398664450 # Number of instructions simulated
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sim_seconds 0.000597 # Number of seconds simulated
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sim_ticks 597363012 # Number of ticks simulated
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sim_ticks 597346012 # Number of ticks simulated
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system.cpu.dcache.ReadReq_accesses 94754482 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 3956.610526 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2956.610526 # average ReadReq mshr miss latency
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@ -19,49 +19,49 @@ system.cpu.dcache.ReadReq_mshr_miss_latency 2808780 #
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 73520727 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 3939.646399 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2939.646399 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 73517520 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 12634446 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_avg_miss_latency 3940.471580 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2940.471580 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 73517525 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 12617390 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.000044 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 3207 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 9427446 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_misses 3202 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 9415390 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 3207 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 40478.963676 # Average number of references to valid blocks.
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system.cpu.dcache.WriteReq_mshr_misses 3202 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 40527.711224 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 168275209 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 3943.523214 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 2943.523214 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 168271052 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 16393226 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_avg_miss_latency 3944.164258 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 2944.164258 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 168271057 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 16376170 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 4157 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses 4152 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 12236226 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency 12224170 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 4157 # number of demand (read+write) MSHR misses
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system.cpu.dcache.demand_mshr_misses 4152 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 168275209 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 3943.523214 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 2943.523214 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 168271052 # number of overall hits
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system.cpu.dcache.overall_miss_latency 16393226 # number of overall miss cycles
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system.cpu.dcache.overall_avg_miss_latency 3944.164258 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 2944.164258 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 168271057 # number of overall hits
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system.cpu.dcache.overall_miss_latency 16376170 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 4157 # number of overall misses
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system.cpu.dcache.overall_misses 4152 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 12236226 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency 12224170 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 4157 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_misses 4152 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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@ -74,24 +74,24 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0
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system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.dcache.replacements 764 # number of replacements
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system.cpu.dcache.sampled_refs 4157 # Sample count of references to valid blocks.
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system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 3222.448687 # Cycle average of tags in use
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system.cpu.dcache.total_refs 168271052 # Total number of references to valid blocks.
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system.cpu.dcache.tagsinuse 3222.413784 # Cycle average of tags in use
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system.cpu.dcache.total_refs 168271057 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 625 # number of writebacks
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system.cpu.icache.ReadReq_accesses 398664451 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 3820.892216 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 2820.892216 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_avg_miss_latency 3820.906097 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 2820.906097 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 398660777 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 14037958 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency 14038009 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 3674 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_miss_latency 10363958 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency 10364009 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 3674 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 108508.649156 # Average number of references to valid blocks.
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system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
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@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 398664451 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 3820.892216 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 2820.892216 # average overall mshr miss latency
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system.cpu.icache.demand_avg_miss_latency 3820.906097 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 2820.906097 # average overall mshr miss latency
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system.cpu.icache.demand_hits 398660777 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 14037958 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency 14038009 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses
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system.cpu.icache.demand_misses 3674 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 10363958 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency 10364009 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000009 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 3674 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 398664451 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 3820.892216 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 2820.892216 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.icache.overall_avg_miss_latency 3820.906097 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 2820.906097 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 398660777 # number of overall hits
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system.cpu.icache.overall_miss_latency 14037958 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency 14038009 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses
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system.cpu.icache.overall_misses 3674 # number of overall misses
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 10363958 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency 10364009 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.000009 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 3674 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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@ -138,57 +138,57 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
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system.cpu.icache.replacements 1770 # number of replacements
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system.cpu.icache.sampled_refs 3674 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 1765.884663 # Cycle average of tags in use
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system.cpu.icache.tagsinuse 1765.882838 # Cycle average of tags in use
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system.cpu.icache.total_refs 398660777 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.l2cache.ReadReq_accesses 7831 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_avg_miss_latency 2982.860028 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1924.618942 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_accesses 7826 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2983.265505 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1924.984530 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 651 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 21416935 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.916869 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 7180 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 13818764 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.916869 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 7180 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 625 # number of WriteReqNoAck|Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.WriteReqNoAck|Writeback_hits 625 # number of WriteReqNoAck|Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.177716 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.ReadReq_miss_latency 21404930 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.916816 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 7175 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 13811764 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.916816 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 7175 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 625 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 625 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.177840 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 7831 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2982.860028 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1924.618942 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_accesses 7826 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2983.265505 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1924.984530 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 651 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 21416935 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.916869 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 7180 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_miss_latency 21404930 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.916816 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 7175 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 13818764 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.916869 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 7180 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 13811764 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.916816 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 7175 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 8456 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2982.860028 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1924.618942 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_accesses 8451 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2983.265505 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1924.984530 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 1276 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 21416935 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.849101 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 7180 # number of overall misses
|
||||
system.cpu.l2cache.overall_miss_latency 21404930 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.849012 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 7175 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 13818764 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.849101 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 7180 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 13811764 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.849012 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 7175 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -201,14 +201,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 7180 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 7175 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 6344.085280 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 6344.042673 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1276 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 597363012 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 597346012 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 398664450 # Number of instructions executed
|
||||
system.cpu.num_refs 174183390 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
getting pixel output filename pixels_out.cook
|
||||
opening control file chair.control.cook
|
||||
|
|
|
|||
Loading…
Reference in a new issue