2008-10-21 01:00:07 +02:00
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---------- Begin Simulation Statistics ----------
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2011-02-08 04:23:13 +01:00
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host_inst_rate 67358 # Simulator instruction rate (inst/s)
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host_mem_usage 313516 # Number of bytes of host memory used
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host_seconds 846.09 # Real time elapsed on the host
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host_tick_rate 2246601111 # Simulator tick rate (ticks/s)
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2008-10-21 01:00:07 +02:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-01-18 23:30:06 +01:00
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sim_insts 56990797 # Number of instructions simulated
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sim_seconds 1.900831 # Number of seconds simulated
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sim_ticks 1900831034500 # Number of ticks simulated
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2009-03-07 23:30:55 +01:00
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system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2011-01-18 23:30:06 +01:00
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system.cpu0.BPredUnit.BTBHits 5875698 # Number of BTB hits
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system.cpu0.BPredUnit.BTBLookups 11164328 # Number of BTB lookups
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system.cpu0.BPredUnit.RASInCorrect 27744 # Number of incorrect RAS predictions.
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system.cpu0.BPredUnit.condIncorrect 509294 # Number of conditional branches incorrect
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system.cpu0.BPredUnit.condPredicted 10430748 # Number of conditional branches predicted
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system.cpu0.BPredUnit.lookups 12489171 # Number of BP lookups
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system.cpu0.BPredUnit.usedRAS 879952 # Number of times the RAS was used to get a target.
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system.cpu0.commit.COM:branches 7522146 # Number of branches committed
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system.cpu0.commit.COM:bw_lim_events 923087 # number cycles where commit BW limit reached
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2008-10-21 01:00:07 +02:00
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system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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2011-01-18 23:30:06 +01:00
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system.cpu0.commit.COM:committed_per_cycle::samples 78252168 # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::mean 0.636069 # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::stdev 1.403085 # Number of insts commited each cycle
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2009-07-07 00:49:48 +02:00
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system.cpu0.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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2011-01-18 23:30:06 +01:00
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system.cpu0.commit.COM:committed_per_cycle::0 56997236 72.84% 72.84% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::1 9310198 11.90% 84.74% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::2 5423748 6.93% 91.67% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::3 2443659 3.12% 94.79% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::4 1857092 2.37% 97.16% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::5 632524 0.81% 97.97% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::6 342942 0.44% 98.41% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::7 321682 0.41% 98.82% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::8 923087 1.18% 100.00% # Number of insts commited each cycle
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2009-07-07 00:49:48 +02:00
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system.cpu0.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
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2011-01-18 23:30:06 +01:00
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system.cpu0.commit.COM:committed_per_cycle::total 78252168 # Number of insts commited each cycle
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system.cpu0.commit.COM:count 49773781 # Number of instructions committed
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2011-02-08 04:23:13 +01:00
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system.cpu0.commit.COM:fp_insts 245595 # Number of committed floating point instructions.
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system.cpu0.commit.COM:function_calls 636046 # Number of function calls committed.
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system.cpu0.commit.COM:int_insts 46098576 # Number of committed integer instructions.
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2011-01-18 23:30:06 +01:00
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system.cpu0.commit.COM:loads 7894849 # Number of loads committed
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2010-09-22 08:07:35 +02:00
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system.cpu0.commit.COM:membars 191655 # Number of memory barriers committed
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2011-01-18 23:30:06 +01:00
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system.cpu0.commit.COM:refs 13318728 # Number of memory references committed
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2008-10-21 01:00:07 +02:00
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system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed
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2011-01-18 23:30:06 +01:00
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system.cpu0.commit.branchMispredicts 652792 # The number of times a branch was mispredicted
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system.cpu0.commit.commitCommittedInsts 49773781 # The number of committed instructions
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system.cpu0.commit.commitNonSpecStalls 564764 # The number of times commit has been forced to stall to communicate backwards
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system.cpu0.commit.commitSquashedInsts 7279166 # The number of squashed insts skipped by commit
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system.cpu0.committedInsts 46913211 # Number of Instructions Simulated
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system.cpu0.committedInsts_total 46913211 # Number of Instructions Simulated
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system.cpu0.cpi 2.403631 # CPI: Cycles Per Instruction
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system.cpu0.cpi_total 2.403631 # CPI: Total CPI of All Threads
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system.cpu0.dcache.LoadLockedReq_accesses::0 178258 # number of LoadLockedReq accesses(hits+misses)
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system.cpu0.dcache.LoadLockedReq_accesses::total 178258 # number of LoadLockedReq accesses(hits+misses)
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system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14381.476316 # average LoadLockedReq miss latency
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2010-02-25 19:08:41 +01:00
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system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
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system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
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2011-01-18 23:30:06 +01:00
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system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10558.033333 # average LoadLockedReq mshr miss latency
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system.cpu0.dcache.LoadLockedReq_hits::0 158899 # number of LoadLockedReq hits
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system.cpu0.dcache.LoadLockedReq_hits::total 158899 # number of LoadLockedReq hits
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system.cpu0.dcache.LoadLockedReq_miss_latency 278411000 # number of LoadLockedReq miss cycles
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system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.108601 # miss rate for LoadLockedReq accesses
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system.cpu0.dcache.LoadLockedReq_misses::0 19359 # number of LoadLockedReq misses
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system.cpu0.dcache.LoadLockedReq_misses::total 19359 # number of LoadLockedReq misses
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system.cpu0.dcache.LoadLockedReq_mshr_hits 4359 # number of LoadLockedReq MSHR hits
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system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 158370500 # number of LoadLockedReq MSHR miss cycles
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system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.084148 # mshr miss rate for LoadLockedReq accesses
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2010-02-25 19:08:41 +01:00
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system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
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system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
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2011-01-18 23:30:06 +01:00
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system.cpu0.dcache.LoadLockedReq_mshr_misses 15000 # number of LoadLockedReq MSHR misses
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system.cpu0.dcache.ReadReq_accesses::0 8018067 # number of ReadReq accesses(hits+misses)
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system.cpu0.dcache.ReadReq_accesses::total 8018067 # number of ReadReq accesses(hits+misses)
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system.cpu0.dcache.ReadReq_avg_miss_latency::0 23754.598189 # average ReadReq miss latency
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2010-02-25 19:08:41 +01:00
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system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
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system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
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2011-01-18 23:30:06 +01:00
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system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23766.786651 # average ReadReq mshr miss latency
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2008-10-21 01:00:07 +02:00
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system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
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2011-01-18 23:30:06 +01:00
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system.cpu0.dcache.ReadReq_hits::0 6640677 # number of ReadReq hits
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system.cpu0.dcache.ReadReq_hits::total 6640677 # number of ReadReq hits
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system.cpu0.dcache.ReadReq_miss_latency 32719346000 # number of ReadReq miss cycles
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system.cpu0.dcache.ReadReq_miss_rate::0 0.171786 # miss rate for ReadReq accesses
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system.cpu0.dcache.ReadReq_misses::0 1377390 # number of ReadReq misses
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system.cpu0.dcache.ReadReq_misses::total 1377390 # number of ReadReq misses
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system.cpu0.dcache.ReadReq_mshr_hits 392262 # number of ReadReq MSHR hits
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system.cpu0.dcache.ReadReq_mshr_miss_latency 23413327000 # number of ReadReq MSHR miss cycles
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system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.122864 # mshr miss rate for ReadReq accesses
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2010-02-25 19:08:41 +01:00
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system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
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system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
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2011-01-18 23:30:06 +01:00
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system.cpu0.dcache.ReadReq_mshr_misses 985128 # number of ReadReq MSHR misses
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system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 920863000 # number of ReadReq MSHR uncacheable cycles
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system.cpu0.dcache.StoreCondReq_accesses::0 185114 # number of StoreCondReq accesses(hits+misses)
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system.cpu0.dcache.StoreCondReq_accesses::total 185114 # number of StoreCondReq accesses(hits+misses)
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system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 13329.315068 # average StoreCondReq miss latency
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2010-02-25 19:08:41 +01:00
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system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
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system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
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2011-01-18 23:30:06 +01:00
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system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 10326.164384 # average StoreCondReq mshr miss latency
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system.cpu0.dcache.StoreCondReq_hits::0 181464 # number of StoreCondReq hits
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system.cpu0.dcache.StoreCondReq_hits::total 181464 # number of StoreCondReq hits
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system.cpu0.dcache.StoreCondReq_miss_latency 48652000 # number of StoreCondReq miss cycles
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system.cpu0.dcache.StoreCondReq_miss_rate::0 0.019718 # miss rate for StoreCondReq accesses
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system.cpu0.dcache.StoreCondReq_misses::0 3650 # number of StoreCondReq misses
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system.cpu0.dcache.StoreCondReq_misses::total 3650 # number of StoreCondReq misses
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system.cpu0.dcache.StoreCondReq_mshr_miss_latency 37690500 # number of StoreCondReq MSHR miss cycles
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system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.019718 # mshr miss rate for StoreCondReq accesses
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2010-02-25 19:08:41 +01:00
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system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
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system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
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2011-01-18 23:30:06 +01:00
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system.cpu0.dcache.StoreCondReq_mshr_misses 3650 # number of StoreCondReq MSHR misses
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system.cpu0.dcache.WriteReq_accesses::0 5223711 # number of WriteReq accesses(hits+misses)
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system.cpu0.dcache.WriteReq_accesses::total 5223711 # number of WriteReq accesses(hits+misses)
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system.cpu0.dcache.WriteReq_avg_miss_latency::0 32400.753552 # average WriteReq miss latency
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2010-02-25 19:08:41 +01:00
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system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
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system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
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2011-01-18 23:30:06 +01:00
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system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 30590.522294 # average WriteReq mshr miss latency
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2008-10-21 01:00:07 +02:00
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system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
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2011-01-18 23:30:06 +01:00
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system.cpu0.dcache.WriteReq_hits::0 3606992 # number of WriteReq hits
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system.cpu0.dcache.WriteReq_hits::total 3606992 # number of WriteReq hits
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system.cpu0.dcache.WriteReq_miss_latency 52382913882 # number of WriteReq miss cycles
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system.cpu0.dcache.WriteReq_miss_rate::0 0.309496 # miss rate for WriteReq accesses
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system.cpu0.dcache.WriteReq_misses::0 1616719 # number of WriteReq misses
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system.cpu0.dcache.WriteReq_misses::total 1616719 # number of WriteReq misses
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system.cpu0.dcache.WriteReq_mshr_hits 1353304 # number of WriteReq MSHR hits
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system.cpu0.dcache.WriteReq_mshr_miss_latency 8058002430 # number of WriteReq MSHR miss cycles
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system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.050427 # mshr miss rate for WriteReq accesses
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2010-02-25 19:08:41 +01:00
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system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
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system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
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2011-01-18 23:30:06 +01:00
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system.cpu0.dcache.WriteReq_mshr_misses 263415 # number of WriteReq MSHR misses
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system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1320187498 # number of WriteReq MSHR uncacheable cycles
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system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8768.456221 # average number of cycles each access was blocked
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2010-11-08 20:58:24 +01:00
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system.cpu0.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked
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2011-01-18 23:30:06 +01:00
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system.cpu0.dcache.avg_refs 8.499270 # Average number of references to valid blocks.
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system.cpu0.dcache.blocked::no_mshrs 83762 # number of cycles access was blocked
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2010-11-08 20:58:24 +01:00
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system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked
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2011-01-18 23:30:06 +01:00
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system.cpu0.dcache.blocked_cycles::no_mshrs 734463430 # number of cycles access was blocked
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2010-11-08 20:58:24 +01:00
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system.cpu0.dcache.blocked_cycles::no_targets 150500 # number of cycles access was blocked
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2008-10-21 01:00:07 +02:00
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system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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2011-01-18 23:30:06 +01:00
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system.cpu0.dcache.demand_accesses::0 13241778 # number of demand (read+write) accesses
|
2010-02-25 19:08:41 +01:00
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system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
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2011-01-18 23:30:06 +01:00
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system.cpu0.dcache.demand_accesses::total 13241778 # number of demand (read+write) accesses
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system.cpu0.dcache.demand_avg_miss_latency::0 28423.233717 # average overall miss latency
|
2010-02-25 19:08:41 +01:00
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|
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system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
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|
|
|
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system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency
|
2011-01-18 23:30:06 +01:00
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system.cpu0.dcache.demand_avg_mshr_miss_latency 25206.444175 # average overall mshr miss latency
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system.cpu0.dcache.demand_hits::0 10247669 # number of demand (read+write) hits
|
2010-02-25 19:08:41 +01:00
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|
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system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits
|
2011-01-18 23:30:06 +01:00
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system.cpu0.dcache.demand_hits::total 10247669 # number of demand (read+write) hits
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|
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system.cpu0.dcache.demand_miss_latency 85102259882 # number of demand (read+write) miss cycles
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system.cpu0.dcache.demand_miss_rate::0 0.226111 # miss rate for demand accesses
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2010-02-25 19:08:41 +01:00
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|
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system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
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|
|
|
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system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
|
2011-01-18 23:30:06 +01:00
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|
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system.cpu0.dcache.demand_misses::0 2994109 # number of demand (read+write) misses
|
2010-02-25 19:08:41 +01:00
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|
|
system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses
|
2011-01-18 23:30:06 +01:00
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|
|
system.cpu0.dcache.demand_misses::total 2994109 # number of demand (read+write) misses
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|
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system.cpu0.dcache.demand_mshr_hits 1745566 # number of demand (read+write) MSHR hits
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system.cpu0.dcache.demand_mshr_miss_latency 31471329430 # number of demand (read+write) MSHR miss cycles
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|
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system.cpu0.dcache.demand_mshr_miss_rate::0 0.094288 # mshr miss rate for demand accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
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|
|
|
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system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
2011-01-18 23:30:06 +01:00
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|
|
system.cpu0.dcache.demand_mshr_misses 1248543 # number of demand (read+write) MSHR misses
|
2008-10-21 01:00:07 +02:00
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system.cpu0.dcache.fast_writes 0 # number of fast writes performed
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system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
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system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-01-18 23:30:06 +01:00
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|
|
system.cpu0.dcache.occ_%::0 0.973184 # Average percentage of cache occupancy
|
2010-09-22 08:07:35 +02:00
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|
|
system.cpu0.dcache.occ_%::1 -0.001953 # Average percentage of cache occupancy
|
2011-01-18 23:30:06 +01:00
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|
system.cpu0.dcache.occ_blocks::0 498.270236 # Average occupied blocks per context
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu0.dcache.occ_blocks::1 -1.000000 # Average occupied blocks per context
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.dcache.overall_accesses::0 13241778 # number of overall (read+write) accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.dcache.overall_accesses::total 13241778 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu0.dcache.overall_avg_miss_latency::0 28423.233717 # average overall miss latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
|
|
|
|
|
system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency 25206.444175 # average overall mshr miss latency
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.dcache.overall_hits::0 10247669 # number of overall hits
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu0.dcache.overall_hits::1 0 # number of overall hits
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.dcache.overall_hits::total 10247669 # number of overall hits
|
|
|
|
|
system.cpu0.dcache.overall_miss_latency 85102259882 # number of overall miss cycles
|
|
|
|
|
system.cpu0.dcache.overall_miss_rate::0 0.226111 # miss rate for overall accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
|
|
|
system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.dcache.overall_misses::0 2994109 # number of overall misses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu0.dcache.overall_misses::1 0 # number of overall misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.dcache.overall_misses::total 2994109 # number of overall misses
|
|
|
|
|
system.cpu0.dcache.overall_mshr_hits 1745566 # number of overall MSHR hits
|
|
|
|
|
system.cpu0.dcache.overall_mshr_miss_latency 31471329430 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu0.dcache.overall_mshr_miss_rate::0 0.094288 # mshr miss rate for overall accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.dcache.overall_mshr_misses 1248543 # number of overall MSHR misses
|
|
|
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency 2241050498 # number of overall MSHR uncacheable cycles
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.dcache.replacements 1246737 # number of replacements
|
|
|
|
|
system.cpu0.dcache.sampled_refs 1247249 # Sample count of references to valid blocks.
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.dcache.tagsinuse 497.270236 # Cycle average of tags in use
|
|
|
|
|
system.cpu0.dcache.total_refs 10600706 # Total number of references to valid blocks.
|
2010-09-09 20:40:19 +02:00
|
|
|
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.dcache.writebacks 721582 # number of writebacks
|
|
|
|
|
system.cpu0.decode.DECODE:BlockedCycles 33790460 # Number of cycles decode is blocked
|
|
|
|
|
system.cpu0.decode.DECODE:BranchMispred 33337 # Number of times decode detected a branch misprediction
|
|
|
|
|
system.cpu0.decode.DECODE:BranchResolved 520850 # Number of times decode resolved a branch
|
|
|
|
|
system.cpu0.decode.DECODE:DecodedInsts 62592464 # Number of instructions handled by decode
|
|
|
|
|
system.cpu0.decode.DECODE:IdleCycles 32176672 # Number of cycles decode is idle
|
|
|
|
|
system.cpu0.decode.DECODE:RunCycles 11304141 # Number of cycles decode is running
|
|
|
|
|
system.cpu0.decode.DECODE:SquashCycles 1271125 # Number of cycles decode is squashing
|
|
|
|
|
system.cpu0.decode.DECODE:SquashedInsts 100674 # Number of squashed instructions handled by decode
|
|
|
|
|
system.cpu0.decode.DECODE:UnblockCycles 980894 # Number of cycles decode is unblocking
|
|
|
|
|
system.cpu0.dtb.data_accesses 795039 # DTB accesses
|
2010-12-08 01:19:57 +01:00
|
|
|
system.cpu0.dtb.data_acv 690 # DTB access violations
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.dtb.data_hits 14240441 # DTB hits
|
|
|
|
|
system.cpu0.dtb.data_misses 32243 # DTB misses
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
|
|
|
|
|
system.cpu0.dtb.fetch_acv 0 # ITB acv
|
|
|
|
|
system.cpu0.dtb.fetch_hits 0 # ITB hits
|
|
|
|
|
system.cpu0.dtb.fetch_misses 0 # ITB misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.dtb.read_accesses 599364 # DTB read accesses
|
|
|
|
|
system.cpu0.dtb.read_acv 521 # DTB read access violations
|
|
|
|
|
system.cpu0.dtb.read_hits 8656203 # DTB read hits
|
|
|
|
|
system.cpu0.dtb.read_misses 26609 # DTB read misses
|
|
|
|
|
system.cpu0.dtb.write_accesses 195675 # DTB write accesses
|
|
|
|
|
system.cpu0.dtb.write_acv 169 # DTB write access violations
|
|
|
|
|
system.cpu0.dtb.write_hits 5584238 # DTB write hits
|
|
|
|
|
system.cpu0.dtb.write_misses 5634 # DTB write misses
|
|
|
|
|
system.cpu0.fetch.Branches 12489171 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu0.fetch.CacheLines 7790772 # Number of cache lines fetched
|
|
|
|
|
system.cpu0.fetch.Cycles 12447663 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu0.fetch.IcacheSquashes 374479 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu0.fetch.Insts 63679882 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu0.fetch.MiscStallCycles 30613 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
|
|
|
system.cpu0.fetch.SquashCycles 745308 # Number of cycles fetch has spent squashing
|
|
|
|
|
system.cpu0.fetch.branchRate 0.110757 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu0.fetch.icacheStallCycles 7790769 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu0.fetch.predictedBranches 6755650 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu0.fetch.rate 0.564728 # Number of inst fetches per cycle
|
|
|
|
|
system.cpu0.fetch.rateDist::samples 79523293 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu0.fetch.rateDist::mean 0.800770 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu0.fetch.rateDist::stdev 2.103978 # Number of instructions fetched each cycle (Total)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.fetch.rateDist::0 67075630 84.35% 84.35% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu0.fetch.rateDist::1 894785 1.13% 85.47% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu0.fetch.rateDist::2 1774565 2.23% 87.70% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu0.fetch.rateDist::3 813228 1.02% 88.73% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu0.fetch.rateDist::4 2745570 3.45% 92.18% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu0.fetch.rateDist::5 583311 0.73% 92.91% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu0.fetch.rateDist::6 681126 0.86% 93.77% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu0.fetch.rateDist::7 829932 1.04% 94.81% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu0.fetch.rateDist::8 4125146 5.19% 100.00% # Number of instructions fetched each cycle (Total)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.fetch.rateDist::total 79523293 # Number of instructions fetched each cycle (Total)
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu0.fp_regfile_reads 120916 # number of floating regfile reads
|
|
|
|
|
system.cpu0.fp_regfile_writes 122710 # number of floating regfile writes
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.icache.ReadReq_accesses::0 7790772 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.icache.ReadReq_accesses::total 7790772 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::0 15066.907100 # average ReadReq miss latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
|
|
|
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12016.512006 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu0.icache.ReadReq_hits::0 6933292 # number of ReadReq hits
|
|
|
|
|
system.cpu0.icache.ReadReq_hits::total 6933292 # number of ReadReq hits
|
|
|
|
|
system.cpu0.icache.ReadReq_miss_latency 12919571500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu0.icache.ReadReq_miss_rate::0 0.110064 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu0.icache.ReadReq_misses::0 857480 # number of ReadReq misses
|
|
|
|
|
system.cpu0.icache.ReadReq_misses::total 857480 # number of ReadReq misses
|
|
|
|
|
system.cpu0.icache.ReadReq_mshr_hits 36653 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency 9863477500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.105359 # mshr miss rate for ReadReq accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.icache.ReadReq_mshr_misses 820827 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs 11372.727273 # average number of cycles each access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.icache.avg_refs 8.447909 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu0.icache.blocked::no_mshrs 55 # number of cycles access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2010-12-08 01:19:57 +01:00
|
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 625500 # number of cycles access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.icache.demand_accesses::0 7790772 # number of demand (read+write) accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.icache.demand_accesses::total 7790772 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu0.icache.demand_avg_miss_latency::0 15066.907100 # average overall miss latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency
|
|
|
|
|
system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency 12016.512006 # average overall mshr miss latency
|
|
|
|
|
system.cpu0.icache.demand_hits::0 6933292 # number of demand (read+write) hits
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.icache.demand_hits::total 6933292 # number of demand (read+write) hits
|
|
|
|
|
system.cpu0.icache.demand_miss_latency 12919571500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu0.icache.demand_miss_rate::0 0.110064 # miss rate for demand accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
|
|
|
|
system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.icache.demand_misses::0 857480 # number of demand (read+write) misses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.icache.demand_misses::total 857480 # number of demand (read+write) misses
|
|
|
|
|
system.cpu0.icache.demand_mshr_hits 36653 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu0.icache.demand_mshr_miss_latency 9863477500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu0.icache.demand_mshr_miss_rate::0 0.105359 # mshr miss rate for demand accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.icache.demand_mshr_misses 820827 # number of demand (read+write) MSHR misses
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu0.icache.occ_%::0 0.995823 # Average percentage of cache occupancy
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.icache.occ_blocks::0 509.861442 # Average occupied blocks per context
|
|
|
|
|
system.cpu0.icache.overall_accesses::0 7790772 # number of overall (read+write) accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.icache.overall_accesses::total 7790772 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu0.icache.overall_avg_miss_latency::0 15066.907100 # average overall miss latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency
|
|
|
|
|
system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency 12016.512006 # average overall mshr miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.icache.overall_hits::0 6933292 # number of overall hits
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu0.icache.overall_hits::1 0 # number of overall hits
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.icache.overall_hits::total 6933292 # number of overall hits
|
|
|
|
|
system.cpu0.icache.overall_miss_latency 12919571500 # number of overall miss cycles
|
|
|
|
|
system.cpu0.icache.overall_miss_rate::0 0.110064 # miss rate for overall accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
|
|
|
system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.icache.overall_misses::0 857480 # number of overall misses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu0.icache.overall_misses::1 0 # number of overall misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.icache.overall_misses::total 857480 # number of overall misses
|
|
|
|
|
system.cpu0.icache.overall_mshr_hits 36653 # number of overall MSHR hits
|
|
|
|
|
system.cpu0.icache.overall_mshr_miss_latency 9863477500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu0.icache.overall_mshr_miss_rate::0 0.105359 # mshr miss rate for overall accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.icache.overall_mshr_misses 820827 # number of overall MSHR misses
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.icache.replacements 820200 # number of replacements
|
|
|
|
|
system.cpu0.icache.sampled_refs 820711 # Sample count of references to valid blocks.
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.icache.tagsinuse 509.861442 # Cycle average of tags in use
|
|
|
|
|
system.cpu0.icache.total_refs 6933292 # Total number of references to valid blocks.
|
2010-11-08 20:58:24 +01:00
|
|
|
system.cpu0.icache.warmup_cycle 24435382000 # Cycle when the warmup percentage was hit.
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.icache.writebacks 107 # number of writebacks
|
|
|
|
|
system.cpu0.idleCycles 33238734 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu0.iew.EXEC:branches 8088887 # Number of branches executed
|
|
|
|
|
system.cpu0.iew.EXEC:nop 3190702 # number of nop insts executed
|
|
|
|
|
system.cpu0.iew.EXEC:rate 0.446643 # Inst execution rate
|
|
|
|
|
system.cpu0.iew.EXEC:refs 14307235 # number of memory reference insts executed
|
|
|
|
|
system.cpu0.iew.EXEC:stores 5602635 # Number of stores executed
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu0.iew.EXEC:swp 0 # number of swp insts executed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.iew.WB:consumers 31606218 # num instructions consuming a value
|
|
|
|
|
system.cpu0.iew.WB:count 49988672 # cumulative count of insts written-back
|
|
|
|
|
system.cpu0.iew.WB:fanout 0.757998 # average fanout of values written-back
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.iew.WB:producers 23957449 # num instructions producing a value
|
|
|
|
|
system.cpu0.iew.WB:rate 0.443311 # insts written-back per cycle
|
|
|
|
|
system.cpu0.iew.WB:sent 50070625 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu0.iew.branchMispredicts 711853 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu0.iew.iewBlockCycles 9019183 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu0.iew.iewDispLoadInsts 9134564 # Number of dispatched load instructions
|
|
|
|
|
system.cpu0.iew.iewDispNonSpecInsts 1512032 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu0.iew.iewDispSquashedInsts 755923 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu0.iew.iewDispStoreInsts 5843380 # Number of dispatched store instructions
|
|
|
|
|
system.cpu0.iew.iewDispatchedInsts 57163450 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu0.iew.iewExecLoadInsts 8704600 # Number of load instructions executed
|
|
|
|
|
system.cpu0.iew.iewExecSquashedInsts 462366 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu0.iew.iewExecutedInsts 50364381 # Number of executed instructions
|
|
|
|
|
system.cpu0.iew.iewIQFullEvents 59583 # Number of times the IQ has become full, causing a stall
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.iew.iewLSQFullEvents 7004 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu0.iew.iewSquashCycles 1271125 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu0.iew.iewUnblockCycles 547384 # Number of cycles IEW is unblocking
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.iew.lsq.thread.0.cacheBlocked 122021 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu0.iew.lsq.thread.0.forwLoads 410783 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu0.iew.lsq.thread.0.ignoredResponses 10667 # Number of memory responses ignored because the instruction is squashed
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.iew.lsq.thread.0.memOrderViolation 38522 # Number of memory ordering violations
|
|
|
|
|
system.cpu0.iew.lsq.thread.0.rescheduledLoads 18606 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu0.iew.lsq.thread.0.squashedLoads 1239715 # Number of loads squashed
|
|
|
|
|
system.cpu0.iew.lsq.thread.0.squashedStores 419501 # Number of stores squashed
|
|
|
|
|
system.cpu0.iew.memOrderViolationEvents 38522 # Number of memory order violations
|
|
|
|
|
system.cpu0.iew.predictedNotTakenIncorrect 332064 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu0.iew.predictedTakenIncorrect 379789 # Number of branches that were predicted taken incorrectly
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu0.int_regfile_reads 66329266 # number of integer regfile reads
|
|
|
|
|
system.cpu0.int_regfile_writes 36276231 # number of integer regfile writes
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.ipc 0.416037 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu0.ipc_total 0.416037 # IPC: Total IPC of All Threads
|
2010-11-08 20:58:24 +01:00
|
|
|
system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 3762 0.01% 0.01% # Type of FU issued
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.iq.ISSUE:FU_type_0::IntAlu 35322205 69.50% 69.50% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.ISSUE:FU_type_0::IntMult 55712 0.11% 69.61% # Type of FU issued
|
2010-12-08 01:19:57 +01:00
|
|
|
system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 69.61% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 15323 0.03% 69.64% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 69.64% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 69.64% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 69.64% # Type of FU issued
|
2010-11-08 20:58:24 +01:00
|
|
|
system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 1880 0.00% 69.65% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 69.65% # Type of FU issued
|
2010-11-15 21:04:05 +01:00
|
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 69.65% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 69.65% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 69.65% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 69.65% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 69.65% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 69.65% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 69.65% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 69.65% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 69.65% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 69.65% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 69.65% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 69.65% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 69.65% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 69.65% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 69.65% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 69.65% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 69.65% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 69.65% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 69.65% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 69.65% # Type of FU issued
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.iq.ISSUE:FU_type_0::MemRead 9003021 17.71% 87.36% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.ISSUE:FU_type_0::MemWrite 5645656 11.11% 98.47% # Type of FU issued
|
|
|
|
|
system.cpu0.iq.ISSUE:FU_type_0::IprAccess 779190 1.53% 100.00% # Type of FU issued
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.iq.ISSUE:FU_type_0::total 50826749 # Type of FU issued
|
|
|
|
|
system.cpu0.iq.ISSUE:fu_busy_cnt 382289 # FU busy when requested
|
|
|
|
|
system.cpu0.iq.ISSUE:fu_busy_rate 0.007521 # FU busy rate (busy events/executed inst)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu0.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.iq.ISSUE:fu_full::IntAlu 40958 10.71% 10.71% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 10.71% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.71% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.71% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.71% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.71% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.71% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.71% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.71% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.ISSUE:fu_full::SimdAdd 0 0.00% 10.71% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 10.71% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.ISSUE:fu_full::SimdAlu 0 0.00% 10.71% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.ISSUE:fu_full::SimdCmp 0 0.00% 10.71% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.ISSUE:fu_full::SimdCvt 0 0.00% 10.71% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.ISSUE:fu_full::SimdMisc 0 0.00% 10.71% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.ISSUE:fu_full::SimdMult 0 0.00% 10.71% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 10.71% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.ISSUE:fu_full::SimdShift 0 0.00% 10.71% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 10.71% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 10.71% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 10.71% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 10.71% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 10.71% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 10.71% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 10.71% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 10.71% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 10.71% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 10.71% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 10.71% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.ISSUE:fu_full::MemRead 226307 59.20% 69.91% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.ISSUE:fu_full::MemWrite 115024 30.09% 100.00% # attempts to use FU when none available
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu0.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::samples 79523293 # Number of insts issued each cycle
|
|
|
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.639143 # Number of insts issued each cycle
|
|
|
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.209985 # Number of insts issued each cycle
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::0 54765331 68.87% 68.87% # Number of insts issued each cycle
|
|
|
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::1 12086611 15.20% 84.07% # Number of insts issued each cycle
|
|
|
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::2 5449422 6.85% 90.92% # Number of insts issued each cycle
|
|
|
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::3 3416951 4.30% 95.22% # Number of insts issued each cycle
|
|
|
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::4 2222762 2.80% 98.01% # Number of insts issued each cycle
|
|
|
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::5 992615 1.25% 99.26% # Number of insts issued each cycle
|
|
|
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::6 434574 0.55% 99.81% # Number of insts issued each cycle
|
|
|
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::7 111342 0.14% 99.95% # Number of insts issued each cycle
|
|
|
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::8 43685 0.05% 100.00% # Number of insts issued each cycle
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::total 79523293 # Number of insts issued each cycle
|
|
|
|
|
system.cpu0.iq.ISSUE:rate 0.450743 # Inst issue rate
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu0.iq.fp_alu_accesses 260476 # Number of floating point alu accesses
|
|
|
|
|
system.cpu0.iq.fp_inst_queue_reads 508189 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu0.iq.fp_inst_queue_wakeup_accesses 246844 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu0.iq.fp_inst_queue_writes 251997 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu0.iq.int_alu_accesses 50944800 # Number of integer alu accesses
|
|
|
|
|
system.cpu0.iq.int_inst_queue_reads 181074941 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu0.iq.int_inst_queue_wakeup_accesses 49741828 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu0.iq.int_inst_queue_writes 60494151 # Number of integer instruction queue writes
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.iq.iqInstsAdded 52250537 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu0.iq.iqInstsIssued 50826749 # Number of instructions issued
|
|
|
|
|
system.cpu0.iq.iqNonSpecInstsAdded 1722211 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu0.iq.iqSquashedInstsExamined 6740578 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu0.iq.iqSquashedInstsIssued 24052 # Number of squashed instructions issued
|
|
|
|
|
system.cpu0.iq.iqSquashedNonSpecRemoved 1157447 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu0.iq.iqSquashedOperandsExamined 3424469 # Number of squashed operands that are examined and possibly removed from graph
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu0.itb.data_accesses 0 # DTB accesses
|
|
|
|
|
system.cpu0.itb.data_acv 0 # DTB access violations
|
|
|
|
|
system.cpu0.itb.data_hits 0 # DTB hits
|
|
|
|
|
system.cpu0.itb.data_misses 0 # DTB misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.itb.fetch_accesses 951927 # ITB accesses
|
|
|
|
|
system.cpu0.itb.fetch_acv 732 # ITB acv
|
|
|
|
|
system.cpu0.itb.fetch_hits 922973 # ITB hits
|
|
|
|
|
system.cpu0.itb.fetch_misses 28954 # ITB misses
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu0.itb.read_acv 0 # DTB read access violations
|
|
|
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu0.itb.write_acv 0 # DTB write access violations
|
|
|
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu0.kern.callpal::wripir 351 0.22% 0.22% # number of callpals executed
|
|
|
|
|
system.cpu0.kern.callpal::wrmces 1 0.00% 0.22% # number of callpals executed
|
|
|
|
|
system.cpu0.kern.callpal::wrfen 1 0.00% 0.22% # number of callpals executed
|
|
|
|
|
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.22% # number of callpals executed
|
|
|
|
|
system.cpu0.kern.callpal::swpctx 3287 2.03% 2.25% # number of callpals executed
|
|
|
|
|
system.cpu0.kern.callpal::tbi 43 0.03% 2.27% # number of callpals executed
|
|
|
|
|
system.cpu0.kern.callpal::wrent 7 0.00% 2.28% # number of callpals executed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.kern.callpal::swpipl 147045 90.75% 93.03% # number of callpals executed
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu0.kern.callpal::rdps 6369 3.93% 96.96% # number of callpals executed
|
|
|
|
|
system.cpu0.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
|
|
|
|
|
system.cpu0.kern.callpal::wrusp 3 0.00% 96.96% # number of callpals executed
|
|
|
|
|
system.cpu0.kern.callpal::rdusp 7 0.00% 96.96% # number of callpals executed
|
|
|
|
|
system.cpu0.kern.callpal::whami 2 0.00% 96.96% # number of callpals executed
|
|
|
|
|
system.cpu0.kern.callpal::rti 4450 2.75% 99.71% # number of callpals executed
|
|
|
|
|
system.cpu0.kern.callpal::callsys 330 0.20% 99.91% # number of callpals executed
|
2010-09-09 20:40:19 +02:00
|
|
|
system.cpu0.kern.callpal::imb 138 0.09% 100.00% # number of callpals executed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.kern.callpal::total 162037 # number of callpals executed
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
2010-12-08 01:19:57 +01:00
|
|
|
system.cpu0.kern.inst.hwrei 176106 # number of hwrei instructions executed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.kern.inst.quiesce 6624 # number of quiesce instructions executed
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu0.kern.ipl_count::0 62137 40.37% 40.37% # number of times we switched to this ipl
|
|
|
|
|
system.cpu0.kern.ipl_count::21 238 0.15% 40.53% # number of times we switched to this ipl
|
|
|
|
|
system.cpu0.kern.ipl_count::22 1925 1.25% 41.78% # number of times we switched to this ipl
|
|
|
|
|
system.cpu0.kern.ipl_count::30 254 0.17% 41.94% # number of times we switched to this ipl
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.kern.ipl_count::31 89359 58.06% 100.00% # number of times we switched to this ipl
|
|
|
|
|
system.cpu0.kern.ipl_count::total 153913 # number of times we switched to this ipl
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu0.kern.ipl_good::0 61267 49.13% 49.13% # number of times we switched to this ipl from a different ipl
|
|
|
|
|
system.cpu0.kern.ipl_good::21 238 0.19% 49.32% # number of times we switched to this ipl from a different ipl
|
|
|
|
|
system.cpu0.kern.ipl_good::22 1925 1.54% 50.87% # number of times we switched to this ipl from a different ipl
|
|
|
|
|
system.cpu0.kern.ipl_good::30 254 0.20% 51.07% # number of times we switched to this ipl from a different ipl
|
|
|
|
|
system.cpu0.kern.ipl_good::31 61013 48.93% 100.00% # number of times we switched to this ipl from a different ipl
|
|
|
|
|
system.cpu0.kern.ipl_good::total 124697 # number of times we switched to this ipl from a different ipl
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.kern.ipl_ticks::0 1862706719500 97.99% 97.99% # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu0.kern.ipl_ticks::21 96293500 0.01% 98.00% # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu0.kern.ipl_ticks::22 398446500 0.02% 98.02% # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu0.kern.ipl_ticks::30 103381000 0.01% 98.03% # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu0.kern.ipl_ticks::31 37525343500 1.97% 100.00% # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu0.kern.ipl_ticks::total 1900830184000 # number of cycles we spent at this ipl
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu0.kern.ipl_used::0 0.985999 # fraction of swpipl calls that actually changed the ipl
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
|
|
|
|
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
|
|
|
|
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.kern.ipl_used::31 0.682785 # fraction of swpipl calls that actually changed the ipl
|
|
|
|
|
system.cpu0.kern.mode_good::kernel 1172
|
|
|
|
|
system.cpu0.kern.mode_good::user 1173
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu0.kern.mode_good::idle 0
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.kern.mode_switch::kernel 6890 # number of protection mode switches
|
|
|
|
|
system.cpu0.kern.mode_switch::user 1173 # number of protection mode switches
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.kern.mode_switch_good::kernel 0.170102 # fraction of useful protection mode switches
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
|
|
|
|
system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches
|
|
|
|
|
system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.kern.mode_ticks::kernel 1898860791500 99.90% 99.90% # number of ticks spent at the given mode
|
|
|
|
|
system.cpu0.kern.mode_ticks::user 1969384500 0.10% 100.00% # number of ticks spent at the given mode
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu0.kern.swap_context 3288 # number of times the context was actually changed
|
|
|
|
|
system.cpu0.kern.syscall::2 6 2.99% 2.99% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::3 17 8.46% 11.44% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::4 3 1.49% 12.94% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::6 27 13.43% 26.37% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::12 1 0.50% 26.87% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::17 9 4.48% 31.34% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::19 6 2.99% 34.33% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::20 4 1.99% 36.32% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::23 1 0.50% 36.82% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::24 3 1.49% 38.31% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::33 7 3.48% 41.79% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::41 2 1.00% 42.79% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::45 36 17.91% 60.70% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::47 3 1.49% 62.19% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::48 7 3.48% 65.67% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::54 9 4.48% 70.15% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::58 1 0.50% 70.65% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::59 5 2.49% 73.13% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::71 27 13.43% 86.57% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::73 3 1.49% 88.06% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::74 7 3.48% 91.54% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::87 1 0.50% 92.04% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::90 1 0.50% 92.54% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::92 7 3.48% 96.02% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::97 2 1.00% 97.01% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::98 2 1.00% 98.01% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::132 1 0.50% 98.51% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::144 1 0.50% 99.00% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::147 2 1.00% 100.00% # number of syscalls executed
|
|
|
|
|
system.cpu0.kern.syscall::total 201 # number of syscalls executed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.memDep0.conflictingLoads 2324520 # Number of conflicting loads.
|
|
|
|
|
system.cpu0.memDep0.conflictingStores 1920330 # Number of conflicting stores.
|
|
|
|
|
system.cpu0.memDep0.insertedLoads 9134564 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu0.memDep0.insertedStores 5843380 # Number of stores inserted to the mem dependence unit.
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu0.misc_regfile_reads 1626369 # number of misc regfile reads
|
|
|
|
|
system.cpu0.misc_regfile_writes 787165 # number of misc regfile writes
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.numCycles 112762027 # number of cpu cycles simulated
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
|
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.rename.RENAME:BlockCycles 12784616 # Number of cycles rename is blocking
|
|
|
|
|
system.cpu0.rename.RENAME:CommittedMaps 33979042 # Number of HB maps that are committed
|
|
|
|
|
system.cpu0.rename.RENAME:IQFullEvents 1006695 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu0.rename.RENAME:IdleCycles 33581656 # Number of cycles rename is idle
|
|
|
|
|
system.cpu0.rename.RENAME:LSQFullEvents 1371330 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu0.rename.RENAME:ROBFullEvents 43310 # Number of times rename has blocked due to ROB full
|
|
|
|
|
system.cpu0.rename.RENAME:RenameLookups 72537525 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu0.rename.RENAME:RenamedInsts 59326371 # Number of instructions processed by rename
|
|
|
|
|
system.cpu0.rename.RENAME:RenamedOperands 39979107 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu0.rename.RENAME:RunCycles 11035754 # Number of cycles rename is running
|
|
|
|
|
system.cpu0.rename.RENAME:SquashCycles 1271125 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu0.rename.RENAME:UnblockCycles 3987965 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu0.rename.RENAME:UndoneMaps 6000063 # Number of HB maps that are undone due to squashing
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu0.rename.RENAME:fp_rename_lookups 359001 # Number of floating rename lookups
|
|
|
|
|
system.cpu0.rename.RENAME:int_rename_lookups 72178524 # Number of integer rename lookups
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.rename.RENAME:serializeStallCycles 16862175 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu0.rename.RENAME:serializingInsts 1393641 # count of serializing insts renamed
|
|
|
|
|
system.cpu0.rename.RENAME:skidInsts 10087757 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu0.rename.RENAME:tempSerializingInsts 207582 # count of temporary serializing insts renamed
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu0.rob.rob_reads 134196739 # The number of ROB reads
|
|
|
|
|
system.cpu0.rob.rob_writes 115376344 # The number of ROB writes
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu0.timesIdled 1187239 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
2009-03-07 23:30:55 +01:00
|
|
|
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.BPredUnit.BTBHits 1159872 # Number of BTB hits
|
|
|
|
|
system.cpu1.BPredUnit.BTBLookups 2699541 # Number of BTB lookups
|
|
|
|
|
system.cpu1.BPredUnit.RASInCorrect 8252 # Number of incorrect RAS predictions.
|
|
|
|
|
system.cpu1.BPredUnit.condIncorrect 107435 # Number of conditional branches incorrect
|
|
|
|
|
system.cpu1.BPredUnit.condPredicted 2484356 # Number of conditional branches predicted
|
|
|
|
|
system.cpu1.BPredUnit.lookups 2997970 # Number of BP lookups
|
|
|
|
|
system.cpu1.BPredUnit.usedRAS 209804 # Number of times the RAS was used to get a target.
|
|
|
|
|
system.cpu1.commit.COM:branches 1520810 # Number of branches committed
|
|
|
|
|
system.cpu1.commit.COM:bw_lim_events 200192 # number cycles where commit BW limit reached
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.commit.COM:committed_per_cycle::samples 17838555 # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.COM:committed_per_cycle::mean 0.594502 # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.COM:committed_per_cycle::stdev 1.408069 # Number of insts commited each cycle
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu1.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.commit.COM:committed_per_cycle::0 13455309 75.43% 75.43% # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.COM:committed_per_cycle::1 2068240 11.59% 87.02% # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.COM:committed_per_cycle::2 796982 4.47% 91.49% # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.COM:committed_per_cycle::3 568404 3.19% 94.68% # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.COM:committed_per_cycle::4 398869 2.24% 96.91% # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.COM:committed_per_cycle::5 150882 0.85% 97.76% # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.COM:committed_per_cycle::6 111519 0.63% 98.38% # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.COM:committed_per_cycle::7 88158 0.49% 98.88% # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.COM:committed_per_cycle::8 200192 1.12% 100.00% # Number of insts commited each cycle
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu1.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.commit.COM:committed_per_cycle::total 17838555 # Number of insts commited each cycle
|
|
|
|
|
system.cpu1.commit.COM:count 10605058 # Number of instructions committed
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu1.commit.COM:fp_insts 116296 # Number of committed floating point instructions.
|
|
|
|
|
system.cpu1.commit.COM:function_calls 166623 # Number of function calls committed.
|
|
|
|
|
system.cpu1.commit.COM:int_insts 9814589 # Number of committed integer instructions.
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.commit.COM:loads 1991974 # Number of loads committed
|
|
|
|
|
system.cpu1.commit.COM:membars 52733 # Number of memory barriers committed
|
|
|
|
|
system.cpu1.commit.COM:refs 3376359 # Number of memory references committed
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.commit.branchMispredicts 164468 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu1.commit.commitCommittedInsts 10605058 # The number of committed instructions
|
|
|
|
|
system.cpu1.commit.commitNonSpecStalls 163004 # The number of times commit has been forced to stall to communicate backwards
|
|
|
|
|
system.cpu1.commit.commitSquashedInsts 1721791 # The number of squashed insts skipped by commit
|
|
|
|
|
system.cpu1.committedInsts 10077586 # Number of Instructions Simulated
|
|
|
|
|
system.cpu1.committedInsts_total 10077586 # Number of Instructions Simulated
|
|
|
|
|
system.cpu1.cpi 1.948890 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu1.cpi_total 1.948890 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_accesses::0 46378 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_accesses::total 46378 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11069.539376 # average LoadLockedReq miss latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 7993.965806 # average LoadLockedReq mshr miss latency
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_hits::0 39648 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_hits::total 39648 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency 74498000 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.145112 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_misses::0 6730 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_misses::total 6730 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_mshr_hits 764 # number of LoadLockedReq MSHR hits
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 47692000 # number of LoadLockedReq MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.128639 # mshr miss rate for LoadLockedReq accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses 5966 # number of LoadLockedReq MSHR misses
|
|
|
|
|
system.cpu1.dcache.ReadReq_accesses::0 2062902 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.ReadReq_accesses::total 2062902 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::0 15016.821540 # average ReadReq miss latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
|
|
|
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11679.389313 # average ReadReq mshr miss latency
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.dcache.ReadReq_hits::0 1868657 # number of ReadReq hits
|
|
|
|
|
system.cpu1.dcache.ReadReq_hits::total 1868657 # number of ReadReq hits
|
|
|
|
|
system.cpu1.dcache.ReadReq_miss_latency 2916942500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu1.dcache.ReadReq_miss_rate::0 0.094161 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.dcache.ReadReq_misses::0 194245 # number of ReadReq misses
|
|
|
|
|
system.cpu1.dcache.ReadReq_misses::total 194245 # number of ReadReq misses
|
|
|
|
|
system.cpu1.dcache.ReadReq_mshr_hits 99139 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency 1110780000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.046103 # mshr miss rate for ReadReq accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.dcache.ReadReq_mshr_misses 95106 # number of ReadReq MSHR misses
|
2010-12-08 01:19:57 +01:00
|
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 17677500 # number of ReadReq MSHR uncacheable cycles
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.dcache.StoreCondReq_accesses::0 43196 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_accesses::total 43196 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 13130.603783 # average StoreCondReq miss latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 10135.856884 # average StoreCondReq mshr miss latency
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_hits::0 39337 # number of StoreCondReq hits
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_hits::total 39337 # number of StoreCondReq hits
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_miss_latency 50671000 # number of StoreCondReq miss cycles
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::0 0.089337 # miss rate for StoreCondReq accesses
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_misses::0 3859 # number of StoreCondReq misses
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_misses::total 3859 # number of StoreCondReq misses
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency 39094000 # number of StoreCondReq MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.089291 # mshr miss rate for StoreCondReq accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses 3857 # number of StoreCondReq MSHR misses
|
|
|
|
|
system.cpu1.dcache.WriteReq_accesses::0 1334800 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.WriteReq_accesses::total 1334800 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::0 21227.985433 # average WriteReq miss latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
|
|
|
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 18769.279348 # average WriteReq mshr miss latency
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.dcache.WriteReq_hits::0 1085325 # number of WriteReq hits
|
|
|
|
|
system.cpu1.dcache.WriteReq_hits::total 1085325 # number of WriteReq hits
|
|
|
|
|
system.cpu1.dcache.WriteReq_miss_latency 5295851666 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu1.dcache.WriteReq_miss_rate::0 0.186901 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu1.dcache.WriteReq_misses::0 249475 # number of WriteReq misses
|
|
|
|
|
system.cpu1.dcache.WriteReq_misses::total 249475 # number of WriteReq misses
|
|
|
|
|
system.cpu1.dcache.WriteReq_mshr_hits 201005 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency 909746970 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.036313 # mshr miss rate for WriteReq accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.dcache.WriteReq_mshr_misses 48470 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 377654500 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9972.984645 # average number of cycles each access was blocked
|
2010-08-23 18:18:42 +02:00
|
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.dcache.avg_refs 22.879556 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu1.dcache.blocked::no_mshrs 5275 # number of cycles access was blocked
|
2010-08-23 18:18:42 +02:00
|
|
|
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 52607494 # number of cycles access was blocked
|
2010-08-23 18:18:42 +02:00
|
|
|
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.dcache.demand_accesses::0 3397702 # number of demand (read+write) accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.dcache.demand_accesses::total 3397702 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu1.dcache.demand_avg_miss_latency::0 18508.956473 # average overall miss latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
|
|
|
|
|
system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency 14072.874088 # average overall mshr miss latency
|
|
|
|
|
system.cpu1.dcache.demand_hits::0 2953982 # number of demand (read+write) hits
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.dcache.demand_hits::total 2953982 # number of demand (read+write) hits
|
|
|
|
|
system.cpu1.dcache.demand_miss_latency 8212794166 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu1.dcache.demand_miss_rate::0 0.130594 # miss rate for demand accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
|
|
|
|
system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.dcache.demand_misses::0 443720 # number of demand (read+write) misses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.dcache.demand_misses::total 443720 # number of demand (read+write) misses
|
|
|
|
|
system.cpu1.dcache.demand_mshr_hits 300144 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu1.dcache.demand_mshr_miss_latency 2020526970 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.demand_mshr_miss_rate::0 0.042257 # mshr miss rate for demand accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.dcache.demand_mshr_misses 143576 # number of demand (read+write) MSHR misses
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.dcache.occ_%::0 0.933238 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu1.dcache.occ_blocks::0 477.817937 # Average occupied blocks per context
|
|
|
|
|
system.cpu1.dcache.overall_accesses::0 3397702 # number of overall (read+write) accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.dcache.overall_accesses::total 3397702 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu1.dcache.overall_avg_miss_latency::0 18508.956473 # average overall miss latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
|
|
|
|
|
system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency 14072.874088 # average overall mshr miss latency
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.dcache.overall_hits::0 2953982 # number of overall hits
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu1.dcache.overall_hits::1 0 # number of overall hits
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.dcache.overall_hits::total 2953982 # number of overall hits
|
|
|
|
|
system.cpu1.dcache.overall_miss_latency 8212794166 # number of overall miss cycles
|
|
|
|
|
system.cpu1.dcache.overall_miss_rate::0 0.130594 # miss rate for overall accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
|
|
|
system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.dcache.overall_misses::0 443720 # number of overall misses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu1.dcache.overall_misses::1 0 # number of overall misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.dcache.overall_misses::total 443720 # number of overall misses
|
|
|
|
|
system.cpu1.dcache.overall_mshr_hits 300144 # number of overall MSHR hits
|
|
|
|
|
system.cpu1.dcache.overall_mshr_miss_latency 2020526970 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu1.dcache.overall_mshr_miss_rate::0 0.042257 # mshr miss rate for overall accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.dcache.overall_mshr_misses 143576 # number of overall MSHR misses
|
|
|
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency 395332000 # number of overall MSHR uncacheable cycles
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.dcache.replacements 132522 # number of replacements
|
|
|
|
|
system.cpu1.dcache.sampled_refs 132916 # Sample count of references to valid blocks.
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.dcache.tagsinuse 477.817937 # Cycle average of tags in use
|
|
|
|
|
system.cpu1.dcache.total_refs 3041059 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu1.dcache.warmup_cycle 1877659429000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu1.dcache.writebacks 88703 # number of writebacks
|
|
|
|
|
system.cpu1.decode.DECODE:BlockedCycles 6965197 # Number of cycles decode is blocked
|
|
|
|
|
system.cpu1.decode.DECODE:BranchMispred 7952 # Number of times decode detected a branch misprediction
|
|
|
|
|
system.cpu1.decode.DECODE:BranchResolved 127936 # Number of times decode resolved a branch
|
|
|
|
|
system.cpu1.decode.DECODE:DecodedInsts 13953075 # Number of instructions handled by decode
|
|
|
|
|
system.cpu1.decode.DECODE:IdleCycles 8268454 # Number of cycles decode is idle
|
|
|
|
|
system.cpu1.decode.DECODE:RunCycles 2505615 # Number of cycles decode is running
|
|
|
|
|
system.cpu1.decode.DECODE:SquashCycles 305805 # Number of cycles decode is squashing
|
|
|
|
|
system.cpu1.decode.DECODE:SquashedInsts 23745 # Number of squashed instructions handled by decode
|
|
|
|
|
system.cpu1.decode.DECODE:UnblockCycles 99288 # Number of cycles decode is unblocking
|
|
|
|
|
system.cpu1.dtb.data_accesses 453627 # DTB accesses
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu1.dtb.data_acv 183 # DTB access violations
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.dtb.data_hits 3614601 # DTB hits
|
|
|
|
|
system.cpu1.dtb.data_misses 12965 # DTB misses
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
|
|
|
|
|
system.cpu1.dtb.fetch_acv 0 # ITB acv
|
|
|
|
|
system.cpu1.dtb.fetch_hits 0 # ITB hits
|
|
|
|
|
system.cpu1.dtb.fetch_misses 0 # ITB misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.dtb.read_accesses 321686 # DTB read accesses
|
|
|
|
|
system.cpu1.dtb.read_acv 80 # DTB read access violations
|
|
|
|
|
system.cpu1.dtb.read_hits 2187439 # DTB read hits
|
|
|
|
|
system.cpu1.dtb.read_misses 10558 # DTB read misses
|
|
|
|
|
system.cpu1.dtb.write_accesses 131941 # DTB write accesses
|
|
|
|
|
system.cpu1.dtb.write_acv 103 # DTB write access violations
|
|
|
|
|
system.cpu1.dtb.write_hits 1427162 # DTB write hits
|
|
|
|
|
system.cpu1.dtb.write_misses 2407 # DTB write misses
|
|
|
|
|
system.cpu1.fetch.Branches 2997970 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu1.fetch.CacheLines 1676515 # Number of cache lines fetched
|
|
|
|
|
system.cpu1.fetch.Cycles 2637646 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu1.fetch.IcacheSquashes 103832 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu1.fetch.Insts 14205200 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu1.fetch.MiscStallCycles 9114 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
|
|
|
system.cpu1.fetch.SquashCycles 191574 # Number of cycles fetch has spent squashing
|
|
|
|
|
system.cpu1.fetch.branchRate 0.152645 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu1.fetch.icacheStallCycles 1676514 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu1.fetch.predictedBranches 1369676 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu1.fetch.rate 0.723275 # Number of inst fetches per cycle
|
|
|
|
|
system.cpu1.fetch.rateDist::samples 18144360 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.rateDist::mean 0.782899 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.rateDist::stdev 2.130950 # Number of instructions fetched each cycle (Total)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.fetch.rateDist::0 15506714 85.46% 85.46% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.rateDist::1 209351 1.15% 86.62% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.rateDist::2 321604 1.77% 88.39% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.rateDist::3 202250 1.11% 89.50% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.rateDist::4 379744 2.09% 91.60% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.rateDist::5 126923 0.70% 92.30% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.rateDist::6 169833 0.94% 93.23% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.rateDist::7 250226 1.38% 94.61% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.rateDist::8 977715 5.39% 100.00% # Number of instructions fetched each cycle (Total)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.fetch.rateDist::total 18144360 # Number of instructions fetched each cycle (Total)
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu1.fp_regfile_reads 63103 # number of floating regfile reads
|
|
|
|
|
system.cpu1.fp_regfile_writes 63156 # number of floating regfile writes
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.icache.ReadReq_accesses::0 1676515 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.icache.ReadReq_accesses::total 1676515 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::0 14673.731413 # average ReadReq miss latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
|
|
|
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11628.822702 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu1.icache.ReadReq_hits::0 1412481 # number of ReadReq hits
|
|
|
|
|
system.cpu1.icache.ReadReq_hits::total 1412481 # number of ReadReq hits
|
|
|
|
|
system.cpu1.icache.ReadReq_miss_latency 3874364000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu1.icache.ReadReq_miss_rate::0 0.157490 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.icache.ReadReq_misses::0 264034 # number of ReadReq misses
|
|
|
|
|
system.cpu1.icache.ReadReq_misses::total 264034 # number of ReadReq misses
|
|
|
|
|
system.cpu1.icache.ReadReq_mshr_hits 8194 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency 2975118000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.152602 # mshr miss rate for ReadReq accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.icache.ReadReq_mshr_misses 255840 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs 5000 # average number of cycles each access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.icache.avg_refs 5.522142 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu1.icache.blocked::no_mshrs 8 # number of cycles access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2010-11-08 20:58:24 +01:00
|
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 40000 # number of cycles access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.icache.demand_accesses::0 1676515 # number of demand (read+write) accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.icache.demand_accesses::total 1676515 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu1.icache.demand_avg_miss_latency::0 14673.731413 # average overall miss latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency
|
|
|
|
|
system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency 11628.822702 # average overall mshr miss latency
|
|
|
|
|
system.cpu1.icache.demand_hits::0 1412481 # number of demand (read+write) hits
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.icache.demand_hits::total 1412481 # number of demand (read+write) hits
|
|
|
|
|
system.cpu1.icache.demand_miss_latency 3874364000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu1.icache.demand_miss_rate::0 0.157490 # miss rate for demand accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
|
|
|
|
system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.icache.demand_misses::0 264034 # number of demand (read+write) misses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.icache.demand_misses::total 264034 # number of demand (read+write) misses
|
|
|
|
|
system.cpu1.icache.demand_mshr_hits 8194 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu1.icache.demand_mshr_miss_latency 2975118000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu1.icache.demand_mshr_miss_rate::0 0.152602 # mshr miss rate for demand accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.icache.demand_mshr_misses 255840 # number of demand (read+write) MSHR misses
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.icache.occ_%::0 0.900434 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu1.icache.occ_blocks::0 461.022394 # Average occupied blocks per context
|
|
|
|
|
system.cpu1.icache.overall_accesses::0 1676515 # number of overall (read+write) accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.icache.overall_accesses::total 1676515 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu1.icache.overall_avg_miss_latency::0 14673.731413 # average overall miss latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency
|
|
|
|
|
system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency 11628.822702 # average overall mshr miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.icache.overall_hits::0 1412481 # number of overall hits
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu1.icache.overall_hits::1 0 # number of overall hits
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.icache.overall_hits::total 1412481 # number of overall hits
|
|
|
|
|
system.cpu1.icache.overall_miss_latency 3874364000 # number of overall miss cycles
|
|
|
|
|
system.cpu1.icache.overall_miss_rate::0 0.157490 # miss rate for overall accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
|
|
|
system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.icache.overall_misses::0 264034 # number of overall misses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu1.icache.overall_misses::1 0 # number of overall misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.icache.overall_misses::total 264034 # number of overall misses
|
|
|
|
|
system.cpu1.icache.overall_mshr_hits 8194 # number of overall MSHR hits
|
|
|
|
|
system.cpu1.icache.overall_mshr_miss_latency 2975118000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu1.icache.overall_mshr_miss_rate::0 0.152602 # mshr miss rate for overall accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.icache.overall_mshr_misses 255840 # number of overall MSHR misses
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.icache.replacements 255273 # number of replacements
|
|
|
|
|
system.cpu1.icache.sampled_refs 255785 # Sample count of references to valid blocks.
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.icache.tagsinuse 461.022394 # Cycle average of tags in use
|
|
|
|
|
system.cpu1.icache.total_refs 1412481 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu1.icache.warmup_cycle 1897915849000 # Cycle when the warmup percentage was hit.
|
2010-11-08 20:58:24 +01:00
|
|
|
system.cpu1.icache.writebacks 13 # number of writebacks
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.idleCycles 1495744 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu1.iew.EXEC:branches 1630347 # Number of branches executed
|
|
|
|
|
system.cpu1.iew.EXEC:nop 601729 # number of nop insts executed
|
|
|
|
|
system.cpu1.iew.EXEC:rate 0.552052 # Inst execution rate
|
|
|
|
|
system.cpu1.iew.EXEC:refs 3644132 # number of memory reference insts executed
|
|
|
|
|
system.cpu1.iew.EXEC:stores 1436628 # Number of stores executed
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu1.iew.EXEC:swp 0 # number of swp insts executed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.iew.WB:consumers 6274106 # num instructions consuming a value
|
|
|
|
|
system.cpu1.iew.WB:count 10735003 # cumulative count of insts written-back
|
|
|
|
|
system.cpu1.iew.WB:fanout 0.735138 # average fanout of values written-back
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.iew.WB:producers 4612335 # num instructions producing a value
|
|
|
|
|
system.cpu1.iew.WB:rate 0.546586 # insts written-back per cycle
|
|
|
|
|
system.cpu1.iew.WB:sent 10758148 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu1.iew.branchMispredicts 178810 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu1.iew.iewBlockCycles 256636 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu1.iew.iewDispLoadInsts 2309588 # Number of dispatched load instructions
|
|
|
|
|
system.cpu1.iew.iewDispNonSpecInsts 500342 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu1.iew.iewDispSquashedInsts 209309 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu1.iew.iewDispStoreInsts 1512714 # Number of dispatched store instructions
|
|
|
|
|
system.cpu1.iew.iewDispatchedInsts 12409933 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu1.iew.iewExecLoadInsts 2207504 # Number of load instructions executed
|
|
|
|
|
system.cpu1.iew.iewExecSquashedInsts 107468 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu1.iew.iewExecutedInsts 10842361 # Number of executed instructions
|
|
|
|
|
system.cpu1.iew.iewIQFullEvents 2486 # Number of times the IQ has become full, causing a stall
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.iew.iewLSQFullEvents 4828 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu1.iew.iewSquashCycles 305805 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu1.iew.iewUnblockCycles 10156 # Number of cycles IEW is unblocking
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.iew.lsq.thread.0.cacheBlocked 22318 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu1.iew.lsq.thread.0.forwLoads 68189 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu1.iew.lsq.thread.0.ignoredResponses 2236 # Number of memory responses ignored because the instruction is squashed
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.iew.lsq.thread.0.memOrderViolation 10653 # Number of memory ordering violations
|
2010-11-08 20:58:24 +01:00
|
|
|
system.cpu1.iew.lsq.thread.0.rescheduledLoads 380 # Number of loads that were rescheduled
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.iew.lsq.thread.0.squashedLoads 317614 # Number of loads squashed
|
|
|
|
|
system.cpu1.iew.lsq.thread.0.squashedStores 128329 # Number of stores squashed
|
|
|
|
|
system.cpu1.iew.memOrderViolationEvents 10653 # Number of memory order violations
|
|
|
|
|
system.cpu1.iew.predictedNotTakenIncorrect 104816 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu1.iew.predictedTakenIncorrect 73994 # Number of branches that were predicted taken incorrectly
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu1.int_regfile_reads 13933756 # number of integer regfile reads
|
|
|
|
|
system.cpu1.int_regfile_writes 7611585 # number of integer regfile writes
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.ipc 0.513113 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu1.ipc_total 0.513113 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 3524 0.03% 0.03% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.ISSUE:FU_type_0::IntAlu 6870860 62.75% 62.78% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.ISSUE:FU_type_0::IntMult 18138 0.17% 62.95% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.95% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 11432 0.10% 63.05% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 63.05% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 63.05% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 63.05% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 1762 0.02% 63.07% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 63.07% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 63.07% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 63.07% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 63.07% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 63.07% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 63.07% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 63.07% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 63.07% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 63.07% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 63.07% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 63.07% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 63.07% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 63.07% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 63.07% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 63.07% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 63.07% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 63.07% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 63.07% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 63.07% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 63.07% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 63.07% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.ISSUE:FU_type_0::MemRead 2282503 20.85% 83.91% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.ISSUE:FU_type_0::MemWrite 1453754 13.28% 97.19% # Type of FU issued
|
|
|
|
|
system.cpu1.iq.ISSUE:FU_type_0::IprAccess 307856 2.81% 100.00% # Type of FU issued
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.iq.ISSUE:FU_type_0::total 10949829 # Type of FU issued
|
|
|
|
|
system.cpu1.iq.ISSUE:fu_busy_cnt 154910 # FU busy when requested
|
|
|
|
|
system.cpu1.iq.ISSUE:fu_busy_rate 0.014147 # FU busy rate (busy events/executed inst)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu1.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.iq.ISSUE:fu_full::IntAlu 4092 2.64% 2.64% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 2.64% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.64% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.64% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.64% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.64% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.64% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.64% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.64% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.64% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.64% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.64% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.64% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.64% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.64% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.64% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.64% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.64% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.64% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.64% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.64% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.64% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.64% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.64% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.64% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.64% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.64% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.64% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.64% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.ISSUE:fu_full::MemRead 90881 58.67% 61.31% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.ISSUE:fu_full::MemWrite 59937 38.69% 100.00% # attempts to use FU when none available
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu1.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::samples 18144360 # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.603484 # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.209438 # Number of insts issued each cycle
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::0 12920190 71.21% 71.21% # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::1 2565455 14.14% 85.35% # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::2 1066502 5.88% 91.22% # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::3 689185 3.80% 95.02% # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::4 526783 2.90% 97.93% # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::5 236336 1.30% 99.23% # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::6 93675 0.52% 99.75% # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::7 36919 0.20% 99.95% # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::8 9315 0.05% 100.00% # Number of insts issued each cycle
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::total 18144360 # Number of insts issued each cycle
|
|
|
|
|
system.cpu1.iq.ISSUE:rate 0.557524 # Inst issue rate
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu1.iq.fp_alu_accesses 125165 # Number of floating point alu accesses
|
|
|
|
|
system.cpu1.iq.fp_inst_queue_reads 243017 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu1.iq.fp_inst_queue_wakeup_accesses 117535 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu1.iq.fp_inst_queue_writes 119622 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu1.iq.int_alu_accesses 10976050 # Number of integer alu accesses
|
|
|
|
|
system.cpu1.iq.int_inst_queue_reads 39966063 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu1.iq.int_inst_queue_wakeup_accesses 10617468 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu1.iq.int_inst_queue_writes 13352810 # Number of integer instruction queue writes
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.iq.iqInstsAdded 11252421 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu1.iq.iqInstsIssued 10949829 # Number of instructions issued
|
|
|
|
|
system.cpu1.iq.iqNonSpecInstsAdded 555783 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu1.iq.iqSquashedInstsExamined 1655590 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu1.iq.iqSquashedInstsIssued 10152 # Number of squashed instructions issued
|
|
|
|
|
system.cpu1.iq.iqSquashedNonSpecRemoved 392779 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu1.iq.iqSquashedOperandsExamined 854299 # Number of squashed operands that are examined and possibly removed from graph
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu1.itb.data_accesses 0 # DTB accesses
|
|
|
|
|
system.cpu1.itb.data_acv 0 # DTB access violations
|
|
|
|
|
system.cpu1.itb.data_hits 0 # DTB hits
|
|
|
|
|
system.cpu1.itb.data_misses 0 # DTB misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.itb.fetch_accesses 448461 # ITB accesses
|
|
|
|
|
system.cpu1.itb.fetch_acv 279 # ITB acv
|
|
|
|
|
system.cpu1.itb.fetch_hits 439821 # ITB hits
|
|
|
|
|
system.cpu1.itb.fetch_misses 8640 # ITB misses
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu1.itb.read_acv 0 # DTB read access violations
|
|
|
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu1.itb.write_acv 0 # DTB write access violations
|
|
|
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
2010-11-08 20:58:24 +01:00
|
|
|
system.cpu1.kern.callpal::wripir 254 0.45% 0.45% # number of callpals executed
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu1.kern.callpal::wrmces 1 0.00% 0.45% # number of callpals executed
|
|
|
|
|
system.cpu1.kern.callpal::wrfen 1 0.00% 0.45% # number of callpals executed
|
|
|
|
|
system.cpu1.kern.callpal::swpctx 1450 2.54% 2.99% # number of callpals executed
|
|
|
|
|
system.cpu1.kern.callpal::tbi 12 0.02% 3.01% # number of callpals executed
|
2010-09-09 20:40:19 +02:00
|
|
|
system.cpu1.kern.callpal::wrent 7 0.01% 3.02% # number of callpals executed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.kern.callpal::swpipl 49364 86.50% 89.53% # number of callpals executed
|
2010-11-08 20:58:24 +01:00
|
|
|
system.cpu1.kern.callpal::rdps 2383 4.18% 93.70% # number of callpals executed
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu1.kern.callpal::wrkgp 1 0.00% 93.71% # number of callpals executed
|
|
|
|
|
system.cpu1.kern.callpal::wrusp 4 0.01% 93.71% # number of callpals executed
|
|
|
|
|
system.cpu1.kern.callpal::rdusp 2 0.00% 93.72% # number of callpals executed
|
|
|
|
|
system.cpu1.kern.callpal::whami 3 0.01% 93.72% # number of callpals executed
|
|
|
|
|
system.cpu1.kern.callpal::rti 3352 5.87% 99.60% # number of callpals executed
|
|
|
|
|
system.cpu1.kern.callpal::callsys 187 0.33% 99.92% # number of callpals executed
|
|
|
|
|
system.cpu1.kern.callpal::imb 43 0.08% 100.00% # number of callpals executed
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.kern.callpal::total 57066 # number of callpals executed
|
2008-10-21 01:00:07 +02:00
|
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.kern.inst.hwrei 64904 # number of hwrei instructions executed
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu1.kern.inst.quiesce 2510 # number of quiesce instructions executed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.kern.ipl_count::0 20664 37.58% 37.58% # number of times we switched to this ipl
|
|
|
|
|
system.cpu1.kern.ipl_count::22 1922 3.50% 41.07% # number of times we switched to this ipl
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu1.kern.ipl_count::30 351 0.64% 41.71% # number of times we switched to this ipl
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.kern.ipl_count::31 32053 58.29% 100.00% # number of times we switched to this ipl
|
|
|
|
|
system.cpu1.kern.ipl_count::total 54990 # number of times we switched to this ipl
|
|
|
|
|
system.cpu1.kern.ipl_good::0 20157 47.72% 47.72% # number of times we switched to this ipl from a different ipl
|
2010-11-08 20:58:24 +01:00
|
|
|
system.cpu1.kern.ipl_good::22 1922 4.55% 52.28% # number of times we switched to this ipl from a different ipl
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu1.kern.ipl_good::30 351 0.83% 53.11% # number of times we switched to this ipl from a different ipl
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.kern.ipl_good::31 19806 46.89% 100.00% # number of times we switched to this ipl from a different ipl
|
|
|
|
|
system.cpu1.kern.ipl_good::total 42236 # number of times we switched to this ipl from a different ipl
|
|
|
|
|
system.cpu1.kern.ipl_ticks::0 1870770703000 98.44% 98.44% # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu1.kern.ipl_ticks::22 347961500 0.02% 98.46% # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu1.kern.ipl_ticks::30 137588500 0.01% 98.46% # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu1.kern.ipl_ticks::31 29223568000 1.54% 100.00% # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu1.kern.ipl_ticks::total 1900479821000 # number of cycles we spent at this ipl
|
|
|
|
|
system.cpu1.kern.ipl_used::0 0.975465 # fraction of swpipl calls that actually changed the ipl
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
|
|
|
|
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.kern.ipl_used::31 0.617914 # fraction of swpipl calls that actually changed the ipl
|
|
|
|
|
system.cpu1.kern.mode_good::kernel 849
|
|
|
|
|
system.cpu1.kern.mode_good::user 573
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu1.kern.mode_good::idle 276
|
2010-11-08 20:58:24 +01:00
|
|
|
system.cpu1.kern.mode_switch::kernel 1766 # number of protection mode switches
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.kern.mode_switch::user 573 # number of protection mode switches
|
|
|
|
|
system.cpu1.kern.mode_switch::idle 2541 # number of protection mode switches
|
|
|
|
|
system.cpu1.kern.mode_switch_good::kernel 0.480747 # fraction of useful protection mode switches
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.kern.mode_switch_good::idle 0.108619 # fraction of useful protection mode switches
|
|
|
|
|
system.cpu1.kern.mode_switch_good::total 1.589366 # fraction of useful protection mode switches
|
|
|
|
|
system.cpu1.kern.mode_ticks::kernel 6317362000 0.33% 0.33% # number of ticks spent at the given mode
|
|
|
|
|
system.cpu1.kern.mode_ticks::user 1020701000 0.05% 0.39% # number of ticks spent at the given mode
|
|
|
|
|
system.cpu1.kern.mode_ticks::idle 1893129288000 99.61% 100.00% # number of ticks spent at the given mode
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu1.kern.swap_context 1451 # number of times the context was actually changed
|
|
|
|
|
system.cpu1.kern.syscall::2 2 1.60% 1.60% # number of syscalls executed
|
|
|
|
|
system.cpu1.kern.syscall::3 13 10.40% 12.00% # number of syscalls executed
|
|
|
|
|
system.cpu1.kern.syscall::4 1 0.80% 12.80% # number of syscalls executed
|
|
|
|
|
system.cpu1.kern.syscall::6 15 12.00% 24.80% # number of syscalls executed
|
|
|
|
|
system.cpu1.kern.syscall::15 1 0.80% 25.60% # number of syscalls executed
|
|
|
|
|
system.cpu1.kern.syscall::17 6 4.80% 30.40% # number of syscalls executed
|
|
|
|
|
system.cpu1.kern.syscall::19 4 3.20% 33.60% # number of syscalls executed
|
|
|
|
|
system.cpu1.kern.syscall::20 2 1.60% 35.20% # number of syscalls executed
|
|
|
|
|
system.cpu1.kern.syscall::23 3 2.40% 37.60% # number of syscalls executed
|
|
|
|
|
system.cpu1.kern.syscall::24 3 2.40% 40.00% # number of syscalls executed
|
|
|
|
|
system.cpu1.kern.syscall::33 4 3.20% 43.20% # number of syscalls executed
|
|
|
|
|
system.cpu1.kern.syscall::45 18 14.40% 57.60% # number of syscalls executed
|
|
|
|
|
system.cpu1.kern.syscall::47 3 2.40% 60.00% # number of syscalls executed
|
|
|
|
|
system.cpu1.kern.syscall::48 3 2.40% 62.40% # number of syscalls executed
|
|
|
|
|
system.cpu1.kern.syscall::54 1 0.80% 63.20% # number of syscalls executed
|
|
|
|
|
system.cpu1.kern.syscall::59 2 1.60% 64.80% # number of syscalls executed
|
|
|
|
|
system.cpu1.kern.syscall::71 27 21.60% 86.40% # number of syscalls executed
|
|
|
|
|
system.cpu1.kern.syscall::74 9 7.20% 93.60% # number of syscalls executed
|
|
|
|
|
system.cpu1.kern.syscall::90 2 1.60% 95.20% # number of syscalls executed
|
|
|
|
|
system.cpu1.kern.syscall::92 2 1.60% 96.80% # number of syscalls executed
|
|
|
|
|
system.cpu1.kern.syscall::132 3 2.40% 99.20% # number of syscalls executed
|
|
|
|
|
system.cpu1.kern.syscall::144 1 0.80% 100.00% # number of syscalls executed
|
|
|
|
|
system.cpu1.kern.syscall::total 125 # number of syscalls executed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.memDep0.conflictingLoads 496033 # Number of conflicting loads.
|
|
|
|
|
system.cpu1.memDep0.conflictingStores 413880 # Number of conflicting stores.
|
|
|
|
|
system.cpu1.memDep0.insertedLoads 2309588 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu1.memDep0.insertedStores 1512714 # Number of stores inserted to the mem dependence unit.
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu1.misc_regfile_reads 594436 # number of misc regfile reads
|
|
|
|
|
system.cpu1.misc_regfile_writes 255211 # number of misc regfile writes
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.numCycles 19640104 # number of cpu cycles simulated
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
|
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.rename.RENAME:BlockCycles 522822 # Number of cycles rename is blocking
|
|
|
|
|
system.cpu1.rename.RENAME:CommittedMaps 7159583 # Number of HB maps that are committed
|
|
|
|
|
system.cpu1.rename.RENAME:IQFullEvents 32718 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu1.rename.RENAME:IdleCycles 8500925 # Number of cycles rename is idle
|
|
|
|
|
system.cpu1.rename.RENAME:LSQFullEvents 256778 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu1.rename.RENAME:ROBFullEvents 15506 # Number of times rename has blocked due to ROB full
|
|
|
|
|
system.cpu1.rename.RENAME:RenameLookups 15473473 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu1.rename.RENAME:RenamedInsts 12930857 # Number of instructions processed by rename
|
|
|
|
|
system.cpu1.rename.RENAME:RenamedOperands 8489204 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu1.rename.RENAME:RunCycles 2359874 # Number of cycles rename is running
|
|
|
|
|
system.cpu1.rename.RENAME:SquashCycles 305805 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu1.rename.RENAME:UnblockCycles 801183 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu1.rename.RENAME:UndoneMaps 1329621 # Number of HB maps that are undone due to squashing
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu1.rename.RENAME:fp_rename_lookups 171444 # Number of floating rename lookups
|
|
|
|
|
system.cpu1.rename.RENAME:int_rename_lookups 15302029 # Number of integer rename lookups
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.rename.RENAME:serializeStallCycles 5653749 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu1.rename.RENAME:serializingInsts 515468 # count of serializing insts renamed
|
|
|
|
|
system.cpu1.rename.RENAME:skidInsts 2303190 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu1.rename.RENAME:tempSerializingInsts 52722 # count of temporary serializing insts renamed
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu1.rob.rob_reads 29861070 # The number of ROB reads
|
|
|
|
|
system.cpu1.rob.rob_writes 24957765 # The number of ROB writes
|
2011-01-18 23:30:06 +01:00
|
|
|
system.cpu1.timesIdled 194766 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
2008-10-21 01:00:07 +02:00
|
|
|
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
|
|
|
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
|
|
|
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
|
|
|
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
|
|
|
|
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
|
|
|
|
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
|
|
|
|
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
|
|
|
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
|
|
|
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
|
|
|
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
|
|
|
|
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
|
|
|
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
2010-09-09 20:40:19 +02:00
|
|
|
system.iocache.ReadReq_accesses::1 172 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.iocache.ReadReq_accesses::total 172 # number of ReadReq accesses(hits+misses)
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.iocache.ReadReq_avg_miss_latency::1 115267.430233 # average ReadReq miss latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.iocache.ReadReq_avg_mshr_miss_latency 63267.430233 # average ReadReq mshr miss latency
|
|
|
|
|
system.iocache.ReadReq_miss_latency 19825998 # number of ReadReq miss cycles
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses
|
2010-09-09 20:40:19 +02:00
|
|
|
system.iocache.ReadReq_misses::1 172 # number of ReadReq misses
|
|
|
|
|
system.iocache.ReadReq_misses::total 172 # number of ReadReq misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.iocache.ReadReq_mshr_miss_latency 10881998 # number of ReadReq MSHR miss cycles
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
2010-09-09 20:40:19 +02:00
|
|
|
system.iocache.ReadReq_mshr_misses 172 # number of ReadReq MSHR misses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.iocache.WriteReq_avg_miss_latency::1 137704.871149 # average WriteReq miss latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.iocache.WriteReq_avg_mshr_miss_latency 85701.289902 # average WriteReq mshr miss latency
|
|
|
|
|
system.iocache.WriteReq_miss_latency 5721912806 # number of WriteReq miss cycles
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses
|
|
|
|
|
system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses
|
|
|
|
|
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.iocache.WriteReq_mshr_miss_latency 3561059998 # number of WriteReq MSHR miss cycles
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
|
2008-10-21 01:00:07 +02:00
|
|
|
system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.iocache.avg_blocked_cycles::no_mshrs 6175.549096 # average number of cycles each access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2008-10-21 01:00:07 +02:00
|
|
|
system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
2010-11-08 20:58:24 +01:00
|
|
|
system.iocache.blocked::no_mshrs 10459 # number of cycles access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.iocache.blocked_cycles::no_mshrs 64590068 # number of cycles access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2008-10-21 01:00:07 +02:00
|
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
|
2010-09-09 20:40:19 +02:00
|
|
|
system.iocache.demand_accesses::1 41724 # number of demand (read+write) accesses
|
|
|
|
|
system.iocache.demand_accesses::total 41724 # number of demand (read+write) accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.iocache.demand_avg_miss_latency::1 137612.376666 # average overall miss latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.demand_avg_miss_latency::total inf # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.iocache.demand_avg_mshr_miss_latency 85608.810181 # average overall mshr miss latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.demand_hits::0 0 # number of demand (read+write) hits
|
|
|
|
|
system.iocache.demand_hits::1 0 # number of demand (read+write) hits
|
|
|
|
|
system.iocache.demand_hits::total 0 # number of demand (read+write) hits
|
2011-01-18 23:30:06 +01:00
|
|
|
system.iocache.demand_miss_latency 5741738804 # number of demand (read+write) miss cycles
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_misses::0 0 # number of demand (read+write) misses
|
2010-09-09 20:40:19 +02:00
|
|
|
system.iocache.demand_misses::1 41724 # number of demand (read+write) misses
|
|
|
|
|
system.iocache.demand_misses::total 41724 # number of demand (read+write) misses
|
2008-10-21 01:00:07 +02:00
|
|
|
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2011-01-18 23:30:06 +01:00
|
|
|
system.iocache.demand_mshr_miss_latency 3571941996 # number of demand (read+write) MSHR miss cycles
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
2010-09-09 20:40:19 +02:00
|
|
|
system.iocache.demand_mshr_misses 41724 # number of demand (read+write) MSHR misses
|
2008-10-21 01:00:07 +02:00
|
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-01-18 23:30:06 +01:00
|
|
|
system.iocache.occ_%::1 0.029206 # Average percentage of cache occupancy
|
|
|
|
|
system.iocache.occ_blocks::1 0.467303 # Average occupied blocks per context
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
|
2010-09-09 20:40:19 +02:00
|
|
|
system.iocache.overall_accesses::1 41724 # number of overall (read+write) accesses
|
|
|
|
|
system.iocache.overall_accesses::total 41724 # number of overall (read+write) accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.iocache.overall_avg_miss_latency::1 137612.376666 # average overall miss latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.overall_avg_miss_latency::total inf # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.iocache.overall_avg_mshr_miss_latency 85608.810181 # average overall mshr miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.overall_hits::0 0 # number of overall hits
|
|
|
|
|
system.iocache.overall_hits::1 0 # number of overall hits
|
|
|
|
|
system.iocache.overall_hits::total 0 # number of overall hits
|
2011-01-18 23:30:06 +01:00
|
|
|
system.iocache.overall_miss_latency 5741738804 # number of overall miss cycles
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_misses::0 0 # number of overall misses
|
2010-09-09 20:40:19 +02:00
|
|
|
system.iocache.overall_misses::1 41724 # number of overall misses
|
|
|
|
|
system.iocache.overall_misses::total 41724 # number of overall misses
|
2008-10-21 01:00:07 +02:00
|
|
|
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
|
2011-01-18 23:30:06 +01:00
|
|
|
system.iocache.overall_mshr_miss_latency 3571941996 # number of overall MSHR miss cycles
|
2010-02-25 19:08:41 +01:00
|
|
|
system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
2010-09-09 20:40:19 +02:00
|
|
|
system.iocache.overall_mshr_misses 41724 # number of overall MSHR misses
|
2008-10-21 01:00:07 +02:00
|
|
|
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2010-09-09 20:40:19 +02:00
|
|
|
system.iocache.replacements 41692 # number of replacements
|
|
|
|
|
system.iocache.sampled_refs 41708 # Sample count of references to valid blocks.
|
2008-10-21 01:00:07 +02:00
|
|
|
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-01-18 23:30:06 +01:00
|
|
|
system.iocache.tagsinuse 0.467303 # Cycle average of tags in use
|
2008-10-21 01:00:07 +02:00
|
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
2011-01-18 23:30:06 +01:00
|
|
|
system.iocache.warmup_cycle 1711286190000 # Cycle when the warmup percentage was hit.
|
2010-08-23 18:18:42 +02:00
|
|
|
system.iocache.writebacks 41520 # number of writebacks
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.ReadExReq_accesses::0 257294 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadExReq_accesses::1 42294 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadExReq_accesses::total 299588 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadExReq_avg_miss_latency::0 55984.033368 # average ReadExReq miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_miss_latency::1 838025.398663 # average ReadExReq miss latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency 40323.668210 # average ReadExReq mshr miss latency
|
|
|
|
|
system.l2c.ReadExReq_hits::0 140895 # number of ReadExReq hits
|
|
|
|
|
system.l2c.ReadExReq_hits::1 34518 # number of ReadExReq hits
|
|
|
|
|
system.l2c.ReadExReq_hits::total 175413 # number of ReadExReq hits
|
|
|
|
|
system.l2c.ReadExReq_miss_latency 6516485500 # number of ReadExReq miss cycles
|
|
|
|
|
system.l2c.ReadExReq_miss_rate::0 0.452397 # miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_miss_rate::1 0.183856 # miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_misses::0 116399 # number of ReadExReq misses
|
|
|
|
|
system.l2c.ReadExReq_misses::1 7776 # number of ReadExReq misses
|
|
|
|
|
system.l2c.ReadExReq_misses::total 124175 # number of ReadExReq misses
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_latency 5007191500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_rate::0 0.482619 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_rate::1 2.935996 # mshr miss rate for ReadExReq accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.ReadExReq_mshr_misses 124175 # number of ReadExReq MSHR misses
|
|
|
|
|
system.l2c.ReadReq_accesses::0 1807450 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::1 343665 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::total 2151115 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::0 52801.925207 # average ReadReq miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::1 3681603.345555 # average ReadReq miss latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.ReadReq_avg_mshr_miss_latency 40018.264766 # average ReadReq mshr miss latency
|
2008-10-21 01:00:07 +02:00
|
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.ReadReq_hits::0 1503171 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::1 339301 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::total 1842472 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_miss_latency 16066517000 # number of ReadReq miss cycles
|
|
|
|
|
system.l2c.ReadReq_miss_rate::0 0.168347 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::1 0.012698 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_misses::0 304279 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::1 4364 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::total 308643 # number of ReadReq misses
|
2010-09-22 08:07:35 +02:00
|
|
|
system.l2c.ReadReq_mshr_hits 16 # number of ReadReq MSHR hits
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.ReadReq_mshr_miss_latency 12350717000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::0 0.170753 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::1 0.898046 # mshr miss rate for ReadReq accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.ReadReq_mshr_misses 308627 # number of ReadReq MSHR misses
|
|
|
|
|
system.l2c.ReadReq_mshr_uncacheable_latency 840465500 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.l2c.SCUpgradeReq_accesses::0 609 # number of SCUpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.SCUpgradeReq_accesses::1 601 # number of SCUpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.SCUpgradeReq_accesses::total 1210 # number of SCUpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::0 4879.928315 # average SCUpgradeReq miss latency
|
|
|
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::1 4727.430556 # average SCUpgradeReq miss latency
|
2010-06-17 00:25:57 +02:00
|
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency
|
|
|
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40008.377425 # average SCUpgradeReq mshr miss latency
|
|
|
|
|
system.l2c.SCUpgradeReq_hits::0 51 # number of SCUpgradeReq hits
|
|
|
|
|
system.l2c.SCUpgradeReq_hits::1 25 # number of SCUpgradeReq hits
|
|
|
|
|
system.l2c.SCUpgradeReq_hits::total 76 # number of SCUpgradeReq hits
|
|
|
|
|
system.l2c.SCUpgradeReq_miss_latency 2723000 # number of SCUpgradeReq miss cycles
|
|
|
|
|
system.l2c.SCUpgradeReq_miss_rate::0 0.916256 # miss rate for SCUpgradeReq accesses
|
|
|
|
|
system.l2c.SCUpgradeReq_miss_rate::1 0.958403 # miss rate for SCUpgradeReq accesses
|
|
|
|
|
system.l2c.SCUpgradeReq_misses::0 558 # number of SCUpgradeReq misses
|
|
|
|
|
system.l2c.SCUpgradeReq_misses::1 576 # number of SCUpgradeReq misses
|
|
|
|
|
system.l2c.SCUpgradeReq_misses::total 1134 # number of SCUpgradeReq misses
|
|
|
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency 45369500 # number of SCUpgradeReq MSHR miss cycles
|
|
|
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.862069 # mshr miss rate for SCUpgradeReq accesses
|
|
|
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.886855 # mshr miss rate for SCUpgradeReq accesses
|
2010-06-17 00:25:57 +02:00
|
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses
|
|
|
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.SCUpgradeReq_mshr_misses 1134 # number of SCUpgradeReq MSHR misses
|
|
|
|
|
system.l2c.UpgradeReq_accesses::0 2885 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.UpgradeReq_accesses::1 1622 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.UpgradeReq_accesses::total 4507 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.UpgradeReq_avg_miss_latency::0 5855.677656 # average UpgradeReq miss latency
|
|
|
|
|
system.l2c.UpgradeReq_avg_miss_latency::1 12557.737628 # average UpgradeReq miss latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency
|
|
|
|
|
system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
|
2010-12-08 01:19:57 +01:00
|
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency 40016.987260 # average UpgradeReq mshr miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.UpgradeReq_hits::0 155 # number of UpgradeReq hits
|
2010-12-08 01:19:57 +01:00
|
|
|
system.l2c.UpgradeReq_hits::1 349 # number of UpgradeReq hits
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.UpgradeReq_hits::total 504 # number of UpgradeReq hits
|
|
|
|
|
system.l2c.UpgradeReq_miss_latency 15986000 # number of UpgradeReq miss cycles
|
|
|
|
|
system.l2c.UpgradeReq_miss_rate::0 0.946274 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_miss_rate::1 0.784834 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_misses::0 2730 # number of UpgradeReq misses
|
|
|
|
|
system.l2c.UpgradeReq_misses::1 1273 # number of UpgradeReq misses
|
2010-12-08 01:19:57 +01:00
|
|
|
system.l2c.UpgradeReq_misses::total 4003 # number of UpgradeReq misses
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_latency 160188000 # number of UpgradeReq MSHR miss cycles
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.UpgradeReq_mshr_miss_rate::0 1.387522 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_rate::1 2.467941 # mshr miss rate for UpgradeReq accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
|
2010-12-08 01:19:57 +01:00
|
|
|
system.l2c.UpgradeReq_mshr_misses 4003 # number of UpgradeReq MSHR misses
|
2008-10-21 01:00:07 +02:00
|
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.WriteReq_mshr_uncacheable_latency 1532818498 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.l2c.Writeback_accesses::0 810405 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.l2c.Writeback_accesses::total 810405 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.l2c.Writeback_hits::0 810405 # number of Writeback hits
|
|
|
|
|
system.l2c.Writeback_hits::total 810405 # number of Writeback hits
|
2009-04-22 19:25:17 +02:00
|
|
|
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.avg_refs 5.657708 # Average number of references to valid blocks.
|
2009-04-22 19:25:17 +02:00
|
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2008-10-21 01:00:07 +02:00
|
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.demand_accesses::0 2064744 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::1 385959 # number of demand (read+write) accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.demand_accesses::total 2450703 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_avg_miss_latency::0 53682.394848 # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_miss_latency::1 1860214.373970 # average overall miss latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_miss_latency::total inf # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.demand_avg_mshr_miss_latency 40105.887912 # average overall mshr miss latency
|
|
|
|
|
system.l2c.demand_hits::0 1644066 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::1 373819 # number of demand (read+write) hits
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.demand_hits::2 0 # number of demand (read+write) hits
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.demand_hits::total 2017885 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_miss_latency 22583002500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.l2c.demand_miss_rate::0 0.203743 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::1 0.031454 # miss rate for demand accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.demand_misses::0 420678 # number of demand (read+write) misses
|
|
|
|
|
system.l2c.demand_misses::1 12140 # number of demand (read+write) misses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.demand_misses::2 0 # number of demand (read+write) misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.demand_misses::total 432818 # number of demand (read+write) misses
|
2010-09-22 08:07:35 +02:00
|
|
|
system.l2c.demand_mshr_hits 16 # number of demand (read+write) MSHR hits
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.demand_mshr_miss_latency 17357908500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::0 0.209615 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::1 1.121368 # mshr miss rate for demand accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.demand_mshr_misses 432802 # number of demand (read+write) MSHR misses
|
2008-10-21 01:00:07 +02:00
|
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.occ_%::0 0.187715 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_%::1 0.005740 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_%::2 0.351851 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_blocks::0 12302.114841 # Average occupied blocks per context
|
|
|
|
|
system.l2c.occ_blocks::1 376.171902 # Average occupied blocks per context
|
|
|
|
|
system.l2c.occ_blocks::2 23058.891094 # Average occupied blocks per context
|
|
|
|
|
system.l2c.overall_accesses::0 2064744 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::1 385959 # number of overall (read+write) accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.overall_accesses::total 2450703 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_avg_miss_latency::0 53682.394848 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_miss_latency::1 1860214.373970 # average overall miss latency
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_miss_latency::total inf # average overall miss latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.overall_avg_mshr_miss_latency 40105.887912 # average overall mshr miss latency
|
2008-10-21 01:00:07 +02:00
|
|
|
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.overall_hits::0 1644066 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::1 373819 # number of overall hits
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.overall_hits::2 0 # number of overall hits
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.overall_hits::total 2017885 # number of overall hits
|
|
|
|
|
system.l2c.overall_miss_latency 22583002500 # number of overall miss cycles
|
|
|
|
|
system.l2c.overall_miss_rate::0 0.203743 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::1 0.031454 # miss rate for overall accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.overall_misses::0 420678 # number of overall misses
|
|
|
|
|
system.l2c.overall_misses::1 12140 # number of overall misses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.overall_misses::2 0 # number of overall misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.overall_misses::total 432818 # number of overall misses
|
2010-09-22 08:07:35 +02:00
|
|
|
system.l2c.overall_mshr_hits 16 # number of overall MSHR hits
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.overall_mshr_miss_latency 17357908500 # number of overall MSHR miss cycles
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::0 0.209615 # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::1 1.121368 # mshr miss rate for overall accesses
|
2010-02-25 19:08:41 +01:00
|
|
|
system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.overall_mshr_misses 432802 # number of overall MSHR misses
|
|
|
|
|
system.l2c.overall_mshr_uncacheable_latency 2373283998 # number of overall MSHR uncacheable cycles
|
2008-10-21 01:00:07 +02:00
|
|
|
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.replacements 395562 # number of replacements
|
2010-12-08 01:19:57 +01:00
|
|
|
system.l2c.sampled_refs 431632 # Sample count of references to valid blocks.
|
2008-10-21 01:00:07 +02:00
|
|
|
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.tagsinuse 35737.177838 # Cycle average of tags in use
|
|
|
|
|
system.l2c.total_refs 2442048 # Total number of references to valid blocks.
|
2010-09-22 08:07:35 +02:00
|
|
|
system.l2c.warmup_cycle 9270445000 # Cycle when the warmup percentage was hit.
|
2011-01-18 23:30:06 +01:00
|
|
|
system.l2c.writebacks 121361 # number of writebacks
|
2009-04-22 19:25:17 +02:00
|
|
|
system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post
|
|
|
|
|
system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post
|
|
|
|
|
system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post
|
|
|
|
|
system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post
|
|
|
|
|
system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post
|
|
|
|
|
system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post
|
|
|
|
|
system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post
|
|
|
|
|
system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post
|
|
|
|
|
system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post
|
2008-10-21 01:00:07 +02:00
|
|
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
|
|
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
|
|
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
|
|
|
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
|
|
|
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
|
|
|
|
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
|
|
|
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
|
|
|
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
|
|
|
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
|
|
|
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
|
|
|
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
|
|
|
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
|
|
|
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
|
|
|
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
|
|
|
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
|
|
|
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
|
|
|
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
|
|
|
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
|
|
|
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
|
|
|
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
|
|
|
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
|
|
|
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
