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gem5/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt

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Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
---------- Begin Simulation Statistics ----------
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
host_inst_rate 96877 # Simulator instruction rate (inst/s)
host_mem_usage 294552 # Number of bytes of host memory used
host_seconds 589.85 # Real time elapsed on the host
host_tick_rate 3232468675 # Simulator tick rate (ticks/s)
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
sim_insts 57142904 # Number of instructions simulated
sim_seconds 1.906675 # Number of seconds simulated
sim_ticks 1906675009500 # Number of ticks simulated
tests: update tests because of changes in stat names and in the stats package
2009-03-07 23:30:55 +01:00
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.BPredUnit.BTBHits 6037320 # Number of BTB hits
system.cpu0.BPredUnit.BTBLookups 11351967 # Number of BTB lookups
system.cpu0.BPredUnit.RASInCorrect 27838 # Number of incorrect RAS predictions.
system.cpu0.BPredUnit.condIncorrect 689824 # Number of conditional branches incorrect
system.cpu0.BPredUnit.condPredicted 10583458 # Number of conditional branches predicted
system.cpu0.BPredUnit.lookups 12665096 # Number of BP lookups
system.cpu0.BPredUnit.usedRAS 889173 # Number of times the RAS was used to get a target.
system.cpu0.commit.COM:branches 7532122 # Number of branches committed
system.cpu0.commit.COM:bw_lim_events 868474 # number cycles where commit BW limit reached
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.commit.COM:committed_per_cycle::samples 85531488 # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::mean 0.582160 # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::stdev 1.346009 # Number of insts commited each cycle
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu0.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.commit.COM:committed_per_cycle::0 64118131 74.96% 74.96% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::1 9419985 11.01% 85.98% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::2 5464530 6.39% 92.37% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::3 2511151 2.94% 95.30% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::4 1836761 2.15% 97.45% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::5 609168 0.71% 98.16% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::6 353146 0.41% 98.58% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::7 350142 0.41% 98.98% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::8 868474 1.02% 100.00% # Number of insts commited each cycle
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu0.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.commit.COM:committed_per_cycle::total 85531488 # Number of insts commited each cycle
system.cpu0.commit.COM:count 49793044 # Number of instructions committed
system.cpu0.commit.COM:loads 8087035 # Number of loads committed
system.cpu0.commit.COM:membars 188923 # Number of memory barriers committed
system.cpu0.commit.COM:refs 13499415 # Number of memory references committed
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.commit.branchMispredicts 656667 # The number of times a branch was mispredicted
system.cpu0.commit.commitCommittedInsts 49793044 # The number of committed instructions
system.cpu0.commit.commitNonSpecStalls 558254 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.commitSquashedInsts 7909295 # The number of squashed insts skipped by commit
system.cpu0.committedInsts 46950766 # Number of Instructions Simulated
system.cpu0.committedInsts_total 46950766 # Number of Instructions Simulated
system.cpu0.cpi 2.557983 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 2.557983 # CPI: Total CPI of All Threads
system.cpu0.dcache.LoadLockedReq_accesses::0 175325 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 175325 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 13891.838160 # average LoadLockedReq miss latency
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10378.791946 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_hits::0 156714 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 156714 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_miss_latency 258541000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.106151 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_misses::0 18611 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 18611 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_mshr_hits 3711 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 154644000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.084985 # mshr miss rate for LoadLockedReq accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.dcache.LoadLockedReq_mshr_misses 14900 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.ReadReq_accesses::0 8024582 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 8024582 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_avg_miss_latency::0 24823.193475 # average ReadReq miss latency
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23777.445948 # average ReadReq mshr miss latency
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.dcache.ReadReq_hits::0 6693712 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 6693712 # number of ReadReq hits
system.cpu0.dcache.ReadReq_miss_latency 33036443500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_rate::0 0.165849 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_misses::0 1330870 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 1330870 # number of ReadReq misses
system.cpu0.dcache.ReadReq_mshr_hits 349277 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_miss_latency 23339774500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.122323 # mshr miss rate for ReadReq accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.dcache.ReadReq_mshr_misses 981593 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 922661000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_accesses::0 183239 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 183239 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 47093.631014 # average StoreCondReq miss latency
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 44096.203773 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_hits::0 165905 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 165905 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_miss_latency 816321000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_rate::0 0.094598 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_misses::0 17334 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 17334 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_mshr_miss_latency 764319500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.094592 # mshr miss rate for StoreCondReq accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.dcache.StoreCondReq_mshr_misses 17333 # number of StoreCondReq MSHR misses
system.cpu0.dcache.WriteReq_accesses::0 5213801 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 5213801 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_avg_miss_latency::0 48517.051427 # average WriteReq miss latency
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53069.050136 # average WriteReq mshr miss latency
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.dcache.WriteReq_hits::0 3350446 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 3350446 # number of WriteReq hits
system.cpu0.dcache.WriteReq_miss_latency 90404490361 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_rate::0 0.357389 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_misses::0 1863355 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 1863355 # number of WriteReq misses
system.cpu0.dcache.WriteReq_mshr_hits 1547991 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_miss_latency 16736067927 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.060486 # mshr miss rate for WriteReq accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.dcache.WriteReq_mshr_misses 315364 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1337193497 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9713.605174 # average number of cycles each access was blocked
ALPHA: The previous O3 patch causes a slight stats change with fullsys.
2010-08-23 18:18:42 +02:00
system.cpu0.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.dcache.avg_refs 8.464502 # Average number of references to valid blocks.
system.cpu0.dcache.blocked::no_mshrs 124903 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 6 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_mshrs 1213258427 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 129000 # number of cycles access was blocked
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.dcache.demand_accesses::0 13238383 # number of demand (read+write) accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.dcache.demand_accesses::total 13238383 # number of demand (read+write) accesses
system.cpu0.dcache.demand_avg_miss_latency::0 38645.034041 # average overall miss latency
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.dcache.demand_avg_mshr_miss_latency 30899.900634 # average overall mshr miss latency
system.cpu0.dcache.demand_hits::0 10044158 # number of demand (read+write) hits
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.dcache.demand_hits::total 10044158 # number of demand (read+write) hits
system.cpu0.dcache.demand_miss_latency 123440933861 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_rate::0 0.241285 # miss rate for demand accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.dcache.demand_misses::0 3194225 # number of demand (read+write) misses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.dcache.demand_misses::total 3194225 # number of demand (read+write) misses
system.cpu0.dcache.demand_mshr_hits 1897268 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_miss_latency 40075842427 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_rate::0 0.097969 # mshr miss rate for demand accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.dcache.demand_mshr_misses 1296957 # number of demand (read+write) MSHR misses
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.dcache.occ_%::0 0.975170 # Average percentage of cache occupancy
system.cpu0.dcache.occ_%::1 -0.005787 # Average percentage of cache occupancy
system.cpu0.dcache.occ_blocks::0 499.286946 # Average occupied blocks per context
system.cpu0.dcache.occ_blocks::1 -2.962988 # Average occupied blocks per context
system.cpu0.dcache.overall_accesses::0 13238383 # number of overall (read+write) accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.dcache.overall_accesses::total 13238383 # number of overall (read+write) accesses
system.cpu0.dcache.overall_avg_miss_latency::0 38645.034041 # average overall miss latency
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.dcache.overall_avg_mshr_miss_latency 30899.900634 # average overall mshr miss latency
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.dcache.overall_hits::0 10044158 # number of overall hits
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.dcache.overall_hits::1 0 # number of overall hits
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.dcache.overall_hits::total 10044158 # number of overall hits
system.cpu0.dcache.overall_miss_latency 123440933861 # number of overall miss cycles
system.cpu0.dcache.overall_miss_rate::0 0.241285 # miss rate for overall accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.dcache.overall_misses::0 3194225 # number of overall misses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.dcache.overall_misses::1 0 # number of overall misses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.dcache.overall_misses::total 3194225 # number of overall misses
system.cpu0.dcache.overall_mshr_hits 1897268 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_miss_latency 40075842427 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_rate::0 0.097969 # mshr miss rate for overall accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.dcache.overall_mshr_misses 1296957 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_uncacheable_latency 2259854497 # number of overall MSHR uncacheable cycles
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.dcache.replacements 1243005 # number of replacements
system.cpu0.dcache.sampled_refs 1243517 # Sample count of references to valid blocks.
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.dcache.tagsinuse 497.305455 # Cycle average of tags in use
system.cpu0.dcache.total_refs 10525752 # Total number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.writebacks 379678 # number of writebacks
system.cpu0.decode.DECODE:BlockedCycles 40702182 # Number of cycles decode is blocked
system.cpu0.decode.DECODE:BranchMispred 33733 # Number of times decode detected a branch misprediction
system.cpu0.decode.DECODE:BranchResolved 526303 # Number of times decode resolved a branch
system.cpu0.decode.DECODE:DecodedInsts 63705520 # Number of instructions handled by decode
system.cpu0.decode.DECODE:IdleCycles 32342676 # Number of cycles decode is idle
system.cpu0.decode.DECODE:RunCycles 11446881 # Number of cycles decode is running
system.cpu0.decode.DECODE:SquashCycles 1370864 # Number of cycles decode is squashing
system.cpu0.decode.DECODE:SquashedInsts 100557 # Number of squashed instructions handled by decode
system.cpu0.decode.DECODE:UnblockCycles 1039748 # Number of cycles decode is unblocking
system.cpu0.dtb.data_accesses 867376 # DTB accesses
system.cpu0.dtb.data_acv 796 # DTB access violations
system.cpu0.dtb.data_hits 14352894 # DTB hits
system.cpu0.dtb.data_misses 32526 # DTB misses
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.dtb.read_accesses 645773 # DTB read accesses
system.cpu0.dtb.read_acv 589 # DTB read access violations
system.cpu0.dtb.read_hits 8766713 # DTB read hits
system.cpu0.dtb.read_misses 26860 # DTB read misses
system.cpu0.dtb.write_accesses 221603 # DTB write accesses
system.cpu0.dtb.write_acv 207 # DTB write access violations
system.cpu0.dtb.write_hits 5586181 # DTB write hits
system.cpu0.dtb.write_misses 5666 # DTB write misses
system.cpu0.fetch.Branches 12665096 # Number of branches that fetch encountered
system.cpu0.fetch.CacheLines 7900913 # Number of cache lines fetched
system.cpu0.fetch.Cycles 20614864 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.IcacheSquashes 378846 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.Insts 65028610 # Number of instructions fetch has processed
system.cpu0.fetch.MiscStallCycles 1156 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.SquashCycles 811969 # Number of cycles fetch has spent squashing
system.cpu0.fetch.branchRate 0.105455 # Number of branch fetches per cycle
system.cpu0.fetch.icacheStallCycles 7900913 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.predictedBranches 6926493 # Number of branches that fetch has predicted taken
system.cpu0.fetch.rate 0.541457 # Number of inst fetches per cycle
system.cpu0.fetch.rateDist::samples 86902352 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 0.748295 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 2.044395 # Number of instructions fetched each cycle (Total)
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.fetch.rateDist::0 74220009 85.41% 85.41% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 901339 1.04% 86.44% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 1804427 2.08% 88.52% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 827724 0.95% 89.47% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 2764395 3.18% 92.65% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5 592140 0.68% 93.33% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 693087 0.80% 94.13% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 935405 1.08% 95.21% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 4163826 4.79% 100.00% # Number of instructions fetched each cycle (Total)
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.fetch.rateDist::total 86902352 # Number of instructions fetched each cycle (Total)
system.cpu0.icache.ReadReq_accesses::0 7900913 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 7900913 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_avg_miss_latency::0 15047.285683 # average ReadReq miss latency
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12005.143233 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_hits::0 7053204 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 7053204 # number of ReadReq hits
system.cpu0.icache.ReadReq_miss_latency 12755719499 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_rate::0 0.107293 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_misses::0 847709 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 847709 # number of ReadReq misses
system.cpu0.icache.ReadReq_mshr_hits 37907 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_miss_latency 9721789000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.102495 # mshr miss rate for ReadReq accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.icache.ReadReq_mshr_misses 809802 # number of ReadReq MSHR misses
system.cpu0.icache.avg_blocked_cycles::no_mshrs 11235.849057 # average number of cycles each access was blocked
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.icache.avg_refs 8.711370 # Average number of references to valid blocks.
system.cpu0.icache.blocked::no_mshrs 53 # number of cycles access was blocked
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.icache.blocked_cycles::no_mshrs 595500 # number of cycles access was blocked
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu0.icache.cache_copies 0 # number of cache copies performed
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.icache.demand_accesses::0 7900913 # number of demand (read+write) accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.icache.demand_accesses::total 7900913 # number of demand (read+write) accesses
system.cpu0.icache.demand_avg_miss_latency::0 15047.285683 # average overall miss latency
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.icache.demand_avg_mshr_miss_latency 12005.143233 # average overall mshr miss latency
system.cpu0.icache.demand_hits::0 7053204 # number of demand (read+write) hits
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.icache.demand_hits::total 7053204 # number of demand (read+write) hits
system.cpu0.icache.demand_miss_latency 12755719499 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_rate::0 0.107293 # miss rate for demand accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.icache.demand_misses::0 847709 # number of demand (read+write) misses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.icache.demand_misses::total 847709 # number of demand (read+write) misses
system.cpu0.icache.demand_mshr_hits 37907 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_miss_latency 9721789000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_rate::0 0.102495 # mshr miss rate for demand accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.icache.demand_mshr_misses 809802 # number of demand (read+write) MSHR misses
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.icache.occ_%::0 0.995703 # Average percentage of cache occupancy
system.cpu0.icache.occ_blocks::0 509.799701 # Average occupied blocks per context
system.cpu0.icache.overall_accesses::0 7900913 # number of overall (read+write) accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.icache.overall_accesses::total 7900913 # number of overall (read+write) accesses
system.cpu0.icache.overall_avg_miss_latency::0 15047.285683 # average overall miss latency
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.icache.overall_avg_mshr_miss_latency 12005.143233 # average overall mshr miss latency
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.icache.overall_hits::0 7053204 # number of overall hits
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.icache.overall_hits::1 0 # number of overall hits
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.icache.overall_hits::total 7053204 # number of overall hits
system.cpu0.icache.overall_miss_latency 12755719499 # number of overall miss cycles
system.cpu0.icache.overall_miss_rate::0 0.107293 # miss rate for overall accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.icache.overall_misses::0 847709 # number of overall misses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.icache.overall_misses::1 0 # number of overall misses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.icache.overall_misses::total 847709 # number of overall misses
system.cpu0.icache.overall_mshr_hits 37907 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_miss_latency 9721789000 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_rate::0 0.102495 # mshr miss rate for overall accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.icache.overall_mshr_misses 809802 # number of overall MSHR misses
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.icache.replacements 809144 # number of replacements
system.cpu0.icache.sampled_refs 809655 # Sample count of references to valid blocks.
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.icache.tagsinuse 509.799701 # Cycle average of tags in use
system.cpu0.icache.total_refs 7053204 # Total number of references to valid blocks.
system.cpu0.icache.warmup_cycle 25253244000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.writebacks 2 # number of writebacks
system.cpu0.idleCycles 33196891 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.iew.EXEC:branches 8125364 # Number of branches executed
system.cpu0.iew.EXEC:nop 3226641 # number of nop insts executed
system.cpu0.iew.EXEC:rate 0.422366 # Inst execution rate
system.cpu0.iew.EXEC:refs 14615271 # number of memory reference insts executed
system.cpu0.iew.EXEC:stores 5604883 # Number of stores executed
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu0.iew.EXEC:swp 0 # number of swp insts executed
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.iew.WB:consumers 31032245 # num instructions consuming a value
system.cpu0.iew.WB:count 50227097 # cumulative count of insts written-back
system.cpu0.iew.WB:fanout 0.763961 # average fanout of values written-back
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.iew.WB:producers 23707433 # num instructions producing a value
system.cpu0.iew.WB:rate 0.418213 # insts written-back per cycle
system.cpu0.iew.WB:sent 50304093 # cumulative count of insts sent to commit
system.cpu0.iew.branchMispredicts 713455 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewBlockCycles 9315247 # Number of cycles IEW is blocking
system.cpu0.iew.iewDispLoadInsts 9510497 # Number of dispatched load instructions
system.cpu0.iew.iewDispNonSpecInsts 1499135 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewDispSquashedInsts 880070 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispStoreInsts 5918886 # Number of dispatched store instructions
system.cpu0.iew.iewDispatchedInsts 57821470 # Number of instructions dispatched to IQ
system.cpu0.iew.iewExecLoadInsts 9010388 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 501816 # Number of squashed instructions skipped in execute
system.cpu0.iew.iewExecutedInsts 50725864 # Number of executed instructions
system.cpu0.iew.iewIQFullEvents 38579 # Number of times the IQ has become full, causing a stall
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.iew.iewLSQFullEvents 5036 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.iewSquashCycles 1370864 # Number of cycles IEW is squashing
system.cpu0.iew.iewUnblockCycles 530507 # Number of cycles IEW is unblocking
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.iew.lsq.thread.0.cacheBlocked 262065 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.lsq.thread.0.forwLoads 407910 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread.0.ignoredResponses 13281 # Number of memory responses ignored because the instruction is squashed
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.iew.lsq.thread.0.memOrderViolation 40793 # Number of memory ordering violations
system.cpu0.iew.lsq.thread.0.rescheduledLoads 18036 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread.0.squashedLoads 1423462 # Number of loads squashed
system.cpu0.iew.lsq.thread.0.squashedStores 506506 # Number of stores squashed
system.cpu0.iew.memOrderViolationEvents 40793 # Number of memory order violations
system.cpu0.iew.predictedNotTakenIncorrect 332881 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.predictedTakenIncorrect 380574 # Number of branches that were predicted taken incorrectly
system.cpu0.ipc 0.390933 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.390933 # IPC: Total IPC of All Threads
system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 3770 0.01% 0.01% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IntAlu 35394718 69.09% 69.10% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IntMult 55798 0.11% 69.21% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 69.21% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 15086 0.03% 69.24% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 69.24% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 69.24% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 69.24% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 1884 0.00% 69.24% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 69.24% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::MemRead 9327899 18.21% 87.45% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::MemWrite 5645566 11.02% 98.47% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IprAccess 782961 1.53% 100.00% # Type of FU issued
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.iq.ISSUE:FU_type_0::total 51227682 # Type of FU issued
system.cpu0.iq.ISSUE:fu_busy_cnt 363911 # FU busy when requested
system.cpu0.iq.ISSUE:fu_busy_rate 0.007104 # FU busy rate (busy events/executed inst)
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu0.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.iq.ISSUE:fu_full::IntAlu 39751 10.92% 10.92% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 10.92% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.92% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.92% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.92% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.92% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.92% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.92% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.92% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::MemRead 236746 65.06% 75.98% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::MemWrite 87414 24.02% 100.00% # attempts to use FU when none available
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.iq.ISSUE:issued_per_cycle::samples 86902352 # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.589486 # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.157706 # Number of insts issued each cycle
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.iq.ISSUE:issued_per_cycle::0 61545337 70.82% 70.82% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::1 12554046 14.45% 85.27% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::2 5586431 6.43% 91.70% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::3 3486187 4.01% 95.71% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::4 2264793 2.61% 98.31% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::5 945170 1.09% 99.40% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::6 407098 0.47% 99.87% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::7 91717 0.11% 99.98% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::8 21573 0.02% 100.00% # Number of insts issued each cycle
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.iq.ISSUE:issued_per_cycle::total 86902352 # Number of insts issued each cycle
system.cpu0.iq.ISSUE:rate 0.426545 # Inst issue rate
system.cpu0.iq.iqInstsAdded 52886391 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqInstsIssued 51227682 # Number of instructions issued
system.cpu0.iq.iqNonSpecInstsAdded 1708438 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqSquashedInstsExamined 7322246 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedInstsIssued 33660 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedNonSpecRemoved 1150184 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.iqSquashedOperandsExamined 3910877 # Number of squashed operands that are examined and possibly removed from graph
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
system.cpu0.itb.data_accesses 0 # DTB accesses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_hits 0 # DTB hits
system.cpu0.itb.data_misses 0 # DTB misses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.itb.fetch_accesses 999568 # ITB accesses
system.cpu0.itb.fetch_acv 893 # ITB acv
system.cpu0.itb.fetch_hits 968847 # ITB hits
system.cpu0.itb.fetch_misses 30721 # ITB misses
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.write_acv 0 # DTB write access violations
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.kern.callpal::wripir 393 0.25% 0.25% # number of callpals executed
system.cpu0.kern.callpal::wrmces 1 0.00% 0.25% # number of callpals executed
system.cpu0.kern.callpal::wrfen 1 0.00% 0.25% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.25% # number of callpals executed
system.cpu0.kern.callpal::swpctx 3319 2.08% 2.33% # number of callpals executed
system.cpu0.kern.callpal::tbi 50 0.03% 2.36% # number of callpals executed
system.cpu0.kern.callpal::wrent 7 0.00% 2.36% # number of callpals executed
system.cpu0.kern.callpal::swpipl 144424 90.42% 92.78% # number of callpals executed
system.cpu0.kern.callpal::rdps 6390 4.00% 96.78% # number of callpals executed
system.cpu0.kern.callpal::wrkgp 1 0.00% 96.79% # number of callpals executed
system.cpu0.kern.callpal::wrusp 3 0.00% 96.79% # number of callpals executed
system.cpu0.kern.callpal::rdusp 9 0.01% 96.79% # number of callpals executed
system.cpu0.kern.callpal::whami 2 0.00% 96.79% # number of callpals executed
system.cpu0.kern.callpal::rti 4592 2.87% 99.67% # number of callpals executed
system.cpu0.kern.callpal::callsys 391 0.24% 99.91% # number of callpals executed
system.cpu0.kern.callpal::imb 138 0.09% 100.00% # number of callpals executed
system.cpu0.kern.callpal::total 159723 # number of callpals executed
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.kern.inst.hwrei 175260 # number of hwrei instructions executed
system.cpu0.kern.inst.quiesce 6689 # number of quiesce instructions executed
system.cpu0.kern.ipl_count::0 61186 40.39% 40.39% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21 239 0.16% 40.55% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22 1930 1.27% 41.82% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30 300 0.20% 42.02% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31 87830 57.98% 100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total 151485 # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0 60407 49.12% 49.12% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21 239 0.19% 49.31% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22 1930 1.57% 50.88% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30 300 0.24% 51.13% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31 60108 48.87% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total 122984 # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0 1866417310500 97.89% 97.89% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21 97564500 0.01% 97.89% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22 399841000 0.02% 97.91% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30 136212500 0.01% 97.92% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31 39623165500 2.08% 100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total 1906674094000 # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0 0.987268 # fraction of swpipl calls that actually changed the ipl
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.kern.ipl_used::31 0.684368 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.mode_good::kernel 1353
system.cpu0.kern.mode_good::user 1354
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu0.kern.mode_good::idle 0
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.kern.mode_switch::kernel 7157 # number of protection mode switches
system.cpu0.kern.mode_switch::user 1354 # number of protection mode switches
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.kern.mode_switch_good::kernel 0.189046 # fraction of useful protection mode switches
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.kern.mode_ticks::kernel 1904400738500 99.88% 99.88% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user 2273347500 0.12% 100.00% # number of ticks spent at the given mode
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu0.kern.swap_context 3320 # number of times the context was actually changed
system.cpu0.kern.syscall::2 8 3.45% 3.45% # number of syscalls executed
system.cpu0.kern.syscall::3 20 8.62% 12.07% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.72% 13.79% # number of syscalls executed
system.cpu0.kern.syscall::6 33 14.22% 28.02% # number of syscalls executed
system.cpu0.kern.syscall::12 1 0.43% 28.45% # number of syscalls executed
system.cpu0.kern.syscall::17 9 3.88% 32.33% # number of syscalls executed
system.cpu0.kern.syscall::19 10 4.31% 36.64% # number of syscalls executed
system.cpu0.kern.syscall::20 6 2.59% 39.22% # number of syscalls executed
system.cpu0.kern.syscall::23 1 0.43% 39.66% # number of syscalls executed
system.cpu0.kern.syscall::24 3 1.29% 40.95% # number of syscalls executed
system.cpu0.kern.syscall::33 7 3.02% 43.97% # number of syscalls executed
system.cpu0.kern.syscall::41 2 0.86% 44.83% # number of syscalls executed
system.cpu0.kern.syscall::45 39 16.81% 61.64% # number of syscalls executed
system.cpu0.kern.syscall::47 3 1.29% 62.93% # number of syscalls executed
system.cpu0.kern.syscall::48 10 4.31% 67.24% # number of syscalls executed
system.cpu0.kern.syscall::54 10 4.31% 71.55% # number of syscalls executed
system.cpu0.kern.syscall::58 1 0.43% 71.98% # number of syscalls executed
system.cpu0.kern.syscall::59 6 2.59% 74.57% # number of syscalls executed
system.cpu0.kern.syscall::71 27 11.64% 86.21% # number of syscalls executed
system.cpu0.kern.syscall::73 3 1.29% 87.50% # number of syscalls executed
system.cpu0.kern.syscall::74 7 3.02% 90.52% # number of syscalls executed
system.cpu0.kern.syscall::87 1 0.43% 90.95% # number of syscalls executed
system.cpu0.kern.syscall::90 3 1.29% 92.24% # number of syscalls executed
system.cpu0.kern.syscall::92 9 3.88% 96.12% # number of syscalls executed
system.cpu0.kern.syscall::97 2 0.86% 96.98% # number of syscalls executed
system.cpu0.kern.syscall::98 2 0.86% 97.84% # number of syscalls executed
system.cpu0.kern.syscall::132 1 0.43% 98.28% # number of syscalls executed
system.cpu0.kern.syscall::144 2 0.86% 99.14% # number of syscalls executed
system.cpu0.kern.syscall::147 2 0.86% 100.00% # number of syscalls executed
system.cpu0.kern.syscall::total 232 # number of syscalls executed
system.cpu0.memDep0.conflictingLoads 2539862 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 2208172 # Number of conflicting stores.
system.cpu0.memDep0.insertedLoads 9510497 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 5918886 # Number of stores inserted to the mem dependence unit.
system.cpu0.numCycles 120099243 # number of cpu cycles simulated
system.cpu0.rename.RENAME:BlockCycles 13446049 # Number of cycles rename is blocking
system.cpu0.rename.RENAME:CommittedMaps 34012953 # Number of HB maps that are committed
system.cpu0.rename.RENAME:IQFullEvents 1022261 # Number of times rename has blocked due to IQ full
system.cpu0.rename.RENAME:IdleCycles 33782009 # Number of cycles rename is idle
system.cpu0.rename.RENAME:LSQFullEvents 1807708 # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RENAME:ROBFullEvents 16757 # Number of times rename has blocked due to ROB full
system.cpu0.rename.RENAME:RenameLookups 73652966 # Number of register rename lookups that rename has made
system.cpu0.rename.RENAME:RenamedInsts 60220724 # Number of instructions processed by rename
system.cpu0.rename.RENAME:RenamedOperands 40595001 # Number of destination operands rename has renamed
system.cpu0.rename.RENAME:RunCycles 11156910 # Number of cycles rename is running
system.cpu0.rename.RENAME:SquashCycles 1370864 # Number of cycles rename is squashing
system.cpu0.rename.RENAME:UnblockCycles 4406747 # Number of cycles rename is unblocking
system.cpu0.rename.RENAME:UndoneMaps 6582046 # Number of HB maps that are undone due to squashing
system.cpu0.rename.RENAME:serializeStallCycles 22739771 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RENAME:serializingInsts 1403717 # count of serializing insts renamed
system.cpu0.rename.RENAME:skidInsts 10900390 # count of insts added to the skid buffer
system.cpu0.rename.RENAME:tempSerializingInsts 213877 # count of temporary serializing insts renamed
system.cpu0.timesIdled 1182515 # Number of times that the entire CPU went into an idle state and unscheduled itself
tests: update tests because of changes in stat names and in the stats package
2009-03-07 23:30:55 +01:00
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.BPredUnit.BTBHits 1168869 # Number of BTB hits
system.cpu1.BPredUnit.BTBLookups 2724358 # Number of BTB lookups
system.cpu1.BPredUnit.RASInCorrect 8216 # Number of incorrect RAS predictions.
system.cpu1.BPredUnit.condIncorrect 170435 # Number of conditional branches incorrect
system.cpu1.BPredUnit.condPredicted 2536443 # Number of conditional branches predicted
system.cpu1.BPredUnit.lookups 3058879 # Number of BP lookups
system.cpu1.BPredUnit.usedRAS 214059 # Number of times the RAS was used to get a target.
system.cpu1.commit.COM:branches 1536055 # Number of branches committed
system.cpu1.commit.COM:bw_lim_events 205800 # number cycles where commit BW limit reached
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.commit.COM:committed_per_cycle::samples 19921603 # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::mean 0.539460 # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::stdev 1.350836 # Number of insts commited each cycle
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu1.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.commit.COM:committed_per_cycle::0 15476427 77.69% 77.69% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::1 2094576 10.51% 88.20% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::2 801789 4.02% 92.23% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::3 588293 2.95% 95.18% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::4 417407 2.10% 97.27% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::5 144338 0.72% 98.00% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::6 104661 0.53% 98.52% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::7 88312 0.44% 98.97% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::8 205800 1.03% 100.00% # Number of insts commited each cycle
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu1.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.commit.COM:committed_per_cycle::total 19921603 # Number of insts commited each cycle
system.cpu1.commit.COM:count 10746901 # Number of instructions committed
system.cpu1.commit.COM:loads 2021572 # Number of loads committed
system.cpu1.commit.COM:membars 56653 # Number of memory barriers committed
system.cpu1.commit.COM:refs 3430255 # Number of memory references committed
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.commit.branchMispredicts 163240 # The number of times a branch was mispredicted
system.cpu1.commit.commitCommittedInsts 10746901 # The number of committed instructions
system.cpu1.commit.commitNonSpecStalls 172585 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.commitSquashedInsts 1766208 # The number of squashed insts skipped by commit
system.cpu1.committedInsts 10192138 # Number of Instructions Simulated
system.cpu1.committedInsts_total 10192138 # Number of Instructions Simulated
system.cpu1.cpi 2.158157 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 2.158157 # CPI: Total CPI of All Threads
system.cpu1.dcache.LoadLockedReq_accesses::0 48648 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 48648 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 10962.569444 # average LoadLockedReq miss latency
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 7807.164404 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_hits::0 41448 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 41448 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_miss_latency 78930500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.148002 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_misses::0 7200 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 7200 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_mshr_hits 570 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 51761500 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.136285 # mshr miss rate for LoadLockedReq accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.dcache.LoadLockedReq_mshr_misses 6630 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.ReadReq_accesses::0 2081061 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 2081061 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_avg_miss_latency::0 16526.110109 # average ReadReq miss latency
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11960.136769 # average ReadReq mshr miss latency
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.dcache.ReadReq_hits::0 1891958 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 1891958 # number of ReadReq hits
system.cpu1.dcache.ReadReq_miss_latency 3125137000 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_rate::0 0.090869 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_misses::0 189103 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 189103 # number of ReadReq misses
system.cpu1.dcache.ReadReq_mshr_hits 93175 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_miss_latency 1147312000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.046096 # mshr miss rate for ReadReq accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.dcache.ReadReq_mshr_misses 95928 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 16183000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.StoreCondReq_accesses::0 45890 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 45890 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 35468.138068 # average StoreCondReq miss latency
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 32471.951759 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_hits::0 36851 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 36851 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_miss_latency 320596500 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_rate::0 0.196971 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_misses::0 9039 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 9039 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_mshr_miss_latency 293481500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.196949 # mshr miss rate for StoreCondReq accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.dcache.StoreCondReq_mshr_misses 9038 # number of StoreCondReq MSHR misses
system.cpu1.dcache.WriteReq_accesses::0 1356401 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 1356401 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_avg_miss_latency::0 48468.442060 # average WriteReq miss latency
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 50000.550136 # average WriteReq mshr miss latency
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.dcache.WriteReq_hits::0 1038709 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 1038709 # number of WriteReq hits
system.cpu1.dcache.WriteReq_miss_latency 15398036295 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_rate::0 0.234217 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_misses::0 317692 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 317692 # number of WriteReq misses
system.cpu1.dcache.WriteReq_mshr_hits 255162 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_miss_latency 3126534400 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.046100 # mshr miss rate for WriteReq accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.dcache.WriteReq_mshr_misses 62530 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 383884000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 11747.407108 # average number of cycles each access was blocked
ALPHA: The previous O3 patch causes a slight stats change with fullsys.
2010-08-23 18:18:42 +02:00
system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.dcache.avg_refs 23.303685 # Average number of references to valid blocks.
system.cpu1.dcache.blocked::no_mshrs 12380 # number of cycles access was blocked
ALPHA: The previous O3 patch causes a slight stats change with fullsys.
2010-08-23 18:18:42 +02:00
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.dcache.blocked_cycles::no_mshrs 145432900 # number of cycles access was blocked
ALPHA: The previous O3 patch causes a slight stats change with fullsys.
2010-08-23 18:18:42 +02:00
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.dcache.demand_accesses::0 3437462 # number of demand (read+write) accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.dcache.demand_accesses::total 3437462 # number of demand (read+write) accesses
system.cpu1.dcache.demand_avg_miss_latency::0 36549.637023 # average overall miss latency
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.dcache.demand_avg_mshr_miss_latency 26971.477616 # average overall mshr miss latency
system.cpu1.dcache.demand_hits::0 2930667 # number of demand (read+write) hits
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.dcache.demand_hits::total 2930667 # number of demand (read+write) hits
system.cpu1.dcache.demand_miss_latency 18523173295 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_rate::0 0.147433 # miss rate for demand accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.dcache.demand_misses::0 506795 # number of demand (read+write) misses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.dcache.demand_misses::total 506795 # number of demand (read+write) misses
system.cpu1.dcache.demand_mshr_hits 348337 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_miss_latency 4273846400 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_rate::0 0.046097 # mshr miss rate for demand accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.dcache.demand_mshr_misses 158458 # number of demand (read+write) MSHR misses
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.dcache.occ_%::0 0.929332 # Average percentage of cache occupancy
system.cpu1.dcache.occ_blocks::0 475.817757 # Average occupied blocks per context
system.cpu1.dcache.overall_accesses::0 3437462 # number of overall (read+write) accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.dcache.overall_accesses::total 3437462 # number of overall (read+write) accesses
system.cpu1.dcache.overall_avg_miss_latency::0 36549.637023 # average overall miss latency
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.dcache.overall_avg_mshr_miss_latency 26971.477616 # average overall mshr miss latency
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.dcache.overall_hits::0 2930667 # number of overall hits
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.dcache.overall_hits::1 0 # number of overall hits
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.dcache.overall_hits::total 2930667 # number of overall hits
system.cpu1.dcache.overall_miss_latency 18523173295 # number of overall miss cycles
system.cpu1.dcache.overall_miss_rate::0 0.147433 # miss rate for overall accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.dcache.overall_misses::0 506795 # number of overall misses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.dcache.overall_misses::1 0 # number of overall misses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.dcache.overall_misses::total 506795 # number of overall misses
system.cpu1.dcache.overall_mshr_hits 348337 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_miss_latency 4273846400 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_rate::0 0.046097 # mshr miss rate for overall accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.dcache.overall_mshr_misses 158458 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_uncacheable_latency 400067000 # number of overall MSHR uncacheable cycles
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.dcache.replacements 131481 # number of replacements
system.cpu1.dcache.sampled_refs 131801 # Sample count of references to valid blocks.
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.dcache.tagsinuse 475.817757 # Cycle average of tags in use
system.cpu1.dcache.total_refs 3071449 # Total number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 1882597271000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.writebacks 66520 # number of writebacks
system.cpu1.decode.DECODE:BlockedCycles 8690485 # Number of cycles decode is blocked
system.cpu1.decode.DECODE:BranchMispred 7262 # Number of times decode detected a branch misprediction
system.cpu1.decode.DECODE:BranchResolved 129460 # Number of times decode resolved a branch
system.cpu1.decode.DECODE:DecodedInsts 14175016 # Number of instructions handled by decode
system.cpu1.decode.DECODE:IdleCycles 8601755 # Number of cycles decode is idle
system.cpu1.decode.DECODE:RunCycles 2517670 # Number of cycles decode is running
system.cpu1.decode.DECODE:SquashCycles 311026 # Number of cycles decode is squashing
system.cpu1.decode.DECODE:SquashedInsts 21330 # Number of squashed instructions handled by decode
system.cpu1.decode.DECODE:UnblockCycles 111692 # Number of cycles decode is unblocking
system.cpu1.dtb.data_accesses 379731 # DTB accesses
system.cpu1.dtb.data_acv 79 # DTB access violations
system.cpu1.dtb.data_hits 3682802 # DTB hits
system.cpu1.dtb.data_misses 10764 # DTB misses
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.dtb.read_accesses 273464 # DTB read accesses
system.cpu1.dtb.read_acv 11 # DTB read access violations
system.cpu1.dtb.read_hits 2232523 # DTB read hits
system.cpu1.dtb.read_misses 8601 # DTB read misses
system.cpu1.dtb.write_accesses 106267 # DTB write accesses
system.cpu1.dtb.write_acv 68 # DTB write access violations
system.cpu1.dtb.write_hits 1450279 # DTB write hits
system.cpu1.dtb.write_misses 2163 # DTB write misses
system.cpu1.fetch.Branches 3058879 # Number of branches that fetch encountered
system.cpu1.fetch.CacheLines 1688815 # Number of cache lines fetched
system.cpu1.fetch.Cycles 4357354 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.IcacheSquashes 105751 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.Insts 14416907 # Number of instructions fetch has processed
system.cpu1.fetch.MiscStallCycles 179 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.SquashCycles 193553 # Number of cycles fetch has spent squashing
system.cpu1.fetch.branchRate 0.139064 # Number of branch fetches per cycle
system.cpu1.fetch.icacheStallCycles 1688815 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.predictedBranches 1382928 # Number of branches that fetch has predicted taken
system.cpu1.fetch.rate 0.655426 # Number of inst fetches per cycle
system.cpu1.fetch.rateDist::samples 20232629 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 0.712557 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.050166 # Number of instructions fetched each cycle (Total)
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.fetch.rateDist::0 17569535 86.84% 86.84% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 215879 1.07% 87.90% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 322874 1.60% 89.50% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 192834 0.95% 90.45% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 374265 1.85% 92.30% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 129017 0.64% 92.94% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 159403 0.79% 93.73% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 272361 1.35% 95.07% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 996461 4.93% 100.00% # Number of instructions fetched each cycle (Total)
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.fetch.rateDist::total 20232629 # Number of instructions fetched each cycle (Total)
system.cpu1.icache.ReadReq_accesses::0 1688815 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 1688815 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_avg_miss_latency::0 14598.075134 # average ReadReq miss latency
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11541.965319 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_hits::0 1410406 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 1410406 # number of ReadReq hits
system.cpu1.icache.ReadReq_miss_latency 4064235500 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_rate::0 0.164855 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_misses::0 278409 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 278409 # number of ReadReq misses
system.cpu1.icache.ReadReq_mshr_hits 7888 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_miss_latency 3122344000 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.160184 # mshr miss rate for ReadReq accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.icache.ReadReq_mshr_misses 270521 # number of ReadReq MSHR misses
system.cpu1.icache.avg_blocked_cycles::no_mshrs 8125 # average number of cycles each access was blocked
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.icache.avg_refs 5.214764 # Average number of references to valid blocks.
system.cpu1.icache.blocked::no_mshrs 8 # number of cycles access was blocked
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.icache.blocked_cycles::no_mshrs 65000 # number of cycles access was blocked
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu1.icache.cache_copies 0 # number of cache copies performed
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.icache.demand_accesses::0 1688815 # number of demand (read+write) accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.icache.demand_accesses::total 1688815 # number of demand (read+write) accesses
system.cpu1.icache.demand_avg_miss_latency::0 14598.075134 # average overall miss latency
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.icache.demand_avg_mshr_miss_latency 11541.965319 # average overall mshr miss latency
system.cpu1.icache.demand_hits::0 1410406 # number of demand (read+write) hits
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.icache.demand_hits::total 1410406 # number of demand (read+write) hits
system.cpu1.icache.demand_miss_latency 4064235500 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_rate::0 0.164855 # miss rate for demand accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.icache.demand_misses::0 278409 # number of demand (read+write) misses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.icache.demand_misses::total 278409 # number of demand (read+write) misses
system.cpu1.icache.demand_mshr_hits 7888 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_miss_latency 3122344000 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_rate::0 0.160184 # mshr miss rate for demand accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.icache.demand_mshr_misses 270521 # number of demand (read+write) MSHR misses
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.icache.occ_%::0 0.900098 # Average percentage of cache occupancy
system.cpu1.icache.occ_blocks::0 460.849961 # Average occupied blocks per context
system.cpu1.icache.overall_accesses::0 1688815 # number of overall (read+write) accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.icache.overall_accesses::total 1688815 # number of overall (read+write) accesses
system.cpu1.icache.overall_avg_miss_latency::0 14598.075134 # average overall miss latency
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.icache.overall_avg_mshr_miss_latency 11541.965319 # average overall mshr miss latency
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.icache.overall_hits::0 1410406 # number of overall hits
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.icache.overall_hits::1 0 # number of overall hits
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.icache.overall_hits::total 1410406 # number of overall hits
system.cpu1.icache.overall_miss_latency 4064235500 # number of overall miss cycles
system.cpu1.icache.overall_miss_rate::0 0.164855 # miss rate for overall accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.icache.overall_misses::0 278409 # number of overall misses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.icache.overall_misses::1 0 # number of overall misses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.icache.overall_misses::total 278409 # number of overall misses
system.cpu1.icache.overall_mshr_hits 7888 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_miss_latency 3122344000 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_rate::0 0.160184 # mshr miss rate for overall accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.icache.overall_mshr_misses 270521 # number of overall MSHR misses
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.icache.replacements 269955 # number of replacements
system.cpu1.icache.sampled_refs 270464 # Sample count of references to valid blocks.
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.icache.tagsinuse 460.849961 # Cycle average of tags in use
system.cpu1.icache.total_refs 1410406 # Total number of references to valid blocks.
system.cpu1.icache.warmup_cycle 1902950008000 # Cycle when the warmup percentage was hit.
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu1.icache.writebacks 0 # number of writebacks
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.idleCycles 1763601 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.iew.EXEC:branches 1647161 # Number of branches executed
system.cpu1.iew.EXEC:nop 633873 # number of nop insts executed
system.cpu1.iew.EXEC:rate 0.498846 # Inst execution rate
system.cpu1.iew.EXEC:refs 3712298 # number of memory reference insts executed
system.cpu1.iew.EXEC:stores 1459673 # Number of stores executed
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu1.iew.EXEC:swp 0 # number of swp insts executed
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.iew.WB:consumers 6255206 # num instructions consuming a value
system.cpu1.iew.WB:count 10847139 # cumulative count of insts written-back
system.cpu1.iew.WB:fanout 0.739229 # average fanout of values written-back
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.iew.WB:producers 4624029 # num instructions producing a value
system.cpu1.iew.WB:rate 0.493136 # insts written-back per cycle
system.cpu1.iew.WB:sent 10867556 # cumulative count of insts sent to commit
system.cpu1.iew.branchMispredicts 177268 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewBlockCycles 332920 # Number of cycles IEW is blocking
system.cpu1.iew.iewDispLoadInsts 2358529 # Number of dispatched load instructions
system.cpu1.iew.iewDispNonSpecInsts 525453 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewDispSquashedInsts 201798 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispStoreInsts 1538474 # Number of dispatched store instructions
system.cpu1.iew.iewDispatchedInsts 12592629 # Number of instructions dispatched to IQ
system.cpu1.iew.iewExecLoadInsts 2252625 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 104488 # Number of squashed instructions skipped in execute
system.cpu1.iew.iewExecutedInsts 10972727 # Number of executed instructions
system.cpu1.iew.iewIQFullEvents 3148 # Number of times the IQ has become full, causing a stall
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.iew.iewLSQFullEvents 1572 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.iewSquashCycles 311026 # Number of cycles IEW is squashing
system.cpu1.iew.iewUnblockCycles 9766 # Number of cycles IEW is unblocking
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.iew.lsq.thread.0.cacheBlocked 50281 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.lsq.thread.0.forwLoads 68629 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread.0.ignoredResponses 4124 # Number of memory responses ignored because the instruction is squashed
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.iew.lsq.thread.0.memOrderViolation 9401 # Number of memory ordering violations
system.cpu1.iew.lsq.thread.0.rescheduledLoads 371 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread.0.squashedLoads 336957 # Number of loads squashed
system.cpu1.iew.lsq.thread.0.squashedStores 129791 # Number of stores squashed
system.cpu1.iew.memOrderViolationEvents 9401 # Number of memory order violations
system.cpu1.iew.predictedNotTakenIncorrect 104860 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.predictedTakenIncorrect 72408 # Number of branches that were predicted taken incorrectly
system.cpu1.ipc 0.463358 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.463358 # IPC: Total IPC of All Threads
system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 3519 0.03% 0.03% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IntAlu 6926354 62.53% 62.56% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IntMult 18692 0.17% 62.73% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.73% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 11838 0.11% 62.84% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 62.84% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 62.84% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 62.84% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 1759 0.02% 62.85% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 62.85% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::MemRead 2331483 21.05% 83.90% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::MemWrite 1476157 13.33% 97.22% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IprAccess 307413 2.78% 100.00% # Type of FU issued
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.iq.ISSUE:FU_type_0::total 11077215 # Type of FU issued
system.cpu1.iq.ISSUE:fu_busy_cnt 158215 # FU busy when requested
system.cpu1.iq.ISSUE:fu_busy_rate 0.014283 # FU busy rate (busy events/executed inst)
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu1.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.iq.ISSUE:fu_full::IntAlu 4066 2.57% 2.57% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 2.57% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.57% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.57% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.57% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.57% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.57% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.57% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.57% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::MemRead 92866 58.70% 61.27% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::MemWrite 61283 38.73% 100.00% # attempts to use FU when none available
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.iq.ISSUE:issued_per_cycle::samples 20232629 # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.547493 # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.152304 # Number of insts issued each cycle
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.iq.ISSUE:issued_per_cycle::0 14868449 73.49% 73.49% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::1 2672522 13.21% 86.70% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::2 1102181 5.45% 92.14% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::3 699877 3.46% 95.60% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::4 518299 2.56% 98.16% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::5 241576 1.19% 99.36% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::6 93786 0.46% 99.82% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::7 30604 0.15% 99.97% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::8 5335 0.03% 100.00% # Number of insts issued each cycle
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.iq.ISSUE:issued_per_cycle::total 20232629 # Number of insts issued each cycle
system.cpu1.iq.ISSUE:rate 0.503596 # Inst issue rate
system.cpu1.iq.iqInstsAdded 11373839 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqInstsIssued 11077215 # Number of instructions issued
system.cpu1.iq.iqNonSpecInstsAdded 584917 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqSquashedInstsExamined 1698901 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedInstsIssued 10384 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedNonSpecRemoved 412332 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.iqSquashedOperandsExamined 877867 # Number of squashed operands that are examined and possibly removed from graph
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
system.cpu1.itb.data_accesses 0 # DTB accesses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_hits 0 # DTB hits
system.cpu1.itb.data_misses 0 # DTB misses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.itb.fetch_accesses 413824 # ITB accesses
system.cpu1.itb.fetch_acv 100 # ITB acv
system.cpu1.itb.fetch_hits 408478 # ITB hits
system.cpu1.itb.fetch_misses 5346 # ITB misses
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.write_acv 0 # DTB write access violations
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.kern.callpal::wripir 300 0.50% 0.50% # number of callpals executed
system.cpu1.kern.callpal::wrmces 1 0.00% 0.50% # number of callpals executed
system.cpu1.kern.callpal::wrfen 1 0.00% 0.50% # number of callpals executed
system.cpu1.kern.callpal::swpctx 1497 2.49% 3.00% # number of callpals executed
system.cpu1.kern.callpal::tbi 3 0.00% 3.00% # number of callpals executed
system.cpu1.kern.callpal::wrent 7 0.01% 3.02% # number of callpals executed
system.cpu1.kern.callpal::swpipl 52375 87.24% 90.26% # number of callpals executed
system.cpu1.kern.callpal::rdps 2373 3.95% 94.21% # number of callpals executed
system.cpu1.kern.callpal::wrkgp 1 0.00% 94.21% # number of callpals executed
system.cpu1.kern.callpal::wrusp 4 0.01% 94.22% # number of callpals executed
system.cpu1.kern.callpal::whami 3 0.00% 94.22% # number of callpals executed
system.cpu1.kern.callpal::rti 3300 5.50% 99.72% # number of callpals executed
system.cpu1.kern.callpal::callsys 124 0.21% 99.93% # number of callpals executed
system.cpu1.kern.callpal::imb 42 0.07% 100.00% # number of callpals executed
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.kern.callpal::total 60033 # number of callpals executed
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.kern.inst.hwrei 66427 # number of hwrei instructions executed
system.cpu1.kern.inst.quiesce 2553 # number of quiesce instructions executed
system.cpu1.kern.ipl_count::0 21855 37.68% 37.68% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22 1927 3.32% 41.01% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30 393 0.68% 41.68% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31 33821 58.32% 100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total 57996 # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0 21257 47.83% 47.83% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22 1927 4.34% 52.17% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30 393 0.88% 53.05% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31 20864 46.95% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total 44441 # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0 1874788065000 98.35% 98.35% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22 349524500 0.02% 98.37% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30 166729500 0.01% 98.38% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31 30954744500 1.62% 100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total 1906259063500 # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0 0.972638 # fraction of swpipl calls that actually changed the ipl
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.kern.ipl_used::31 0.616895 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.mode_good::kernel 700
system.cpu1.kern.mode_good::user 383
system.cpu1.kern.mode_good::idle 317
system.cpu1.kern.mode_switch::kernel 1588 # number of protection mode switches
system.cpu1.kern.mode_switch::user 383 # number of protection mode switches
system.cpu1.kern.mode_switch::idle 2627 # number of protection mode switches
system.cpu1.kern.mode_switch_good::kernel 0.440806 # fraction of useful protection mode switches
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.cpu1.kern.mode_switch_good::idle 0.120670 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total 1.561476 # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel 7544739000 0.40% 0.40% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user 853569500 0.04% 0.44% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 1897425262500 99.56% 100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context 1498 # number of times the context was actually changed
system.cpu1.kern.syscall::3 10 10.64% 10.64% # number of syscalls executed
system.cpu1.kern.syscall::6 9 9.57% 20.21% # number of syscalls executed
system.cpu1.kern.syscall::15 1 1.06% 21.28% # number of syscalls executed
system.cpu1.kern.syscall::17 6 6.38% 27.66% # number of syscalls executed
system.cpu1.kern.syscall::23 3 3.19% 30.85% # number of syscalls executed
system.cpu1.kern.syscall::24 3 3.19% 34.04% # number of syscalls executed
system.cpu1.kern.syscall::33 4 4.26% 38.30% # number of syscalls executed
system.cpu1.kern.syscall::45 15 15.96% 54.26% # number of syscalls executed
system.cpu1.kern.syscall::47 3 3.19% 57.45% # number of syscalls executed
system.cpu1.kern.syscall::59 1 1.06% 58.51% # number of syscalls executed
system.cpu1.kern.syscall::71 27 28.72% 87.23% # number of syscalls executed
system.cpu1.kern.syscall::74 9 9.57% 96.81% # number of syscalls executed
system.cpu1.kern.syscall::132 3 3.19% 100.00% # number of syscalls executed
system.cpu1.kern.syscall::total 94 # number of syscalls executed
system.cpu1.memDep0.conflictingLoads 510972 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 447437 # Number of conflicting stores.
system.cpu1.memDep0.insertedLoads 2358529 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 1538474 # Number of stores inserted to the mem dependence unit.
system.cpu1.numCycles 21996230 # number of cpu cycles simulated
system.cpu1.rename.RENAME:BlockCycles 659886 # Number of cycles rename is blocking
system.cpu1.rename.RENAME:CommittedMaps 7238905 # Number of HB maps that are committed
system.cpu1.rename.RENAME:IQFullEvents 29431 # Number of times rename has blocked due to IQ full
system.cpu1.rename.RENAME:IdleCycles 8848928 # Number of cycles rename is idle
system.cpu1.rename.RENAME:LSQFullEvents 376341 # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RENAME:ROBFullEvents 2702 # Number of times rename has blocked due to ROB full
system.cpu1.rename.RENAME:RenameLookups 15628999 # Number of register rename lookups that rename has made
system.cpu1.rename.RENAME:RenamedInsts 13115251 # Number of instructions processed by rename
system.cpu1.rename.RENAME:RenamedOperands 8582665 # Number of destination operands rename has renamed
system.cpu1.rename.RENAME:RunCycles 2365502 # Number of cycles rename is running
system.cpu1.rename.RENAME:SquashCycles 311026 # Number of cycles rename is squashing
system.cpu1.rename.RENAME:UnblockCycles 913464 # Number of cycles rename is unblocking
system.cpu1.rename.RENAME:UndoneMaps 1343760 # Number of HB maps that are undone due to squashing
system.cpu1.rename.RENAME:serializeStallCycles 7133821 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RENAME:serializingInsts 521569 # count of serializing insts renamed
system.cpu1.rename.RENAME:skidInsts 2485864 # count of insts added to the skid buffer
system.cpu1.rename.RENAME:tempSerializingInsts 55479 # count of temporary serializing insts renamed
system.cpu1.timesIdled 207727 # Number of times that the entire CPU went into an idle state and unscheduled itself
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.iocache.ReadReq_accesses::1 172 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 172 # number of ReadReq accesses(hits+misses)
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.iocache.ReadReq_avg_miss_latency::1 115273.244186 # average ReadReq miss latency
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.iocache.ReadReq_avg_mshr_miss_latency 63273.244186 # average ReadReq mshr miss latency
system.iocache.ReadReq_miss_latency 19826998 # number of ReadReq miss cycles
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.iocache.ReadReq_misses::1 172 # number of ReadReq misses
system.iocache.ReadReq_misses::total 172 # number of ReadReq misses
system.iocache.ReadReq_mshr_miss_latency 10882998 # number of ReadReq MSHR miss cycles
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.iocache.ReadReq_mshr_misses 172 # number of ReadReq MSHR misses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.iocache.WriteReq_avg_miss_latency::1 137834.973190 # average WriteReq miss latency
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.iocache.WriteReq_avg_mshr_miss_latency 85831.529120 # average WriteReq mshr miss latency
system.iocache.WriteReq_miss_latency 5727318806 # number of WriteReq miss cycles
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.iocache.WriteReq_mshr_miss_latency 3566471698 # number of WriteReq MSHR miss cycles
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.iocache.avg_blocked_cycles::no_mshrs 6167.680658 # average number of cycles each access was blocked
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.iocache.avg_refs 0 # Average number of references to valid blocks.
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.iocache.blocked::no_mshrs 10459 # number of cycles access was blocked
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.iocache.blocked_cycles::no_mshrs 64507772 # number of cycles access was blocked
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.iocache.cache_copies 0 # number of cache copies performed
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.iocache.demand_accesses::1 41724 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 41724 # number of demand (read+write) accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.iocache.demand_avg_miss_latency::1 137741.966350 # average overall miss latency
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.iocache.demand_avg_miss_latency::total inf # average overall miss latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.iocache.demand_avg_mshr_miss_latency 85738.536478 # average overall mshr miss latency
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.iocache.demand_hits::0 0 # number of demand (read+write) hits
system.iocache.demand_hits::1 0 # number of demand (read+write) hits
system.iocache.demand_hits::total 0 # number of demand (read+write) hits
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.iocache.demand_miss_latency 5747145804 # number of demand (read+write) miss cycles
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
system.iocache.demand_misses::0 0 # number of demand (read+write) misses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.iocache.demand_misses::1 41724 # number of demand (read+write) misses
system.iocache.demand_misses::total 41724 # number of demand (read+write) misses
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.iocache.demand_mshr_miss_latency 3577354696 # number of demand (read+write) MSHR miss cycles
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.iocache.demand_mshr_misses 41724 # number of demand (read+write) MSHR misses
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.iocache.occ_%::1 0.029720 # Average percentage of cache occupancy
system.iocache.occ_blocks::1 0.475524 # Average occupied blocks per context
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.iocache.overall_accesses::1 41724 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 41724 # number of overall (read+write) accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.iocache.overall_avg_miss_latency::1 137741.966350 # average overall miss latency
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.iocache.overall_avg_miss_latency::total inf # average overall miss latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.iocache.overall_avg_mshr_miss_latency 85738.536478 # average overall mshr miss latency
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.iocache.overall_hits::0 0 # number of overall hits
system.iocache.overall_hits::1 0 # number of overall hits
system.iocache.overall_hits::total 0 # number of overall hits
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.iocache.overall_miss_latency 5747145804 # number of overall miss cycles
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
system.iocache.overall_misses::0 0 # number of overall misses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.iocache.overall_misses::1 41724 # number of overall misses
system.iocache.overall_misses::total 41724 # number of overall misses
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.iocache.overall_mshr_miss_latency 3577354696 # number of overall MSHR miss cycles
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.iocache.overall_mshr_misses 41724 # number of overall MSHR misses
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.iocache.replacements 41692 # number of replacements
system.iocache.sampled_refs 41708 # Sample count of references to valid blocks.
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.iocache.tagsinuse 0.475524 # Cycle average of tags in use
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.iocache.total_refs 0 # Total number of references to valid blocks.
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.iocache.warmup_cycle 1715203940000 # Cycle when the warmup percentage was hit.
ALPHA: The previous O3 patch causes a slight stats change with fullsys.
2010-08-23 18:18:42 +02:00
system.iocache.writebacks 41520 # number of writebacks
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.l2c.ReadExReq_accesses::0 257631 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::1 41153 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 298784 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_avg_miss_latency::0 60735.824013 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::1 380275.607871 # average ReadExReq miss latency
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.l2c.ReadExReq_avg_mshr_miss_latency 40207.175331 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_hits::0 1663 # number of ReadExReq hits
system.l2c.ReadExReq_hits::1 271 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 1934 # number of ReadExReq hits
system.l2c.ReadExReq_miss_latency 15546427401 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_rate::0 0.993545 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::1 0.993415 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses::0 255968 # number of ReadExReq misses
system.l2c.ReadExReq_misses::1 40882 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 296850 # number of ReadExReq misses
system.l2c.ReadExReq_mshr_miss_latency 11935499997 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_rate::0 1.152229 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1 7.213326 # mshr miss rate for ReadExReq accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.l2c.ReadExReq_mshr_misses 296850 # number of ReadExReq MSHR misses
system.l2c.ReadReq_accesses::0 1795093 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::1 360112 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2155205 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_avg_miss_latency::0 52872.781104 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::1 3365794.496366 # average ReadReq miss latency
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.l2c.ReadReq_avg_mshr_miss_latency 40019.494912 # average ReadReq mshr miss latency
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.l2c.ReadReq_hits::0 1488578 # number of ReadReq hits
system.l2c.ReadReq_hits::1 355297 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1843875 # number of ReadReq hits
system.l2c.ReadReq_miss_latency 16206300500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_rate::0 0.170752 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::1 0.013371 # miss rate for ReadReq accesses
system.l2c.ReadReq_misses::0 306515 # number of ReadReq misses
system.l2c.ReadReq_misses::1 4815 # number of ReadReq misses
system.l2c.ReadReq_misses::total 311330 # number of ReadReq misses
ALPHA: The previous O3 patch causes a slight stats change with fullsys.
2010-08-23 18:18:42 +02:00
system.l2c.ReadReq_mshr_hits 18 # number of ReadReq MSHR hits
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.l2c.ReadReq_mshr_miss_latency 12458549000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate::0 0.173424 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::1 0.864487 # mshr miss rate for ReadReq accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.l2c.ReadReq_mshr_misses 311312 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_uncacheable_latency 840831000 # number of ReadReq MSHR uncacheable cycles
system.l2c.SCUpgradeReq_accesses::0 14188 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::1 5331 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 19519 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_avg_miss_latency::0 67372.602257 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::1 179272.565209 # average SCUpgradeReq miss latency
stats: update stats for SC protocol change Some subset of UpgradeReq messages shifted to the new SCUpgradeReq type. Other than that there are no significant differences.
2010-06-17 00:25:57 +02:00
system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40011.251217 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_hits::0 8 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::1 2 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_miss_latency 955343500 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_rate::0 0.999436 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::1 0.999625 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_misses::0 14180 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::1 5329 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 19509 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_mshr_miss_latency 780579500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.375035 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::1 3.659539 # mshr miss rate for SCUpgradeReq accesses
stats: update stats for SC protocol change Some subset of UpgradeReq messages shifted to the new SCUpgradeReq type. Other than that there are no significant differences.
2010-06-17 00:25:57 +02:00
system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.l2c.SCUpgradeReq_mshr_misses 19509 # number of SCUpgradeReq MSHR misses
system.l2c.UpgradeReq_accesses::0 55251 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::1 16863 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 72114 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_avg_miss_latency::0 64253.326605 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::1 210525.121307 # average UpgradeReq miss latency
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.l2c.UpgradeReq_avg_mshr_miss_latency 40021.687237 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_hits::0 16 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::1 5 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 21 # number of UpgradeReq hits
system.l2c.UpgradeReq_miss_latency 3549032495 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_rate::0 0.999710 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::1 0.999703 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_misses::0 55235 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::1 16858 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 72093 # number of UpgradeReq misses
system.l2c.UpgradeReq_mshr_miss_latency 2885283498 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_rate::0 1.304827 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::1 4.275218 # mshr miss rate for UpgradeReq accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.l2c.UpgradeReq_mshr_misses 72093 # number of UpgradeReq MSHR misses
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.l2c.WriteReq_mshr_uncacheable_latency 1554057498 # number of WriteReq MSHR uncacheable cycles
system.l2c.Writeback_accesses::0 446200 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 446200 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_hits::0 446200 # number of Writeback hits
system.l2c.Writeback_hits::total 446200 # number of Writeback hits
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.l2c.avg_refs 4.752489 # Average number of references to valid blocks.
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.l2c.cache_copies 0 # number of cache copies performed
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.l2c.demand_accesses::0 2052724 # number of demand (read+write) accesses
system.l2c.demand_accesses::1 401265 # number of demand (read+write) accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.l2c.demand_accesses::total 2453989 # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency::0 56451.000121 # average overall miss latency
system.l2c.demand_avg_miss_latency::1 694853.664376 # average overall miss latency
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency
system.l2c.demand_avg_miss_latency::total inf # average overall miss latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.l2c.demand_avg_mshr_miss_latency 40111.103615 # average overall mshr miss latency
system.l2c.demand_hits::0 1490241 # number of demand (read+write) hits
system.l2c.demand_hits::1 355568 # number of demand (read+write) hits
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.l2c.demand_hits::2 0 # number of demand (read+write) hits
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.l2c.demand_hits::total 1845809 # number of demand (read+write) hits
system.l2c.demand_miss_latency 31752727901 # number of demand (read+write) miss cycles
system.l2c.demand_miss_rate::0 0.274018 # miss rate for demand accesses
system.l2c.demand_miss_rate::1 0.113882 # miss rate for demand accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses
system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.l2c.demand_misses::0 562483 # number of demand (read+write) misses
system.l2c.demand_misses::1 45697 # number of demand (read+write) misses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.l2c.demand_misses::2 0 # number of demand (read+write) misses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.l2c.demand_misses::total 608180 # number of demand (read+write) misses
ALPHA: The previous O3 patch causes a slight stats change with fullsys.
2010-08-23 18:18:42 +02:00
system.l2c.demand_mshr_hits 18 # number of demand (read+write) MSHR hits
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.l2c.demand_mshr_miss_latency 24394048997 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate::0 0.296271 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1 1.515612 # mshr miss rate for demand accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.l2c.demand_mshr_misses 608162 # number of demand (read+write) MSHR misses
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.l2c.occ_%::0 0.174396 # Average percentage of cache occupancy
system.l2c.occ_%::1 0.005052 # Average percentage of cache occupancy
system.l2c.occ_%::2 0.332288 # Average percentage of cache occupancy
system.l2c.occ_blocks::0 11429.229058 # Average occupied blocks per context
system.l2c.occ_blocks::1 331.081192 # Average occupied blocks per context
system.l2c.occ_blocks::2 21776.825321 # Average occupied blocks per context
system.l2c.overall_accesses::0 2052724 # number of overall (read+write) accesses
system.l2c.overall_accesses::1 401265 # number of overall (read+write) accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.l2c.overall_accesses::total 2453989 # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency::0 56451.000121 # average overall miss latency
system.l2c.overall_avg_miss_latency::1 694853.664376 # average overall miss latency
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency
system.l2c.overall_avg_miss_latency::total inf # average overall miss latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.l2c.overall_avg_mshr_miss_latency 40111.103615 # average overall mshr miss latency
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.l2c.overall_hits::0 1490241 # number of overall hits
system.l2c.overall_hits::1 355568 # number of overall hits
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.l2c.overall_hits::2 0 # number of overall hits
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.l2c.overall_hits::total 1845809 # number of overall hits
system.l2c.overall_miss_latency 31752727901 # number of overall miss cycles
system.l2c.overall_miss_rate::0 0.274018 # miss rate for overall accesses
system.l2c.overall_miss_rate::1 0.113882 # miss rate for overall accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses
system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.l2c.overall_misses::0 562483 # number of overall misses
system.l2c.overall_misses::1 45697 # number of overall misses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.l2c.overall_misses::2 0 # number of overall misses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.l2c.overall_misses::total 608180 # number of overall misses
ALPHA: The previous O3 patch causes a slight stats change with fullsys.
2010-08-23 18:18:42 +02:00
system.l2c.overall_mshr_hits 18 # number of overall MSHR hits
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.l2c.overall_mshr_miss_latency 24394048997 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate::0 0.296271 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1 1.515612 # mshr miss rate for overall accesses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.l2c.overall_mshr_misses 608162 # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency 2394888498 # number of overall MSHR uncacheable cycles
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.l2c.replacements 399060 # number of replacements
system.l2c.sampled_refs 435274 # Sample count of references to valid blocks.
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
system.l2c.tagsinuse 33537.135570 # Cycle average of tags in use
system.l2c.total_refs 2068635 # Total number of references to valid blocks.
system.l2c.warmup_cycle 9277782000 # Cycle when the warmup percentage was hit.
system.l2c.writebacks 122307 # number of writebacks
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post
system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post
system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post
system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post
Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
2008-10-21 01:00:07 +02:00
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink