gem5/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
host_inst_rate                                 136464                       # Simulator instruction rate (inst/s)
host_mem_usage                                 294032                       # Number of bytes of host memory used
host_seconds                                   417.62                       # Real time elapsed on the host
host_tick_rate                             4551611662                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                    56990237                       # Number of instructions simulated
sim_seconds                                  1.900844                       # Number of seconds simulated
sim_ticks                                1900844230500                       # Number of ticks simulated
system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.BTBHits                 5873671                       # Number of BTB hits
system.cpu0.BPredUnit.BTBLookups             11166529                       # Number of BTB lookups
system.cpu0.BPredUnit.RASInCorrect              27790                       # Number of incorrect RAS predictions.
system.cpu0.BPredUnit.condIncorrect            685267                       # Number of conditional branches incorrect
system.cpu0.BPredUnit.condPredicted          10432996                       # Number of conditional branches predicted
system.cpu0.BPredUnit.lookups                12491450                       # Number of BP lookups
system.cpu0.BPredUnit.usedRAS                  879904                       # Number of times the RAS was used to get a target.
system.cpu0.commit.COM:branches               7524834                       # Number of branches committed
system.cpu0.commit.COM:bw_lim_events           923111                       # number cycles where commit BW limit reached
system.cpu0.commit.COM:bw_limited                   0                       # number of insts not committed due to BW limits
system.cpu0.commit.COM:committed_per_cycle::samples     78256773                       # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::mean     0.636207                       # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::stdev     1.403151                       # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::0     56995845     72.83%     72.83% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::1      9310416     11.90%     84.73% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::2      5430205      6.94%     91.67% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::3      2440245      3.12%     94.79% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::4      1860572      2.38%     97.16% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::5       630930      0.81%     97.97% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::6       344016      0.44%     98.41% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::7       321433      0.41%     98.82% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::8       923111      1.18%    100.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::total     78256773                       # Number of insts commited each cycle
system.cpu0.commit.COM:count                 49787514                       # Number of instructions committed
system.cpu0.commit.COM:loads                  7895784                       # Number of loads committed
system.cpu0.commit.COM:membars                 191655                       # Number of memory barriers committed
system.cpu0.commit.COM:refs                  13320151                       # Number of memory references committed
system.cpu0.commit.COM:swp_count                    0                       # Number of s/w prefetches committed
system.cpu0.commit.branchMispredicts           652659                       # The number of times a branch was mispredicted
system.cpu0.commit.commitCommittedInsts      49787514                       # The number of committed instructions
system.cpu0.commit.commitNonSpecStalls         564772                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.commitSquashedInsts        7271893                       # The number of squashed insts skipped by commit
system.cpu0.committedInsts                   46926700                       # Number of Instructions Simulated
system.cpu0.committedInsts_total             46926700                       # Number of Instructions Simulated
system.cpu0.cpi                              2.403270                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        2.403270                       # CPI: Total CPI of All Threads
system.cpu0.dcache.LoadLockedReq_accesses::0       178277                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       178277                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14385.010585                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10557.129525                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_hits::0       158910                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       158910                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_miss_latency    278594500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_rate::0     0.108634                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_misses::0        19367                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        19367                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_mshr_hits         4366                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency    158367500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0     0.084144                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_misses        15001                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.ReadReq_accesses::0        8018710                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total      8018710                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_avg_miss_latency::0 23752.163525                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23766.972926                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_hits::0            6640866                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total        6640866                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_miss_latency   32726776000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_rate::0      0.171829                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_misses::0          1377844                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      1377844                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_mshr_hits           392731                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_miss_latency  23413154000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::0     0.122852                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_misses         985113                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency    920830500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_accesses::0       185114                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       185114                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 13300.547196                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 10297.264022                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_hits::0        181459                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       181459                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_miss_latency     48613500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_rate::0     0.019745                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_misses::0         3655                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total         3655                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_mshr_miss_latency     37636500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0     0.019745                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_misses         3655                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.WriteReq_accesses::0       5224193                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total      5224193                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_avg_miss_latency::0 32390.296487                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 30580.318877                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_hits::0           3607335                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total       3607335                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_miss_latency  52370509997                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_rate::0     0.309494                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_misses::0         1616858                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1616858                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_mshr_hits         1353465                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_miss_latency   8054641930                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_rate::0     0.050418                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_misses        263393                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency   1320665498                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.avg_blocked_cycles::no_mshrs  8775.921635                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets        21500                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_refs                  8.499931                       # Average number of references to valid blocks.
system.cpu0.dcache.blocked::no_mshrs            83634                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              7                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_mshrs    733965430                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets       150500                       # number of cycles access was blocked
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.demand_accesses::0        13242903                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     13242903                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_avg_miss_latency::0 28415.944557                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency 25204.360996                       # average overall mshr miss latency
system.cpu0.dcache.demand_hits::0            10248201                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        10248201                       # number of demand (read+write) hits
system.cpu0.dcache.demand_miss_latency    85097285997                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_rate::0       0.226136                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu0.dcache.demand_misses::0           2994702                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       2994702                       # number of demand (read+write) misses
system.cpu0.dcache.demand_mshr_hits           1746196                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_miss_latency  31467795930                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_rate::0     0.094277                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_misses         1248506                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.occ_%::0                  0.973616                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_%::1                 -0.001953                       # Average percentage of cache occupancy
system.cpu0.dcache.occ_blocks::0           498.491480                       # Average occupied blocks per context
system.cpu0.dcache.occ_blocks::1            -1.000000                       # Average occupied blocks per context
system.cpu0.dcache.overall_accesses::0       13242903                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     13242903                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_avg_miss_latency::0 28415.944557                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency 25204.360996                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_hits::0           10248201                       # number of overall hits
system.cpu0.dcache.overall_hits::1                  0                       # number of overall hits
system.cpu0.dcache.overall_hits::total       10248201                       # number of overall hits
system.cpu0.dcache.overall_miss_latency   85097285997                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_rate::0      0.226136                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu0.dcache.overall_misses::0          2994702                       # number of overall misses
system.cpu0.dcache.overall_misses::1                0                       # number of overall misses
system.cpu0.dcache.overall_misses::total      2994702                       # number of overall misses
system.cpu0.dcache.overall_mshr_hits          1746196                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_miss_latency  31467795930                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_rate::0     0.094277                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_misses        1248506                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_uncacheable_latency   2241495998                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.replacements               1246705                       # number of replacements
system.cpu0.dcache.sampled_refs               1247217                       # Sample count of references to valid blocks.
system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.dcache.tagsinuse               497.491481                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                10601259                       # Total number of references to valid blocks.
system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.writebacks                  721554                       # number of writebacks
system.cpu0.decode.DECODE:BlockedCycles      33796856                       # Number of cycles decode is blocked
system.cpu0.decode.DECODE:BranchMispred         33338                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DECODE:BranchResolved       520908                       # Number of times decode resolved a branch
system.cpu0.decode.DECODE:DecodedInsts       62600964                       # Number of instructions handled by decode
system.cpu0.decode.DECODE:IdleCycles         32174872                       # Number of cycles decode is idle
system.cpu0.decode.DECODE:RunCycles          11303760                       # Number of cycles decode is running
system.cpu0.decode.DECODE:SquashCycles        1270160                       # Number of cycles decode is squashing
system.cpu0.decode.DECODE:SquashedInsts        100637                       # Number of squashed instructions handled by decode
system.cpu0.decode.DECODE:UnblockCycles        981284                       # Number of cycles decode is unblocking
system.cpu0.dtb.data_accesses                  794683                       # DTB accesses
system.cpu0.dtb.data_acv                          699                       # DTB access violations
system.cpu0.dtb.data_hits                    14241389                       # DTB hits
system.cpu0.dtb.data_misses                     32519                       # DTB misses
system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu0.dtb.fetch_acv                           0                       # ITB acv
system.cpu0.dtb.fetch_hits                          0                       # ITB hits
system.cpu0.dtb.fetch_misses                        0                       # ITB misses
system.cpu0.dtb.read_accesses                  599310                       # DTB read accesses
system.cpu0.dtb.read_acv                          523                       # DTB read access violations
system.cpu0.dtb.read_hits                     8657125                       # DTB read hits
system.cpu0.dtb.read_misses                     26727                       # DTB read misses
system.cpu0.dtb.write_accesses                 195373                       # DTB write accesses
system.cpu0.dtb.write_acv                         176                       # DTB write access violations
system.cpu0.dtb.write_hits                    5584264                       # DTB write hits
system.cpu0.dtb.write_misses                     5792                       # DTB write misses
system.cpu0.fetch.Branches                   12491450                       # Number of branches that fetch encountered
system.cpu0.fetch.CacheLines                  7791215                       # Number of cache lines fetched
system.cpu0.fetch.Cycles                     20268333                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.IcacheSquashes               374565                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.Insts                      63688508                       # Number of instructions fetch has processed
system.cpu0.fetch.MiscStallCycles                1103                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.SquashCycles                 745343                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.branchRate                 0.110762                       # Number of branch fetches per cycle
system.cpu0.fetch.icacheStallCycles           7791215                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.predictedBranches           6753575                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.rate                       0.564727                       # Number of inst fetches per cycle
system.cpu0.fetch.rateDist::samples          79526933                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.800842                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            2.104211                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0                67079407     84.35%     84.35% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1                  896436      1.13%     85.48% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                 1772079      2.23%     87.70% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3                  811632      1.02%     88.72% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4                 2745328      3.45%     92.18% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5                  585266      0.74%     92.91% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6                  679619      0.85%     93.77% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7                  829666      1.04%     94.81% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8                 4127500      5.19%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total            79526933                       # Number of instructions fetched each cycle (Total)
system.cpu0.icache.ReadReq_accesses::0        7791215                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total      7791215                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_avg_miss_latency::0 15067.927393                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12017.913224                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_hits::0            6933667                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total        6933667                       # number of ReadReq hits
system.cpu0.icache.ReadReq_miss_latency   12921471000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_rate::0      0.110066                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_misses::0           857548                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total       857548                       # number of ReadReq misses
system.cpu0.icache.ReadReq_mshr_hits            36674                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_miss_latency   9865192500                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::0     0.105359                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_misses         820874                       # number of ReadReq MSHR misses
system.cpu0.icache.avg_blocked_cycles::no_mshrs 12107.843137                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu0.icache.avg_refs                  8.447903                       # Average number of references to valid blocks.
system.cpu0.icache.blocked::no_mshrs               51                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_mshrs       617500                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.demand_accesses::0         7791215                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total      7791215                       # number of demand (read+write) accesses
system.cpu0.icache.demand_avg_miss_latency::0 15067.927393                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency 12017.913224                       # average overall mshr miss latency
system.cpu0.icache.demand_hits::0             6933667                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total         6933667                       # number of demand (read+write) hits
system.cpu0.icache.demand_miss_latency    12921471000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_rate::0       0.110066                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu0.icache.demand_misses::0            857548                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total        857548                       # number of demand (read+write) misses
system.cpu0.icache.demand_mshr_hits             36674                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_miss_latency   9865192500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_rate::0     0.105359                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_misses          820874                       # number of demand (read+write) MSHR misses
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.occ_%::0                  0.995823                       # Average percentage of cache occupancy
system.cpu0.icache.occ_blocks::0           509.861243                       # Average occupied blocks per context
system.cpu0.icache.overall_accesses::0        7791215                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total      7791215                       # number of overall (read+write) accesses
system.cpu0.icache.overall_avg_miss_latency::0 15067.927393                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency 12017.913224                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_hits::0            6933667                       # number of overall hits
system.cpu0.icache.overall_hits::1                  0                       # number of overall hits
system.cpu0.icache.overall_hits::total        6933667                       # number of overall hits
system.cpu0.icache.overall_miss_latency   12921471000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_rate::0      0.110066                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu0.icache.overall_misses::0           857548                       # number of overall misses
system.cpu0.icache.overall_misses::1                0                       # number of overall misses
system.cpu0.icache.overall_misses::total       857548                       # number of overall misses
system.cpu0.icache.overall_mshr_hits            36674                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_miss_latency   9865192500                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_rate::0     0.105359                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_misses         820874                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.icache.replacements                820245                       # number of replacements
system.cpu0.icache.sampled_refs                820756                       # Sample count of references to valid blocks.
system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.icache.tagsinuse               509.861243                       # Cycle average of tags in use
system.cpu0.icache.total_refs                 6933667                       # Total number of references to valid blocks.
system.cpu0.icache.warmup_cycle           24435382000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.writebacks                     109                       # number of writebacks
system.cpu0.idleCycles                       33250612                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.iew.EXEC:branches                 8091553                       # Number of branches executed
system.cpu0.iew.EXEC:nop                      3189610                       # number of nop insts executed
system.cpu0.iew.EXEC:rate                    0.446670                       # Inst execution rate
system.cpu0.iew.EXEC:refs                    14308443                       # number of memory reference insts executed
system.cpu0.iew.EXEC:stores                   5602810                       # Number of stores executed
system.cpu0.iew.EXEC:swp                            0                       # number of swp insts executed
system.cpu0.iew.WB:consumers                 31619553                       # num instructions consuming a value
system.cpu0.iew.WB:count                     49998381                       # cumulative count of insts written-back
system.cpu0.iew.WB:fanout                    0.757763                       # average fanout of values written-back
system.cpu0.iew.WB:penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu0.iew.WB:penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.iew.WB:producers                 23960113                       # num instructions producing a value
system.cpu0.iew.WB:rate                      0.443336                       # insts written-back per cycle
system.cpu0.iew.WB:sent                      50080785                       # cumulative count of insts sent to commit
system.cpu0.iew.branchMispredicts              711622                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewBlockCycles                9015836                       # Number of cycles IEW is blocking
system.cpu0.iew.iewDispLoadInsts              9134167                       # Number of dispatched load instructions
system.cpu0.iew.iewDispNonSpecInsts           1511990                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewDispSquashedInsts           755493                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispStoreInsts             5841972                       # Number of dispatched store instructions
system.cpu0.iew.iewDispatchedInsts           57170075                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewExecLoadInsts              8705633                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts           463276                       # Number of squashed instructions skipped in execute
system.cpu0.iew.iewExecutedInsts             50374391                       # Number of executed instructions
system.cpu0.iew.iewIQFullEvents                 59438                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewLSQFullEvents                 6976                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.iewSquashCycles               1270160                       # Number of cycles IEW is squashing
system.cpu0.iew.iewUnblockCycles               547257                       # Number of cycles IEW is unblocking
system.cpu0.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread.0.cacheBlocked       121631                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.lsq.thread.0.forwLoads         411302                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread.0.ignoredResponses        10774                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread.0.memOrderViolation        38966                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread.0.rescheduledLoads        18610                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread.0.squashedLoads      1238383                       # Number of loads squashed
system.cpu0.iew.lsq.thread.0.squashedStores       417605                       # Number of stores squashed
system.cpu0.iew.memOrderViolationEvents         38966                       # Number of memory order violations
system.cpu0.iew.predictedNotTakenIncorrect       331944                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.predictedTakenIncorrect        379678                       # Number of branches that were predicted taken incorrectly
system.cpu0.ipc                              0.416100                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.416100                       # IPC: Total IPC of All Threads
system.cpu0.iq.ISSUE:FU_type_0::No_OpClass         3762      0.01%      0.01% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IntAlu       35331602     69.50%     69.51% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IntMult         55961      0.11%     69.62% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IntDiv              0      0.00%     69.62% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatAdd        15323      0.03%     69.65% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatCmp            0      0.00%     69.65% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatCvt            0      0.00%     69.65% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     69.65% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatDiv         1880      0.00%     69.65% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     69.65% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdAdd             0      0.00%     69.65% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     69.65% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdAlu             0      0.00%     69.65% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdCmp             0      0.00%     69.65% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdCvt             0      0.00%     69.65% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdMisc            0      0.00%     69.65% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdMult            0      0.00%     69.65% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     69.65% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     69.65% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     69.65% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdSqrt            0      0.00%     69.65% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     69.65% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     69.65% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     69.65% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     69.65% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     69.65% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     69.65% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     69.65% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     69.65% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     69.65% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::MemRead       9004352     17.71%     87.36% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::MemWrite      5645593     11.11%     98.47% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IprAccess       779196      1.53%    100.00% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::total        50837669                       # Type of FU issued
system.cpu0.iq.ISSUE:fu_busy_cnt               379948                       # FU busy when requested
system.cpu0.iq.ISSUE:fu_busy_rate            0.007474                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.ISSUE:fu_full::No_OpClass            0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IntAlu            41291     10.87%     10.87% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IntMult               0      0.00%     10.87% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IntDiv                0      0.00%     10.87% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatAdd              0      0.00%     10.87% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatCmp              0      0.00%     10.87% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatCvt              0      0.00%     10.87% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatMult             0      0.00%     10.87% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatDiv              0      0.00%     10.87% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatSqrt             0      0.00%     10.87% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdAdd               0      0.00%     10.87% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdAddAcc            0      0.00%     10.87% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdAlu               0      0.00%     10.87% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdCmp               0      0.00%     10.87% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdCvt               0      0.00%     10.87% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdMisc              0      0.00%     10.87% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdMult              0      0.00%     10.87% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%     10.87% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdShift             0      0.00%     10.87% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%     10.87% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdSqrt              0      0.00%     10.87% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%     10.87% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%     10.87% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%     10.87% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%     10.87% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%     10.87% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%     10.87% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%     10.87% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%     10.87% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%     10.87% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::MemRead          225058     59.23%     70.10% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::MemWrite         113599     29.90%    100.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IprAccess             0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:issued_per_cycle::samples     79526933                       # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::mean     0.639251                       # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::stdev     1.210486                       # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::0     54768546     68.87%     68.87% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::1     12090793     15.20%     84.07% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::2      5440746      6.84%     90.91% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::3      3421929      4.30%     95.22% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::4      2219727      2.79%     98.01% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::5       991235      1.25%     99.25% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::6       436578      0.55%     99.80% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::7       113986      0.14%     99.95% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::8        43393      0.05%    100.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::total     79526933                       # Number of insts issued each cycle
system.cpu0.iq.ISSUE:rate                    0.450778                       # Inst issue rate
system.cpu0.iq.iqInstsAdded                  52258300                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqInstsIssued                 50837669                       # Number of instructions issued
system.cpu0.iq.iqNonSpecInstsAdded            1722165                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqSquashedInstsExamined        6733244                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedInstsIssued            24149                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedNonSpecRemoved       1157393                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.iqSquashedOperandsExamined      3421850                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.itb.data_accesses                       0                       # DTB accesses
system.cpu0.itb.data_acv                            0                       # DTB access violations
system.cpu0.itb.data_hits                           0                       # DTB hits
system.cpu0.itb.data_misses                         0                       # DTB misses
system.cpu0.itb.fetch_accesses                 951504                       # ITB accesses
system.cpu0.itb.fetch_acv                         721                       # ITB acv
system.cpu0.itb.fetch_hits                     922631                       # ITB hits
system.cpu0.itb.fetch_misses                    28873                       # ITB misses
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.read_acv                            0                       # DTB read access violations
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.write_acv                           0                       # DTB write access violations
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir                  351      0.22%      0.22% # number of callpals executed
system.cpu0.kern.callpal::wrmces                    1      0.00%      0.22% # number of callpals executed
system.cpu0.kern.callpal::wrfen                     1      0.00%      0.22% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.22% # number of callpals executed
system.cpu0.kern.callpal::swpctx                 3287      2.03%      2.25% # number of callpals executed
system.cpu0.kern.callpal::tbi                      43      0.03%      2.27% # number of callpals executed
system.cpu0.kern.callpal::wrent                     7      0.00%      2.28% # number of callpals executed
system.cpu0.kern.callpal::swpipl               147045     90.75%     93.03% # number of callpals executed
system.cpu0.kern.callpal::rdps                   6369      3.93%     96.96% # number of callpals executed
system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.96% # number of callpals executed
system.cpu0.kern.callpal::wrusp                     3      0.00%     96.96% # number of callpals executed
system.cpu0.kern.callpal::rdusp                     7      0.00%     96.96% # number of callpals executed
system.cpu0.kern.callpal::whami                     2      0.00%     96.96% # number of callpals executed
system.cpu0.kern.callpal::rti                    4450      2.75%     99.71% # number of callpals executed
system.cpu0.kern.callpal::callsys                 330      0.20%     99.91% # number of callpals executed
system.cpu0.kern.callpal::imb                     138      0.09%    100.00% # number of callpals executed
system.cpu0.kern.callpal::total                162037                       # number of callpals executed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.hwrei                    176107                       # number of hwrei instructions executed
system.cpu0.kern.inst.quiesce                    6625                       # number of quiesce instructions executed
system.cpu0.kern.ipl_count::0                   62137     40.37%     40.37% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21                    238      0.15%     40.53% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22                   1925      1.25%     41.78% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30                    254      0.17%     41.94% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31                  89359     58.06%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total              153913                       # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0                    61267     49.13%     49.13% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21                     238      0.19%     49.32% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22                    1925      1.54%     50.87% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30                     254      0.20%     51.07% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31                   61013     48.93%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total               124697                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0            1862714429000     97.99%     97.99% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21               96239500      0.01%     98.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22              398463500      0.02%     98.02% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30              103371000      0.01%     98.03% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31            37530876000      1.97%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total        1900843379000                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0                 0.985999                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31                0.682785                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.mode_good::kernel               1172                      
system.cpu0.kern.mode_good::user                 1173                      
system.cpu0.kern.mode_good::idle                    0                      
system.cpu0.kern.mode_switch::kernel             6892                       # number of protection mode switches
system.cpu0.kern.mode_switch::user               1173                       # number of protection mode switches
system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
system.cpu0.kern.mode_switch_good::kernel     0.170052                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle      no_value                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total     no_value                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel      1898870092500     99.90%     99.90% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user          1973278500      0.10%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    3288                       # number of times the context was actually changed
system.cpu0.kern.syscall::2                         6      2.99%      2.99% # number of syscalls executed
system.cpu0.kern.syscall::3                        17      8.46%     11.44% # number of syscalls executed
system.cpu0.kern.syscall::4                         3      1.49%     12.94% # number of syscalls executed
system.cpu0.kern.syscall::6                        27     13.43%     26.37% # number of syscalls executed
system.cpu0.kern.syscall::12                        1      0.50%     26.87% # number of syscalls executed
system.cpu0.kern.syscall::17                        9      4.48%     31.34% # number of syscalls executed
system.cpu0.kern.syscall::19                        6      2.99%     34.33% # number of syscalls executed
system.cpu0.kern.syscall::20                        4      1.99%     36.32% # number of syscalls executed
system.cpu0.kern.syscall::23                        1      0.50%     36.82% # number of syscalls executed
system.cpu0.kern.syscall::24                        3      1.49%     38.31% # number of syscalls executed
system.cpu0.kern.syscall::33                        7      3.48%     41.79% # number of syscalls executed
system.cpu0.kern.syscall::41                        2      1.00%     42.79% # number of syscalls executed
system.cpu0.kern.syscall::45                       36     17.91%     60.70% # number of syscalls executed
system.cpu0.kern.syscall::47                        3      1.49%     62.19% # number of syscalls executed
system.cpu0.kern.syscall::48                        7      3.48%     65.67% # number of syscalls executed
system.cpu0.kern.syscall::54                        9      4.48%     70.15% # number of syscalls executed
system.cpu0.kern.syscall::58                        1      0.50%     70.65% # number of syscalls executed
system.cpu0.kern.syscall::59                        5      2.49%     73.13% # number of syscalls executed
system.cpu0.kern.syscall::71                       27     13.43%     86.57% # number of syscalls executed
system.cpu0.kern.syscall::73                        3      1.49%     88.06% # number of syscalls executed
system.cpu0.kern.syscall::74                        7      3.48%     91.54% # number of syscalls executed
system.cpu0.kern.syscall::87                        1      0.50%     92.04% # number of syscalls executed
system.cpu0.kern.syscall::90                        1      0.50%     92.54% # number of syscalls executed
system.cpu0.kern.syscall::92                        7      3.48%     96.02% # number of syscalls executed
system.cpu0.kern.syscall::97                        2      1.00%     97.01% # number of syscalls executed
system.cpu0.kern.syscall::98                        2      1.00%     98.01% # number of syscalls executed
system.cpu0.kern.syscall::132                       1      0.50%     98.51% # number of syscalls executed
system.cpu0.kern.syscall::144                       1      0.50%     99.00% # number of syscalls executed
system.cpu0.kern.syscall::147                       2      1.00%    100.00% # number of syscalls executed
system.cpu0.kern.syscall::total                   201                       # number of syscalls executed
system.cpu0.memDep0.conflictingLoads          2303690                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         1915346                       # Number of conflicting stores.
system.cpu0.memDep0.insertedLoads             9134167                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores            5841972                       # Number of stores inserted to the mem dependence unit.
system.cpu0.numCycles                       112777545                       # number of cpu cycles simulated
system.cpu0.rename.RENAME:BlockCycles        12780906                       # Number of cycles rename is blocking
system.cpu0.rename.RENAME:CommittedMaps      33989447                       # Number of HB maps that are committed
system.cpu0.rename.RENAME:IQFullEvents        1008250                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.RENAME:IdleCycles         33579404                       # Number of cycles rename is idle
system.cpu0.rename.RENAME:LSQFullEvents       1370622                       # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RENAME:ROBFullEvents         43227                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.RENAME:RenameLookups      72557706                       # Number of register rename lookups that rename has made
system.cpu0.rename.RENAME:RenamedInsts       59333926                       # Number of instructions processed by rename
system.cpu0.rename.RENAME:RenamedOperands     39987201                       # Number of destination operands rename has renamed
system.cpu0.rename.RENAME:RunCycles          11036329                       # Number of cycles rename is running
system.cpu0.rename.RENAME:SquashCycles        1270160                       # Number of cycles rename is squashing
system.cpu0.rename.RENAME:UnblockCycles       3988199                       # Number of cycles rename is unblocking
system.cpu0.rename.RENAME:UndoneMaps          5997752                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.RENAME:serializeStallCycles     16871933                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RENAME:serializingInsts      1393572                       # count of serializing insts renamed
system.cpu0.rename.RENAME:skidInsts          10085816                       # count of insts added to the skid buffer
system.cpu0.rename.RENAME:tempSerializingInsts       207581                       # count of temporary serializing insts renamed
system.cpu0.timesIdled                        1187611                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.BTBHits                 1157962                       # Number of BTB hits
system.cpu1.BPredUnit.BTBLookups              2699963                       # Number of BTB lookups
system.cpu1.BPredUnit.RASInCorrect               8335                       # Number of incorrect RAS predictions.
system.cpu1.BPredUnit.condIncorrect            172116                       # Number of conditional branches incorrect
system.cpu1.BPredUnit.condPredicted           2481640                       # Number of conditional branches predicted
system.cpu1.BPredUnit.lookups                 2995076                       # Number of BP lookups
system.cpu1.BPredUnit.usedRAS                  209806                       # Number of times the RAS was used to get a target.
system.cpu1.commit.COM:branches               1517916                       # Number of branches committed
system.cpu1.commit.COM:bw_lim_events           197525                       # number cycles where commit BW limit reached
system.cpu1.commit.COM:bw_limited                   0                       # number of insts not committed due to BW limits
system.cpu1.commit.COM:committed_per_cycle::samples     17848598                       # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::mean     0.593368                       # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::stdev     1.404700                       # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::0     13459755     75.41%     75.41% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::1      2076221     11.63%     87.04% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::2       798391      4.47%     91.52% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::3       569134      3.19%     94.70% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::4       394612      2.21%     96.92% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::5       153567      0.86%     97.78% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::6       111850      0.63%     98.40% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::7        87543      0.49%     98.89% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::8       197525      1.11%    100.00% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::total     17848598                       # Number of insts commited each cycle
system.cpu1.commit.COM:count                 10590789                       # Number of instructions committed
system.cpu1.commit.COM:loads                  1991065                       # Number of loads committed
system.cpu1.commit.COM:membars                  52740                       # Number of memory barriers committed
system.cpu1.commit.COM:refs                   3374997                       # Number of memory references committed
system.cpu1.commit.COM:swp_count                    0                       # Number of s/w prefetches committed
system.cpu1.commit.branchMispredicts           164251                       # The number of times a branch was mispredicted
system.cpu1.commit.commitCommittedInsts      10590789                       # The number of committed instructions
system.cpu1.commit.commitNonSpecStalls         163017                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.commitSquashedInsts        1716683                       # The number of squashed insts skipped by commit
system.cpu1.committedInsts                   10063537                       # Number of Instructions Simulated
system.cpu1.committedInsts_total             10063537                       # Number of Instructions Simulated
system.cpu1.cpi                              1.953144                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.953144                       # CPI: Total CPI of All Threads
system.cpu1.dcache.LoadLockedReq_accesses::0        46385                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        46385                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11093.156176                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency  8017.085427                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_hits::0        39649                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        39649                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_miss_latency     74723500                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_rate::0     0.145219                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_misses::0         6736                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total         6736                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_mshr_hits          766                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency     47862000                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0     0.128705                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_misses         5970                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.ReadReq_accesses::0        2063183                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total      2063183                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_avg_miss_latency::0 15106.279717                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11684.123629                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_hits::0            1870531                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total        1870531                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_miss_latency    2910255000                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_rate::0      0.093376                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_misses::0           192652                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       192652                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_mshr_hits            97561                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_miss_latency   1111055000                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::0     0.046089                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_misses          95091                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency     17677000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.StoreCondReq_accesses::0        43197                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        43197                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 13112.263417                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 10114.107884                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_hits::0         39340                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        39340                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_miss_latency     50574000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_rate::0     0.089289                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_misses::0         3857                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total         3857                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_mshr_miss_latency     39000000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0     0.089265                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_misses         3856                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.WriteReq_accesses::0       1334344                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      1334344                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_avg_miss_latency::0 21202.003457                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 18758.167110                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_hits::0           1085015                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       1085015                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_miss_latency   5286274320                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_rate::0     0.186855                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_misses::0          249329                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total       249329                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_mshr_hits          200876                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_miss_latency    908889471                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_rate::0     0.036312                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_misses         48453                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency    377675000                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 10123.559438                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_refs                 22.895667                       # Average number of references to valid blocks.
system.cpu1.dcache.blocked::no_mshrs             5123                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_mshrs     51862995                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.demand_accesses::0         3397527                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total      3397527                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_avg_miss_latency::0 18544.981164                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency 14071.953345                       # average overall mshr miss latency
system.cpu1.dcache.demand_hits::0             2955546                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total         2955546                       # number of demand (read+write) hits
system.cpu1.dcache.demand_miss_latency     8196529320                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_rate::0       0.130089                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu1.dcache.demand_misses::0            441981                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        441981                       # number of demand (read+write) misses
system.cpu1.dcache.demand_mshr_hits            298437                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_miss_latency   2019944471                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_rate::0     0.042250                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_misses          143544                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.occ_%::0                  0.933247                       # Average percentage of cache occupancy
system.cpu1.dcache.occ_blocks::0           477.822541                       # Average occupied blocks per context
system.cpu1.dcache.overall_accesses::0        3397527                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total      3397527                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_avg_miss_latency::0 18544.981164                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency 14071.953345                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_hits::0            2955546                       # number of overall hits
system.cpu1.dcache.overall_hits::1                  0                       # number of overall hits
system.cpu1.dcache.overall_hits::total        2955546                       # number of overall hits
system.cpu1.dcache.overall_miss_latency    8196529320                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_rate::0      0.130089                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu1.dcache.overall_misses::0           441981                       # number of overall misses
system.cpu1.dcache.overall_misses::1                0                       # number of overall misses
system.cpu1.dcache.overall_misses::total       441981                       # number of overall misses
system.cpu1.dcache.overall_mshr_hits           298437                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_miss_latency   2019944471                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_rate::0     0.042250                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_misses         143544                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_uncacheable_latency    395352000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.replacements                132498                       # number of replacements
system.cpu1.dcache.sampled_refs                132892                       # Sample count of references to valid blocks.
system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.dcache.tagsinuse               477.822541                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                 3042651                       # Total number of references to valid blocks.
system.cpu1.dcache.warmup_cycle          1877659701000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.writebacks                   88702                       # number of writebacks
system.cpu1.decode.DECODE:BlockedCycles       6987029                       # Number of cycles decode is blocked
system.cpu1.decode.DECODE:BranchMispred          7945                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DECODE:BranchResolved       127739                       # Number of times decode resolved a branch
system.cpu1.decode.DECODE:DecodedInsts       13932578                       # Number of instructions handled by decode
system.cpu1.decode.DECODE:IdleCycles          8260937                       # Number of cycles decode is idle
system.cpu1.decode.DECODE:RunCycles           2501859                       # Number of cycles decode is running
system.cpu1.decode.DECODE:SquashCycles         305063                       # Number of cycles decode is squashing
system.cpu1.decode.DECODE:SquashedInsts         23694                       # Number of squashed instructions handled by decode
system.cpu1.decode.DECODE:UnblockCycles         98772                       # Number of cycles decode is unblocking
system.cpu1.dtb.data_accesses                  453342                       # DTB accesses
system.cpu1.dtb.data_acv                          183                       # DTB access violations
system.cpu1.dtb.data_hits                     3613400                       # DTB hits
system.cpu1.dtb.data_misses                     12964                       # DTB misses
system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
system.cpu1.dtb.fetch_acv                           0                       # ITB acv
system.cpu1.dtb.fetch_hits                          0                       # ITB hits
system.cpu1.dtb.fetch_misses                        0                       # ITB misses
system.cpu1.dtb.read_accesses                  321975                       # DTB read accesses
system.cpu1.dtb.read_acv                           83                       # DTB read access violations
system.cpu1.dtb.read_hits                     2187186                       # DTB read hits
system.cpu1.dtb.read_misses                     10487                       # DTB read misses
system.cpu1.dtb.write_accesses                 131367                       # DTB write accesses
system.cpu1.dtb.write_acv                         100                       # DTB write access violations
system.cpu1.dtb.write_hits                    1426214                       # DTB write hits
system.cpu1.dtb.write_misses                     2477                       # DTB write misses
system.cpu1.fetch.Branches                    2995076                       # Number of branches that fetch encountered
system.cpu1.fetch.CacheLines                  1674453                       # Number of cache lines fetched
system.cpu1.fetch.Cycles                      4316686                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.IcacheSquashes               103652                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.Insts                      14184875                       # Number of instructions fetch has processed
system.cpu1.fetch.MiscStallCycles                 463                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.SquashCycles                 191233                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.branchRate                 0.152378                       # Number of branch fetches per cycle
system.cpu1.fetch.icacheStallCycles           1674453                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.predictedBranches           1367768                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.rate                       0.721673                       # Number of inst fetches per cycle
system.cpu1.fetch.rateDist::samples          18153661                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.781378                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            2.130034                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0                15520231     85.49%     85.49% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1                  211004      1.16%     86.66% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                  323759      1.78%     88.44% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3                  198428      1.09%     89.53% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4                  375870      2.07%     91.60% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5                  125712      0.69%     92.30% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6                  169249      0.93%     93.23% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7                  251729      1.39%     94.61% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8                  977679      5.39%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total            18153661                       # Number of instructions fetched each cycle (Total)
system.cpu1.icache.ReadReq_accesses::0        1674453                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total      1674453                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_avg_miss_latency::0 14671.340426                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11628.734234                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_hits::0            1410604                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total        1410604                       # number of ReadReq hits
system.cpu1.icache.ReadReq_miss_latency    3871018500                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_rate::0      0.157573                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_misses::0           263849                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       263849                       # number of ReadReq misses
system.cpu1.icache.ReadReq_mshr_hits             8241                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_miss_latency   2972397500                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::0     0.152652                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_misses         255608                       # number of ReadReq MSHR misses
system.cpu1.icache.avg_blocked_cycles::no_mshrs  4444.444444                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu1.icache.avg_refs                  5.519875                       # Average number of references to valid blocks.
system.cpu1.icache.blocked::no_mshrs                9                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_mshrs        40000                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.demand_accesses::0         1674453                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total      1674453                       # number of demand (read+write) accesses
system.cpu1.icache.demand_avg_miss_latency::0 14671.340426                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency 11628.734234                       # average overall mshr miss latency
system.cpu1.icache.demand_hits::0             1410604                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::1                   0                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total         1410604                       # number of demand (read+write) hits
system.cpu1.icache.demand_miss_latency     3871018500                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_rate::0       0.157573                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
system.cpu1.icache.demand_misses::0            263849                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::1                 0                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        263849                       # number of demand (read+write) misses
system.cpu1.icache.demand_mshr_hits              8241                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_miss_latency   2972397500                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_rate::0     0.152652                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_misses          255608                       # number of demand (read+write) MSHR misses
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.occ_%::0                  0.900435                       # Average percentage of cache occupancy
system.cpu1.icache.occ_blocks::0           461.022947                       # Average occupied blocks per context
system.cpu1.icache.overall_accesses::0        1674453                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total      1674453                       # number of overall (read+write) accesses
system.cpu1.icache.overall_avg_miss_latency::0 14671.340426                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency 11628.734234                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_hits::0            1410604                       # number of overall hits
system.cpu1.icache.overall_hits::1                  0                       # number of overall hits
system.cpu1.icache.overall_hits::total        1410604                       # number of overall hits
system.cpu1.icache.overall_miss_latency    3871018500                       # number of overall miss cycles
system.cpu1.icache.overall_miss_rate::0      0.157573                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
system.cpu1.icache.overall_misses::0           263849                       # number of overall misses
system.cpu1.icache.overall_misses::1                0                       # number of overall misses
system.cpu1.icache.overall_misses::total       263849                       # number of overall misses
system.cpu1.icache.overall_mshr_hits             8241                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_miss_latency   2972397500                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_rate::0     0.152652                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_misses         255608                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.icache.replacements                255038                       # number of replacements
system.cpu1.icache.sampled_refs                255550                       # Sample count of references to valid blocks.
system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.icache.tagsinuse               461.022947                       # Cycle average of tags in use
system.cpu1.icache.total_refs                 1410604                       # Total number of references to valid blocks.
system.cpu1.icache.warmup_cycle          1897916451000                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.writebacks                      13                       # number of writebacks
system.cpu1.idleCycles                        1501880                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.iew.EXEC:branches                 1627207                       # Number of branches executed
system.cpu1.iew.EXEC:nop                       601288                       # number of nop insts executed
system.cpu1.iew.EXEC:rate                    0.550852                       # Inst execution rate
system.cpu1.iew.EXEC:refs                     3642900                       # number of memory reference insts executed
system.cpu1.iew.EXEC:stores                   1435734                       # Number of stores executed
system.cpu1.iew.EXEC:swp                            0                       # number of swp insts executed
system.cpu1.iew.WB:consumers                  6254497                       # num instructions consuming a value
system.cpu1.iew.WB:count                     10719851                       # cumulative count of insts written-back
system.cpu1.iew.WB:fanout                    0.736543                       # average fanout of values written-back
system.cpu1.iew.WB:penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu1.iew.WB:penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.iew.WB:producers                  4606706                       # num instructions producing a value
system.cpu1.iew.WB:rate                      0.545386                       # insts written-back per cycle
system.cpu1.iew.WB:sent                      10743061                       # cumulative count of insts sent to commit
system.cpu1.iew.branchMispredicts              178420                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewBlockCycles                 265381                       # Number of cycles IEW is blocking
system.cpu1.iew.iewDispLoadInsts              2308328                       # Number of dispatched load instructions
system.cpu1.iew.iewDispNonSpecInsts            500549                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewDispSquashedInsts           208852                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispStoreInsts             1509637                       # Number of dispatched store instructions
system.cpu1.iew.iewDispatchedInsts           12390699                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewExecLoadInsts              2207166                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts           106974                       # Number of squashed instructions skipped in execute
system.cpu1.iew.iewExecutedInsts             10827293                       # Number of executed instructions
system.cpu1.iew.iewIQFullEvents                  2483                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewLSQFullEvents                 4852                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.iewSquashCycles                305063                       # Number of cycles IEW is squashing
system.cpu1.iew.iewUnblockCycles                10314                       # Number of cycles IEW is unblocking
system.cpu1.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread.0.cacheBlocked        22342                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.lsq.thread.0.forwLoads          67469                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread.0.ignoredResponses         2212                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread.0.memOrderViolation        10592                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread.0.rescheduledLoads          380                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread.0.squashedLoads       317263                       # Number of loads squashed
system.cpu1.iew.lsq.thread.0.squashedStores       125705                       # Number of stores squashed
system.cpu1.iew.memOrderViolationEvents         10592                       # Number of memory order violations
system.cpu1.iew.predictedNotTakenIncorrect       104736                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.predictedTakenIncorrect         73684                       # Number of branches that were predicted taken incorrectly
system.cpu1.ipc                              0.511995                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.511995                       # IPC: Total IPC of All Threads
system.cpu1.iq.ISSUE:FU_type_0::No_OpClass         3525      0.03%      0.03% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IntAlu        6856403     62.71%     62.74% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IntMult         17935      0.16%     62.90% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IntDiv              0      0.00%     62.90% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatAdd        11432      0.10%     63.01% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatCmp            0      0.00%     63.01% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatCvt            0      0.00%     63.01% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     63.01% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatDiv         1762      0.02%     63.02% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     63.02% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdAdd             0      0.00%     63.02% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     63.02% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdAlu             0      0.00%     63.02% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdCmp             0      0.00%     63.02% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdCvt             0      0.00%     63.02% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdMisc            0      0.00%     63.02% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdMult            0      0.00%     63.02% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     63.02% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     63.02% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     63.02% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdSqrt            0      0.00%     63.02% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     63.02% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     63.02% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     63.02% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     63.02% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     63.02% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     63.02% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     63.02% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     63.02% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     63.02% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::MemRead       2282654     20.88%     83.90% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::MemWrite      1452686     13.29%     97.18% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IprAccess       307870      2.82%    100.00% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::total        10934267                       # Type of FU issued
system.cpu1.iq.ISSUE:fu_busy_cnt               157620                       # FU busy when requested
system.cpu1.iq.ISSUE:fu_busy_rate            0.014415                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.ISSUE:fu_full::No_OpClass            0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IntAlu             4070      2.58%      2.58% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IntMult               0      0.00%      2.58% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IntDiv                0      0.00%      2.58% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatAdd              0      0.00%      2.58% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatCmp              0      0.00%      2.58% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatCvt              0      0.00%      2.58% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatMult             0      0.00%      2.58% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatDiv              0      0.00%      2.58% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatSqrt             0      0.00%      2.58% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdAdd               0      0.00%      2.58% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdAddAcc            0      0.00%      2.58% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdAlu               0      0.00%      2.58% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdCmp               0      0.00%      2.58% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdCvt               0      0.00%      2.58% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdMisc              0      0.00%      2.58% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdMult              0      0.00%      2.58% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      2.58% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdShift             0      0.00%      2.58% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      2.58% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdSqrt              0      0.00%      2.58% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      2.58% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      2.58% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      2.58% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      2.58% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      2.58% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      2.58% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      2.58% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      2.58% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      2.58% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::MemRead           93965     59.61%     62.20% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::MemWrite          59585     37.80%    100.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IprAccess             0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:issued_per_cycle::samples     18153661                       # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::mean     0.602317                       # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::stdev     1.206394                       # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::0     12924725     71.20%     71.20% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::1      2574747     14.18%     85.38% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::2      1068107      5.88%     91.26% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::3       685428      3.78%     95.04% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::4       525394      2.89%     97.93% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::5       238254      1.31%     99.25% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::6        93756      0.52%     99.76% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::7        34360      0.19%     99.95% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::8         8890      0.05%    100.00% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::total     18153661                       # Number of insts issued each cycle
system.cpu1.iq.ISSUE:rate                    0.556294                       # Inst issue rate
system.cpu1.iq.iqInstsAdded                  11233407                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqInstsIssued                 10934267                       # Number of instructions issued
system.cpu1.iq.iqNonSpecInstsAdded             556004                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqSquashedInstsExamined        1651489                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedInstsIssued            10261                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedNonSpecRemoved        392987                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.iqSquashedOperandsExamined       847945                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.itb.data_accesses                       0                       # DTB accesses
system.cpu1.itb.data_acv                            0                       # DTB access violations
system.cpu1.itb.data_hits                           0                       # DTB hits
system.cpu1.itb.data_misses                         0                       # DTB misses
system.cpu1.itb.fetch_accesses                 448239                       # ITB accesses
system.cpu1.itb.fetch_acv                         291                       # ITB acv
system.cpu1.itb.fetch_hits                     439727                       # ITB hits
system.cpu1.itb.fetch_misses                     8512                       # ITB misses
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.read_acv                            0                       # DTB read access violations
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.write_acv                           0                       # DTB write access violations
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir                  254      0.45%      0.45% # number of callpals executed
system.cpu1.kern.callpal::wrmces                    1      0.00%      0.45% # number of callpals executed
system.cpu1.kern.callpal::wrfen                     1      0.00%      0.45% # number of callpals executed
system.cpu1.kern.callpal::swpctx                 1450      2.54%      2.99% # number of callpals executed
system.cpu1.kern.callpal::tbi                      12      0.02%      3.01% # number of callpals executed
system.cpu1.kern.callpal::wrent                     7      0.01%      3.02% # number of callpals executed
system.cpu1.kern.callpal::swpipl                49367     86.50%     89.53% # number of callpals executed
system.cpu1.kern.callpal::rdps                   2383      4.18%     93.70% # number of callpals executed
system.cpu1.kern.callpal::wrkgp                     1      0.00%     93.71% # number of callpals executed
system.cpu1.kern.callpal::wrusp                     4      0.01%     93.71% # number of callpals executed
system.cpu1.kern.callpal::rdusp                     2      0.00%     93.72% # number of callpals executed
system.cpu1.kern.callpal::whami                     3      0.01%     93.72% # number of callpals executed
system.cpu1.kern.callpal::rti                    3352      5.87%     99.60% # number of callpals executed
system.cpu1.kern.callpal::callsys                 187      0.33%     99.92% # number of callpals executed
system.cpu1.kern.callpal::imb                      43      0.08%    100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
system.cpu1.kern.callpal::total                 57069                       # number of callpals executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.hwrei                     64908                       # number of hwrei instructions executed
system.cpu1.kern.inst.quiesce                    2510                       # number of quiesce instructions executed
system.cpu1.kern.ipl_count::0                   20666     37.58%     37.58% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22                   1922      3.49%     41.07% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30                    351      0.64%     41.71% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31                  32054     58.29%    100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total               54993                       # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0                    20159     47.72%     47.72% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22                    1922      4.55%     52.28% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30                     351      0.83%     53.11% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31                   19808     46.89%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total                42240                       # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0            1870788653000     98.44%     98.44% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22              347996000      0.02%     98.46% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30              137644000      0.01%     98.46% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31            29218866000      1.54%    100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total        1900493159000                       # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0                 0.975467                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31                0.617957                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.mode_good::kernel                848                      
system.cpu1.kern.mode_good::user                  572                      
system.cpu1.kern.mode_good::idle                  276                      
system.cpu1.kern.mode_switch::kernel             1766                       # number of protection mode switches
system.cpu1.kern.mode_switch::user                572                       # number of protection mode switches
system.cpu1.kern.mode_switch::idle               2543                       # number of protection mode switches
system.cpu1.kern.mode_switch_good::kernel     0.480181                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle      0.108533                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total     1.588714                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel        6310117500      0.33%      0.33% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user          1035001500      0.05%      0.39% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle        1893135458000     99.61%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context                    1451                       # number of times the context was actually changed
system.cpu1.kern.syscall::2                         2      1.60%      1.60% # number of syscalls executed
system.cpu1.kern.syscall::3                        13     10.40%     12.00% # number of syscalls executed
system.cpu1.kern.syscall::4                         1      0.80%     12.80% # number of syscalls executed
system.cpu1.kern.syscall::6                        15     12.00%     24.80% # number of syscalls executed
system.cpu1.kern.syscall::15                        1      0.80%     25.60% # number of syscalls executed
system.cpu1.kern.syscall::17                        6      4.80%     30.40% # number of syscalls executed
system.cpu1.kern.syscall::19                        4      3.20%     33.60% # number of syscalls executed
system.cpu1.kern.syscall::20                        2      1.60%     35.20% # number of syscalls executed
system.cpu1.kern.syscall::23                        3      2.40%     37.60% # number of syscalls executed
system.cpu1.kern.syscall::24                        3      2.40%     40.00% # number of syscalls executed
system.cpu1.kern.syscall::33                        4      3.20%     43.20% # number of syscalls executed
system.cpu1.kern.syscall::45                       18     14.40%     57.60% # number of syscalls executed
system.cpu1.kern.syscall::47                        3      2.40%     60.00% # number of syscalls executed
system.cpu1.kern.syscall::48                        3      2.40%     62.40% # number of syscalls executed
system.cpu1.kern.syscall::54                        1      0.80%     63.20% # number of syscalls executed
system.cpu1.kern.syscall::59                        2      1.60%     64.80% # number of syscalls executed
system.cpu1.kern.syscall::71                       27     21.60%     86.40% # number of syscalls executed
system.cpu1.kern.syscall::74                        9      7.20%     93.60% # number of syscalls executed
system.cpu1.kern.syscall::90                        2      1.60%     95.20% # number of syscalls executed
system.cpu1.kern.syscall::92                        2      1.60%     96.80% # number of syscalls executed
system.cpu1.kern.syscall::132                       3      2.40%     99.20% # number of syscalls executed
system.cpu1.kern.syscall::144                       1      0.80%    100.00% # number of syscalls executed
system.cpu1.kern.syscall::total                   125                       # number of syscalls executed
system.cpu1.memDep0.conflictingLoads           486173                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores          418032                       # Number of conflicting stores.
system.cpu1.memDep0.insertedLoads             2308328                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores            1509637                       # Number of stores inserted to the mem dependence unit.
system.cpu1.numCycles                        19655541                       # number of cpu cycles simulated
system.cpu1.rename.RENAME:BlockCycles          539966                       # Number of cycles rename is blocking
system.cpu1.rename.RENAME:CommittedMaps       7148793                       # Number of HB maps that are committed
system.cpu1.rename.RENAME:IQFullEvents          37026                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.RENAME:IdleCycles          8494445                       # Number of cycles rename is idle
system.cpu1.rename.RENAME:LSQFullEvents        255442                       # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RENAME:ROBFullEvents         15493                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.RENAME:RenameLookups      15440476                       # Number of register rename lookups that rename has made
system.cpu1.rename.RENAME:RenamedInsts       12911511                       # Number of instructions processed by rename
system.cpu1.rename.RENAME:RenamedOperands      8475661                       # Number of destination operands rename has renamed
system.cpu1.rename.RENAME:RunCycles           2354555                       # Number of cycles rename is running
system.cpu1.rename.RENAME:SquashCycles         305063                       # Number of cycles rename is squashing
system.cpu1.rename.RENAME:UnblockCycles        804143                       # Number of cycles rename is unblocking
system.cpu1.rename.RENAME:UndoneMaps          1326868                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.RENAME:serializeStallCycles      5655487                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RENAME:serializingInsts       515592                       # count of serializing insts renamed
system.cpu1.rename.RENAME:skidInsts           2314825                       # count of insts added to the skid buffer
system.cpu1.rename.RENAME:tempSerializingInsts        52743                       # count of temporary serializing insts renamed
system.cpu1.timesIdled                         195289                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
system.iocache.ReadReq_accesses::1                172                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            172                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::1 115267.430233                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.iocache.ReadReq_avg_mshr_miss_latency 63267.430233                       # average ReadReq mshr miss latency
system.iocache.ReadReq_miss_latency          19825998                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_misses::1                  172                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              172                       # number of ReadReq misses
system.iocache.ReadReq_mshr_miss_latency     10881998                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::1            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_misses                172                       # number of ReadReq MSHR misses
system.iocache.WriteReq_accesses::1             41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::1 137698.469532                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
system.iocache.WriteReq_avg_mshr_miss_latency 85694.888285                       # average WriteReq mshr miss latency
system.iocache.WriteReq_miss_latency       5721646806                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_misses::1               41552                       # number of WriteReq misses
system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
system.iocache.WriteReq_mshr_miss_latency   3560793998                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_rate::0          inf                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::1            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_misses             41552                       # number of WriteReq MSHR misses
system.iocache.avg_blocked_cycles::no_mshrs  6175.166651                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
system.iocache.blocked::no_mshrs                10459                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_mshrs      64586068                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
system.iocache.demand_accesses::1               41724                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           41724                       # number of demand (read+write) accesses
system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
system.iocache.demand_avg_miss_latency::1 137606.001438                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.iocache.demand_avg_mshr_miss_latency 85602.434954                       # average overall mshr miss latency
system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
system.iocache.demand_miss_latency         5741472804                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
system.iocache.demand_misses::1                 41724                       # number of demand (read+write) misses
system.iocache.demand_misses::total             41724                       # number of demand (read+write) misses
system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
system.iocache.demand_mshr_miss_latency    3571675996                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_rate::0           inf                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::1             1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_misses               41724                       # number of demand (read+write) MSHR misses
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.iocache.occ_%::1                      0.029213                       # Average percentage of cache occupancy
system.iocache.occ_blocks::1                 0.467409                       # Average occupied blocks per context
system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
system.iocache.overall_accesses::1              41724                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          41724                       # number of overall (read+write) accesses
system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
system.iocache.overall_avg_miss_latency::1 137606.001438                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.iocache.overall_avg_mshr_miss_latency 85602.434954                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.iocache.overall_hits::0                      0                       # number of overall hits
system.iocache.overall_hits::1                      0                       # number of overall hits
system.iocache.overall_hits::total                  0                       # number of overall hits
system.iocache.overall_miss_latency        5741472804                       # number of overall miss cycles
system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
system.iocache.overall_misses::0                    0                       # number of overall misses
system.iocache.overall_misses::1                41724                       # number of overall misses
system.iocache.overall_misses::total            41724                       # number of overall misses
system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
system.iocache.overall_mshr_miss_latency   3571675996                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_misses              41724                       # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.iocache.replacements                     41692                       # number of replacements
system.iocache.sampled_refs                     41708                       # Sample count of references to valid blocks.
system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
system.iocache.tagsinuse                     0.467409                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.warmup_cycle              1711286220000                       # Cycle when the warmup percentage was hit.
system.iocache.writebacks                       41520                       # number of writebacks
system.l2c.ReadExReq_accesses::0               257299                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::1                42275                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           299574                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_avg_miss_latency::0 55985.285399                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::1 837699.087169                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::2          inf                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 40323.891140                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_hits::0                   140918                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::1                    34497                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               175415                       # number of ReadExReq hits
system.l2c.ReadExReq_miss_latency          6515623500                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_rate::0            0.452318                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::1            0.183986                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses::0                 116381                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::1                   7778                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             124159                       # number of ReadExReq misses
system.l2c.ReadExReq_mshr_miss_latency     5006574000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_rate::0       0.482548                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1       2.936937                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::2            inf                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_misses               124159                       # number of ReadExReq MSHR misses
system.l2c.ReadReq_accesses::0                1807451                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::1                 343425                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            2150876                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_avg_miss_latency::0   52799.873154                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::1   3686022.252810                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::2            inf                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
system.l2c.ReadReq_avg_mshr_miss_latency 40018.119229                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_hits::0                    1503144                       # number of ReadReq hits
system.l2c.ReadReq_hits::1                     339066                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1842210                       # number of ReadReq hits
system.l2c.ReadReq_miss_latency           16067371000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_rate::0              0.168363                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::1              0.012693                       # miss rate for ReadReq accesses
system.l2c.ReadReq_misses::0                   304307                       # number of ReadReq misses
system.l2c.ReadReq_misses::1                     4359                       # number of ReadReq misses
system.l2c.ReadReq_misses::total               308666                       # number of ReadReq misses
system.l2c.ReadReq_mshr_hits                       16                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_miss_latency      12351592500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate::0         0.170765                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::1         0.898741                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::2              inf                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_misses                 308650                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_uncacheable_latency    840468500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.SCUpgradeReq_accesses::0               609                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::1               601                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          1210                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_avg_miss_latency::0  4894.075404                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::1  4740.869565                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::2          inf                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total          inf                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40013.692580                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_hits::0                    52                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::1                    26                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                78                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_miss_latency          2726000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_rate::0         0.914614                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::1         0.956739                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_misses::0                 557                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::1                 575                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1132                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_mshr_miss_latency     45295500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_rate::0     1.858785                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::1     1.883527                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::2          inf                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_misses              1132                       # number of SCUpgradeReq MSHR misses
system.l2c.UpgradeReq_accesses::0                2884                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::1                1624                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            4508                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_avg_miss_latency::0  5854.945055                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::1 12526.645768                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::2          inf                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 40016.724913                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_hits::0                     154                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::1                     348                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 502                       # number of UpgradeReq hits
system.l2c.UpgradeReq_miss_latency           15984000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_rate::0           0.946602                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::1           0.785714                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_misses::0                  2730                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::1                  1276                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              4006                       # number of UpgradeReq misses
system.l2c.UpgradeReq_mshr_miss_latency     160307000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_rate::0      1.389043                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::1      2.466749                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::2           inf                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_misses                4006                       # number of UpgradeReq MSHR misses
system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_mshr_uncacheable_latency   1533340998                       # number of WriteReq MSHR uncacheable cycles
system.l2c.Writeback_accesses::0               810378                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           810378                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_hits::0                   810378                       # number of Writeback hits
system.l2c.Writeback_hits::total               810378                       # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.l2c.avg_refs                          5.650924                       # Average number of references to valid blocks.
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.demand_accesses::0                 2064750                       # number of demand (read+write) accesses
system.l2c.demand_accesses::1                  385700                       # number of demand (read+write) accesses
system.l2c.demand_accesses::2                       0                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2450450                       # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency::0    53681.099770                       # average overall miss latency
system.l2c.demand_avg_miss_latency::1    1860673.518992                       # average overall miss latency
system.l2c.demand_avg_miss_latency::2             inf                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total          inf                       # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency  40105.835368                       # average overall mshr miss latency
system.l2c.demand_hits::0                     1644062                       # number of demand (read+write) hits
system.l2c.demand_hits::1                      373563                       # number of demand (read+write) hits
system.l2c.demand_hits::2                           0                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2017625                       # number of demand (read+write) hits
system.l2c.demand_miss_latency            22582994500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_rate::0               0.203748                       # miss rate for demand accesses
system.l2c.demand_miss_rate::1               0.031467                       # miss rate for demand accesses
system.l2c.demand_miss_rate::2               no_value                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
system.l2c.demand_misses::0                    420688                       # number of demand (read+write) misses
system.l2c.demand_misses::1                     12137                       # number of demand (read+write) misses
system.l2c.demand_misses::2                         0                       # number of demand (read+write) misses
system.l2c.demand_misses::total                432825                       # number of demand (read+write) misses
system.l2c.demand_mshr_hits                        16                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency       17358166500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate::0          0.209618                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1          1.122139                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::2               inf                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total           inf                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_misses                  432809                       # number of demand (read+write) MSHR misses
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.l2c.occ_%::0                          0.187928                       # Average percentage of cache occupancy
system.l2c.occ_%::1                          0.005741                       # Average percentage of cache occupancy
system.l2c.occ_%::2                          0.351843                       # Average percentage of cache occupancy
system.l2c.occ_blocks::0                 12316.075760                       # Average occupied blocks per context
system.l2c.occ_blocks::1                   376.251227                       # Average occupied blocks per context
system.l2c.occ_blocks::2                 23058.372205                       # Average occupied blocks per context
system.l2c.overall_accesses::0                2064750                       # number of overall (read+write) accesses
system.l2c.overall_accesses::1                 385700                       # number of overall (read+write) accesses
system.l2c.overall_accesses::2                      0                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2450450                       # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency::0   53681.099770                       # average overall miss latency
system.l2c.overall_avg_miss_latency::1   1860673.518992                       # average overall miss latency
system.l2c.overall_avg_miss_latency::2            inf                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total          inf                       # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency 40105.835368                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
system.l2c.overall_hits::0                    1644062                       # number of overall hits
system.l2c.overall_hits::1                     373563                       # number of overall hits
system.l2c.overall_hits::2                          0                       # number of overall hits
system.l2c.overall_hits::total                2017625                       # number of overall hits
system.l2c.overall_miss_latency           22582994500                       # number of overall miss cycles
system.l2c.overall_miss_rate::0              0.203748                       # miss rate for overall accesses
system.l2c.overall_miss_rate::1              0.031467                       # miss rate for overall accesses
system.l2c.overall_miss_rate::2              no_value                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          no_value                       # miss rate for overall accesses
system.l2c.overall_misses::0                   420688                       # number of overall misses
system.l2c.overall_misses::1                    12137                       # number of overall misses
system.l2c.overall_misses::2                        0                       # number of overall misses
system.l2c.overall_misses::total               432825                       # number of overall misses
system.l2c.overall_mshr_hits                       16                       # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency      17358166500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate::0         0.209618                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1         1.122139                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::2              inf                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses                 432809                       # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency   2373809498                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.l2c.replacements                        395557                       # number of replacements
system.l2c.sampled_refs                        431639                       # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
system.l2c.tagsinuse                     35750.699192                       # Cycle average of tags in use
system.l2c.total_refs                         2439159                       # Total number of references to valid blocks.
system.l2c.warmup_cycle                    9270445000                       # Cycle when the warmup percentage was hit.
system.l2c.writebacks                          121360                       # number of writebacks
system.tsunami.ethernet.coalescedRxDesc      no_value                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.coalescedRxIdle      no_value                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.coalescedRxOk        no_value                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.coalescedRxOrn       no_value                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.coalescedSwi         no_value                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.coalescedTotal       no_value                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.coalescedTxDesc      no_value                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.coalescedTxIdle      no_value                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.coalescedTxOk        no_value                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR

---------- End Simulation Statistics   ----------