2012-09-21 17:48:13 +02:00
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/*
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2014-05-10 00:58:48 +02:00
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* Copyright (c) 2012-2014 ARM Limited
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2012-09-21 17:48:13 +02:00
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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2013-08-19 09:52:30 +02:00
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* Copyright (c) 2013 Amin Farmahini-Farahani
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* All rights reserved.
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*
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2012-09-21 17:48:13 +02:00
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Andreas Hansson
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* Ani Udipi
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2013-11-01 16:56:20 +01:00
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* Neha Agarwal
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2012-09-21 17:48:13 +02:00
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*/
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/**
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* @file
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2014-03-23 16:12:12 +01:00
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* DRAMCtrl declaration
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2012-09-21 17:48:13 +02:00
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*/
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2014-03-23 16:12:12 +01:00
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#ifndef __MEM_DRAM_CTRL_HH__
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#define __MEM_DRAM_CTRL_HH__
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2012-09-21 17:48:13 +02:00
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2013-01-31 13:49:14 +01:00
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#include <deque>
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2012-09-21 17:48:13 +02:00
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#include "base/statistics.hh"
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#include "enums/AddrMap.hh"
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#include "enums/MemSched.hh"
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#include "enums/PageManage.hh"
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#include "mem/abstract_mem.hh"
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#include "mem/qport.hh"
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2014-03-23 16:12:12 +01:00
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#include "params/DRAMCtrl.hh"
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2012-09-21 17:48:13 +02:00
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#include "sim/eventq.hh"
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/**
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2014-08-26 16:13:03 +02:00
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* The DRAM controller is a single-channel memory controller capturing
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* the most important timing constraints associated with a
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* contemporary DRAM. For multi-channel memory systems, the controller
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* is combined with a crossbar model, with the channel address
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* interleaving taking part in the crossbar.
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2012-09-21 17:48:13 +02:00
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*
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2014-08-26 16:13:03 +02:00
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* As a basic design principle, this controller
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* model is not cycle callable, but instead uses events to: 1) decide
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* when new decisions can be made, 2) when resources become available,
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* 3) when things are to be considered done, and 4) when to send
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* things back. Through these simple principles, the model delivers
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* high performance, and lots of flexibility, allowing users to
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* evaluate the system impact of a wide range of memory technologies,
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* such as DDR3/4, LPDDR2/3/4, WideIO1/2, HBM and HMC.
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*
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* For more details, please see Hansson et al, "Simulating DRAM
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* controllers for future system architecture exploration",
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* Proc. ISPASS, 2014. If you use this model as part of your research
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* please cite the paper.
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2012-09-21 17:48:13 +02:00
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*/
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2014-03-23 16:12:12 +01:00
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class DRAMCtrl : public AbstractMemory
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2012-09-21 17:48:13 +02:00
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{
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private:
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// For now, make use of a queued slave port to avoid dealing with
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// flow control for the responses being sent back
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class MemoryPort : public QueuedSlavePort
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{
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SlavePacketQueue queue;
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2014-03-23 16:12:12 +01:00
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DRAMCtrl& memory;
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2012-09-21 17:48:13 +02:00
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public:
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2014-03-23 16:12:12 +01:00
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MemoryPort(const std::string& name, DRAMCtrl& _memory);
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2012-09-21 17:48:13 +02:00
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protected:
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Tick recvAtomic(PacketPtr pkt);
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void recvFunctional(PacketPtr pkt);
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bool recvTimingReq(PacketPtr);
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virtual AddrRangeList getAddrRanges() const;
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};
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/**
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* Our incoming port, for a multi-ported controller add a crossbar
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* in front of it
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*/
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MemoryPort port;
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/**
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* Remember if we have to retry a request when available.
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*/
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bool retryRdReq;
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bool retryWrReq;
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/**
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2014-05-10 00:58:48 +02:00
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* Bus state used to control the read/write switching and drive
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* the scheduling of the next request.
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2012-09-21 17:48:13 +02:00
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*/
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2014-05-10 00:58:48 +02:00
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enum BusState {
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READ = 0,
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READ_TO_WRITE,
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WRITE,
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WRITE_TO_READ
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};
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BusState busState;
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2012-09-21 17:48:13 +02:00
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2013-01-31 13:49:14 +01:00
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/** List to keep track of activate ticks */
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2013-11-01 16:56:22 +01:00
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std::vector<std::deque<Tick>> actTicks;
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2013-01-31 13:49:14 +01:00
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2012-09-21 17:48:13 +02:00
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/**
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2014-05-10 00:58:48 +02:00
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* A basic class to track the bank state, i.e. what row is
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* currently open (if any), when is the bank free to accept a new
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2014-05-10 00:58:48 +02:00
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* column (read/write) command, when can it be precharged, and
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* when can it be activated.
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2014-05-10 00:58:48 +02:00
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*
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* The bank also keeps track of how many bytes have been accessed
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* in the open row since it was opened.
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2012-09-21 17:48:13 +02:00
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*/
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class Bank
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{
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public:
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2014-05-10 00:58:48 +02:00
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static const uint32_t NO_ROW = -1;
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2012-09-21 17:48:13 +02:00
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uint32_t openRow;
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2014-06-30 19:56:02 +02:00
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uint8_t rank;
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uint8_t bank;
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2012-09-21 17:48:13 +02:00
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2014-05-10 00:58:48 +02:00
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Tick colAllowedAt;
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2014-05-10 00:58:48 +02:00
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Tick preAllowedAt;
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2013-11-01 16:56:22 +01:00
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Tick actAllowedAt;
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2012-09-21 17:48:13 +02:00
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2014-03-23 16:12:03 +01:00
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uint32_t rowAccesses;
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2013-05-30 18:54:13 +02:00
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uint32_t bytesAccessed;
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Bank() :
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2014-06-30 19:56:02 +02:00
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openRow(NO_ROW), rank(0), bank(0),
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colAllowedAt(0), preAllowedAt(0), actAllowedAt(0),
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2014-03-23 16:12:03 +01:00
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rowAccesses(0), bytesAccessed(0)
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2012-09-21 17:48:13 +02:00
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{ }
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};
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2013-08-19 09:52:30 +02:00
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/**
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* A burst helper helps organize and manage a packet that is larger than
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* the DRAM burst size. A system packet that is larger than the burst size
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* is split into multiple DRAM packets and all those DRAM packets point to
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* a single burst helper such that we know when the whole packet is served.
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*/
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class BurstHelper {
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public:
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/** Number of DRAM bursts requred for a system packet **/
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const unsigned int burstCount;
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/** Number of DRAM bursts serviced so far for a system packet **/
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unsigned int burstsServiced;
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BurstHelper(unsigned int _burstCount)
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: burstCount(_burstCount), burstsServiced(0)
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{ }
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};
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2012-09-21 17:48:13 +02:00
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/**
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* A DRAM packet stores packets along with the timestamp of when
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* the packet entered the queue, and also the decoded address.
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*/
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class DRAMPacket {
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public:
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/** When did request enter the controller */
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const Tick entryTime;
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/** When will request leave the controller */
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Tick readyTime;
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/** This comes from the outside world */
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const PacketPtr pkt;
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2013-11-01 16:56:19 +01:00
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const bool isRead;
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2012-09-21 17:48:13 +02:00
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/** Will be populated by address decoder */
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const uint8_t rank;
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2013-11-01 16:56:20 +01:00
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const uint8_t bank;
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2014-06-30 19:56:01 +02:00
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const uint32_t row;
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2013-08-19 09:52:30 +02:00
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2013-11-01 16:56:20 +01:00
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/**
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* Bank id is calculated considering banks in all the ranks
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* eg: 2 ranks each with 8 banks, then bankId = 0 --> rank0, bank0 and
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* bankId = 8 --> rank1, bank0
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*/
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const uint16_t bankId;
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2013-08-19 09:52:30 +02:00
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/**
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* The starting address of the DRAM packet.
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* This address could be unaligned to burst size boundaries. The
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* reason is to keep the address offset so we can accurately check
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* incoming read packets with packets in the write queue.
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*/
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2013-08-19 09:52:31 +02:00
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Addr addr;
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2013-08-19 09:52:30 +02:00
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/**
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* The size of this dram packet in bytes
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* It is always equal or smaller than DRAM burst size
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*/
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2013-08-19 09:52:31 +02:00
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unsigned int size;
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2013-08-19 09:52:30 +02:00
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/**
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* A pointer to the BurstHelper if this DRAMPacket is a split packet
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* If not a split packet (common case), this is set to NULL
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*/
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BurstHelper* burstHelper;
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2013-11-01 16:56:20 +01:00
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Bank& bankRef;
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2012-09-21 17:48:13 +02:00
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2013-11-01 16:56:20 +01:00
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DRAMPacket(PacketPtr _pkt, bool is_read, uint8_t _rank, uint8_t _bank,
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2014-06-30 19:56:01 +02:00
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uint32_t _row, uint16_t bank_id, Addr _addr,
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2013-11-01 16:56:20 +01:00
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unsigned int _size, Bank& bank_ref)
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2012-09-21 17:48:13 +02:00
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: entryTime(curTick()), readyTime(curTick()),
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2013-11-01 16:56:20 +01:00
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pkt(_pkt), isRead(is_read), rank(_rank), bank(_bank), row(_row),
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bankId(bank_id), addr(_addr), size(_size), burstHelper(NULL),
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bankRef(bank_ref)
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2012-09-21 17:48:13 +02:00
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{ }
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};
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/**
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* Bunch of things requires to setup "events" in gem5
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2014-05-10 00:58:48 +02:00
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* When event "respondEvent" occurs for example, the method
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* processRespondEvent is called; no parameters are allowed
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2012-09-21 17:48:13 +02:00
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* in these methods
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*/
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2014-05-10 00:58:48 +02:00
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void processNextReqEvent();
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EventWrapper<DRAMCtrl,&DRAMCtrl::processNextReqEvent> nextReqEvent;
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2012-09-21 17:48:13 +02:00
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void processRespondEvent();
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2014-03-23 16:12:12 +01:00
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EventWrapper<DRAMCtrl, &DRAMCtrl::processRespondEvent> respondEvent;
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2012-09-21 17:48:13 +02:00
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2014-05-10 00:58:48 +02:00
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void processActivateEvent();
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EventWrapper<DRAMCtrl, &DRAMCtrl::processActivateEvent> activateEvent;
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void processPrechargeEvent();
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EventWrapper<DRAMCtrl, &DRAMCtrl::processPrechargeEvent> prechargeEvent;
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2012-09-21 17:48:13 +02:00
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void processRefreshEvent();
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2014-03-23 16:12:12 +01:00
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EventWrapper<DRAMCtrl, &DRAMCtrl::processRefreshEvent> refreshEvent;
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2012-09-21 17:48:13 +02:00
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2014-05-10 00:58:48 +02:00
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void processPowerEvent();
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EventWrapper<DRAMCtrl,&DRAMCtrl::processPowerEvent> powerEvent;
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2012-09-21 17:48:13 +02:00
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/**
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* Check if the read queue has room for more entries
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*
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2013-08-19 09:52:30 +02:00
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* @param pktCount The number of entries needed in the read queue
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2012-09-21 17:48:13 +02:00
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* @return true if read queue is full, false otherwise
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*/
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2013-08-19 09:52:30 +02:00
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bool readQueueFull(unsigned int pktCount) const;
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2012-09-21 17:48:13 +02:00
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/**
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* Check if the write queue has room for more entries
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*
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2013-08-19 09:52:30 +02:00
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* @param pktCount The number of entries needed in the write queue
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2012-09-21 17:48:13 +02:00
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* @return true if write queue is full, false otherwise
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*/
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2013-08-19 09:52:30 +02:00
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bool writeQueueFull(unsigned int pktCount) const;
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2012-09-21 17:48:13 +02:00
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/**
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* When a new read comes in, first check if the write q has a
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* pending request to the same address.\ If not, decode the
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2013-08-19 09:52:30 +02:00
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* address to populate rank/bank/row, create one or mutliple
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* "dram_pkt", and push them to the back of the read queue.\
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* If this is the only
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2012-09-21 17:48:13 +02:00
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* read request in the system, schedule an event to start
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* servicing it.
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*
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* @param pkt The request packet from the outside world
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2013-08-19 09:52:30 +02:00
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* @param pktCount The number of DRAM bursts the pkt
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* translate to. If pkt size is larger then one full burst,
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* then pktCount is greater than one.
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2012-09-21 17:48:13 +02:00
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*/
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2013-08-19 09:52:30 +02:00
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void addToReadQueue(PacketPtr pkt, unsigned int pktCount);
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2012-09-21 17:48:13 +02:00
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/**
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* Decode the incoming pkt, create a dram_pkt and push to the
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* back of the write queue. \If the write q length is more than
|
|
|
|
* the threshold specified by the user, ie the queue is beginning
|
|
|
|
* to get full, stop reads, and start draining writes.
|
|
|
|
*
|
|
|
|
* @param pkt The request packet from the outside world
|
2013-08-19 09:52:30 +02:00
|
|
|
* @param pktCount The number of DRAM bursts the pkt
|
|
|
|
* translate to. If pkt size is larger then one full burst,
|
|
|
|
* then pktCount is greater than one.
|
2012-09-21 17:48:13 +02:00
|
|
|
*/
|
2013-08-19 09:52:30 +02:00
|
|
|
void addToWriteQueue(PacketPtr pkt, unsigned int pktCount);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
/**
|
|
|
|
* Actually do the DRAM access - figure out the latency it
|
|
|
|
* will take to service the req based on bank state, channel state etc
|
|
|
|
* and then update those states to account for this request.\ Based
|
|
|
|
* on this, update the packet's "readyTime" and move it to the
|
|
|
|
* response q from where it will eventually go back to the outside
|
|
|
|
* world.
|
|
|
|
*
|
|
|
|
* @param pkt The DRAM packet created from the outside world pkt
|
|
|
|
*/
|
|
|
|
void doDRAMAccess(DRAMPacket* dram_pkt);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* When a packet reaches its "readyTime" in the response Q,
|
|
|
|
* use the "access()" method in AbstractMemory to actually
|
|
|
|
* create the response packet, and send it back to the outside
|
|
|
|
* world requestor.
|
|
|
|
*
|
|
|
|
* @param pkt The packet from the outside world
|
2013-05-30 18:54:12 +02:00
|
|
|
* @param static_latency Static latency to add before sending the packet
|
2012-09-21 17:48:13 +02:00
|
|
|
*/
|
2013-05-30 18:54:12 +02:00
|
|
|
void accessAndRespond(PacketPtr pkt, Tick static_latency);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
/**
|
|
|
|
* Address decoder to figure out physical mapping onto ranks,
|
2013-08-19 09:52:30 +02:00
|
|
|
* banks, and rows. This function is called multiple times on the same
|
|
|
|
* system packet if the pakcet is larger than burst of the memory. The
|
|
|
|
* dramPktAddr is used for the offset within the packet.
|
2012-09-21 17:48:13 +02:00
|
|
|
*
|
|
|
|
* @param pkt The packet from the outside world
|
2013-08-19 09:52:30 +02:00
|
|
|
* @param dramPktAddr The starting address of the DRAM packet
|
|
|
|
* @param size The size of the DRAM packet in bytes
|
2013-11-01 16:56:19 +01:00
|
|
|
* @param isRead Is the request for a read or a write to DRAM
|
2012-09-21 17:48:13 +02:00
|
|
|
* @return A DRAMPacket pointer with the decoded information
|
|
|
|
*/
|
2014-03-23 16:12:06 +01:00
|
|
|
DRAMPacket* decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned int size,
|
|
|
|
bool isRead);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
/**
|
2014-05-10 00:58:48 +02:00
|
|
|
* The memory schduler/arbiter - picks which request needs to
|
2013-03-01 19:20:24 +01:00
|
|
|
* go next, based on the specified policy such as FCFS or FR-FCFS
|
2014-05-10 00:58:48 +02:00
|
|
|
* and moves it to the head of the queue.
|
2012-09-21 17:48:13 +02:00
|
|
|
*/
|
2014-05-10 00:58:48 +02:00
|
|
|
void chooseNext(std::deque<DRAMPacket*>& queue);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-11-01 16:56:27 +01:00
|
|
|
/**
|
|
|
|
* For FR-FCFS policy reorder the read/write queue depending on row buffer
|
|
|
|
* hits and earliest banks available in DRAM
|
|
|
|
*/
|
|
|
|
void reorderQueue(std::deque<DRAMPacket*>& queue);
|
|
|
|
|
2013-11-01 16:56:20 +01:00
|
|
|
/**
|
2014-05-10 00:58:48 +02:00
|
|
|
* Find which are the earliest banks ready to issue an activate
|
|
|
|
* for the enqueued requests. Assumes maximum of 64 banks per DIMM
|
2013-11-01 16:56:20 +01:00
|
|
|
*
|
|
|
|
* @param Queued requests to consider
|
|
|
|
* @return One-hot encoded mask of bank indices
|
|
|
|
*/
|
2014-05-10 00:58:48 +02:00
|
|
|
uint64_t minBankActAt(const std::deque<DRAMPacket*>& queue) const;
|
2013-01-31 13:49:14 +01:00
|
|
|
|
|
|
|
/**
|
|
|
|
* Keep track of when row activations happen, in order to enforce
|
|
|
|
* the maximum number of activations in the activation window. The
|
|
|
|
* method updates the time that the banks become available based
|
|
|
|
* on the current limits.
|
2014-05-10 00:58:48 +02:00
|
|
|
*
|
2014-06-30 19:56:02 +02:00
|
|
|
* @param bank Reference to the bank
|
2014-05-10 00:58:48 +02:00
|
|
|
* @param act_tick Time when the activation takes place
|
|
|
|
* @param row Index of the row
|
2013-01-31 13:49:14 +01:00
|
|
|
*/
|
2014-06-30 19:56:02 +02:00
|
|
|
void activateBank(Bank& bank, Tick act_tick, uint32_t row);
|
2014-05-10 00:58:48 +02:00
|
|
|
|
|
|
|
/**
|
|
|
|
* Precharge a given bank and also update when the precharge is
|
|
|
|
* done. This will also deal with any stats related to the
|
|
|
|
* accesses to the open page.
|
|
|
|
*
|
2014-06-30 19:56:03 +02:00
|
|
|
* @param bank_ref The bank to precharge
|
2014-05-10 00:58:48 +02:00
|
|
|
* @param pre_at Time when the precharge takes place
|
2014-06-30 19:56:03 +02:00
|
|
|
* @param trace Is this an auto precharge then do not add to trace
|
2014-05-10 00:58:48 +02:00
|
|
|
*/
|
2014-06-30 19:56:03 +02:00
|
|
|
void prechargeBank(Bank& bank_ref, Tick pre_at, bool trace = true);
|
2013-01-31 13:49:14 +01:00
|
|
|
|
2014-03-23 16:12:06 +01:00
|
|
|
/**
|
|
|
|
* Used for debugging to observe the contents of the queues.
|
|
|
|
*/
|
2012-09-21 17:48:13 +02:00
|
|
|
void printQs() const;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* The controller's main read and write queues
|
|
|
|
*/
|
2013-08-19 09:52:32 +02:00
|
|
|
std::deque<DRAMPacket*> readQueue;
|
|
|
|
std::deque<DRAMPacket*> writeQueue;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
/**
|
|
|
|
* Response queue where read packets wait after we're done working
|
2013-03-01 19:20:24 +01:00
|
|
|
* with them, but it's not time to send the response yet. The
|
|
|
|
* responses are stored seperately mostly to keep the code clean
|
|
|
|
* and help with events scheduling. For all logical purposes such
|
|
|
|
* as sizing the read queue, this and the main read queue need to
|
|
|
|
* be added together.
|
2012-09-21 17:48:13 +02:00
|
|
|
*/
|
2013-08-19 09:52:32 +02:00
|
|
|
std::deque<DRAMPacket*> respQueue;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-03-01 19:20:24 +01:00
|
|
|
/**
|
|
|
|
* If we need to drain, keep the drain manager around until we're
|
|
|
|
* done here.
|
2012-09-21 17:48:13 +02:00
|
|
|
*/
|
2012-11-02 17:32:01 +01:00
|
|
|
DrainManager *drainManager;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
/**
|
|
|
|
* Multi-dimensional vector of banks, first dimension is ranks,
|
|
|
|
* second is bank
|
|
|
|
*/
|
|
|
|
std::vector<std::vector<Bank> > banks;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* The following are basic design parameters of the memory
|
2013-08-19 09:52:30 +02:00
|
|
|
* controller, and are initialized based on parameter values.
|
|
|
|
* The rowsPerBank is determined based on the capacity, number of
|
|
|
|
* ranks and banks, the burst size, and the row buffer size.
|
|
|
|
*/
|
|
|
|
const uint32_t deviceBusWidth;
|
|
|
|
const uint32_t burstLength;
|
|
|
|
const uint32_t deviceRowBufferSize;
|
|
|
|
const uint32_t devicesPerRank;
|
|
|
|
const uint32_t burstSize;
|
|
|
|
const uint32_t rowBufferSize;
|
2014-03-23 16:12:01 +01:00
|
|
|
const uint32_t columnsPerRowBuffer;
|
2014-08-26 16:12:45 +02:00
|
|
|
const uint32_t columnsPerStripe;
|
2012-09-21 17:48:13 +02:00
|
|
|
const uint32_t ranksPerChannel;
|
|
|
|
const uint32_t banksPerRank;
|
2013-03-01 19:20:22 +01:00
|
|
|
const uint32_t channels;
|
2012-09-21 17:48:13 +02:00
|
|
|
uint32_t rowsPerBank;
|
|
|
|
const uint32_t readBufferSize;
|
|
|
|
const uint32_t writeBufferSize;
|
2014-03-23 16:12:01 +01:00
|
|
|
const uint32_t writeHighThreshold;
|
|
|
|
const uint32_t writeLowThreshold;
|
|
|
|
const uint32_t minWritesPerSwitch;
|
|
|
|
uint32_t writesThisTime;
|
2014-03-23 16:12:14 +01:00
|
|
|
uint32_t readsThisTime;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
/**
|
|
|
|
* Basic memory timing parameters initialized based on parameter
|
|
|
|
* values.
|
|
|
|
*/
|
2014-08-26 16:12:45 +02:00
|
|
|
const Tick M5_CLASS_VAR_USED tCK;
|
2012-09-21 17:48:13 +02:00
|
|
|
const Tick tWTR;
|
2014-05-10 00:58:48 +02:00
|
|
|
const Tick tRTW;
|
2012-09-21 17:48:13 +02:00
|
|
|
const Tick tBURST;
|
|
|
|
const Tick tRCD;
|
|
|
|
const Tick tCL;
|
|
|
|
const Tick tRP;
|
2013-11-01 16:56:16 +01:00
|
|
|
const Tick tRAS;
|
2014-05-10 00:58:48 +02:00
|
|
|
const Tick tWR;
|
2014-05-10 00:58:48 +02:00
|
|
|
const Tick tRTP;
|
2012-09-21 17:48:13 +02:00
|
|
|
const Tick tRFC;
|
|
|
|
const Tick tREFI;
|
2013-11-01 16:56:24 +01:00
|
|
|
const Tick tRRD;
|
2013-01-31 13:49:14 +01:00
|
|
|
const Tick tXAW;
|
|
|
|
const uint32_t activationLimit;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
/**
|
|
|
|
* Memory controller configuration initialized based on parameter
|
|
|
|
* values.
|
|
|
|
*/
|
|
|
|
Enums::MemSched memSchedPolicy;
|
|
|
|
Enums::AddrMap addrMapping;
|
|
|
|
Enums::PageManage pageMgmt;
|
|
|
|
|
2014-03-23 16:12:03 +01:00
|
|
|
/**
|
|
|
|
* Max column accesses (read and write) per row, before forefully
|
|
|
|
* closing it.
|
|
|
|
*/
|
|
|
|
const uint32_t maxAccessesPerRow;
|
|
|
|
|
2013-05-30 18:54:12 +02:00
|
|
|
/**
|
|
|
|
* Pipeline latency of the controller frontend. The frontend
|
|
|
|
* contribution is added to writes (that complete when they are in
|
|
|
|
* the write buffer) and reads that are serviced the write buffer.
|
|
|
|
*/
|
|
|
|
const Tick frontendLatency;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Pipeline latency of the backend and PHY. Along with the
|
|
|
|
* frontend contribution, this latency is added to reads serviced
|
|
|
|
* by the DRAM.
|
|
|
|
*/
|
|
|
|
const Tick backendLatency;
|
|
|
|
|
2012-09-21 17:48:13 +02:00
|
|
|
/**
|
|
|
|
* Till when has the main data bus been spoken for already?
|
|
|
|
*/
|
|
|
|
Tick busBusyUntil;
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
/**
|
|
|
|
* Keep track of when a refresh is due.
|
|
|
|
*/
|
|
|
|
Tick refreshDueAt;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* The refresh state is used to control the progress of the
|
|
|
|
* refresh scheduling. When normal operation is in progress the
|
|
|
|
* refresh state is idle. From there, it progresses to the refresh
|
|
|
|
* drain state once tREFI has passed. The refresh drain state
|
|
|
|
* captures the DRAM row active state, as it will stay there until
|
|
|
|
* all ongoing accesses complete. Thereafter all banks are
|
|
|
|
* precharged, and lastly, the DRAM is refreshed.
|
|
|
|
*/
|
|
|
|
enum RefreshState {
|
|
|
|
REF_IDLE = 0,
|
|
|
|
REF_DRAIN,
|
|
|
|
REF_PRE,
|
|
|
|
REF_RUN
|
|
|
|
};
|
|
|
|
|
|
|
|
RefreshState refreshState;
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
/**
|
|
|
|
* The power state captures the different operational states of
|
|
|
|
* the DRAM and interacts with the bus read/write state machine,
|
|
|
|
* and the refresh state machine. In the idle state all banks are
|
|
|
|
* precharged. From there we either go to an auto refresh (as
|
|
|
|
* determined by the refresh state machine), or to a precharge
|
|
|
|
* power down mode. From idle the memory can also go to the active
|
|
|
|
* state (with one or more banks active), and in turn from there
|
|
|
|
* to active power down. At the moment we do not capture the deep
|
|
|
|
* power down and self-refresh state.
|
|
|
|
*/
|
|
|
|
enum PowerState {
|
|
|
|
PWR_IDLE = 0,
|
|
|
|
PWR_REF,
|
|
|
|
PWR_PRE_PDN,
|
|
|
|
PWR_ACT,
|
|
|
|
PWR_ACT_PDN
|
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Since we are taking decisions out of order, we need to keep
|
|
|
|
* track of what power transition is happening at what time, such
|
|
|
|
* that we can go back in time and change history. For example, if
|
|
|
|
* we precharge all banks and schedule going to the idle state, we
|
|
|
|
* might at a later point decide to activate a bank before the
|
|
|
|
* transition to idle would have taken place.
|
|
|
|
*/
|
|
|
|
PowerState pwrStateTrans;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Current power state.
|
|
|
|
*/
|
|
|
|
PowerState pwrState;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Schedule a power state transition in the future, and
|
|
|
|
* potentially override an already scheduled transition.
|
|
|
|
*
|
|
|
|
* @param pwr_state Power state to transition to
|
|
|
|
* @param tick Tick when transition should take place
|
|
|
|
*/
|
|
|
|
void schedulePowerEvent(PowerState pwr_state, Tick tick);
|
|
|
|
|
2012-09-21 17:48:13 +02:00
|
|
|
Tick prevArrival;
|
|
|
|
|
2014-05-10 00:58:48 +02:00
|
|
|
/**
|
|
|
|
* The soonest you have to start thinking about the next request
|
|
|
|
* is the longest access time that can occur before
|
|
|
|
* busBusyUntil. Assuming you need to precharge, open a new row,
|
|
|
|
* and access, it is tRP + tRCD + tCL.
|
|
|
|
*/
|
|
|
|
Tick nextReqTime;
|
2013-11-01 16:56:25 +01:00
|
|
|
|
2012-09-21 17:48:13 +02:00
|
|
|
// All statistics that the model needs to capture
|
|
|
|
Stats::Scalar readReqs;
|
|
|
|
Stats::Scalar writeReqs;
|
2013-08-19 09:52:30 +02:00
|
|
|
Stats::Scalar readBursts;
|
|
|
|
Stats::Scalar writeBursts;
|
2013-11-01 16:56:28 +01:00
|
|
|
Stats::Scalar bytesReadDRAM;
|
|
|
|
Stats::Scalar bytesReadWrQ;
|
2012-09-21 17:48:13 +02:00
|
|
|
Stats::Scalar bytesWritten;
|
2013-11-01 16:56:31 +01:00
|
|
|
Stats::Scalar bytesReadSys;
|
|
|
|
Stats::Scalar bytesWrittenSys;
|
2012-09-21 17:48:13 +02:00
|
|
|
Stats::Scalar servicedByWrQ;
|
2013-11-01 16:56:31 +01:00
|
|
|
Stats::Scalar mergedWrBursts;
|
2012-09-21 17:48:13 +02:00
|
|
|
Stats::Scalar neitherReadNorWrite;
|
2013-11-01 16:56:31 +01:00
|
|
|
Stats::Vector perBankRdBursts;
|
|
|
|
Stats::Vector perBankWrBursts;
|
2012-09-21 17:48:13 +02:00
|
|
|
Stats::Scalar numRdRetry;
|
|
|
|
Stats::Scalar numWrRetry;
|
|
|
|
Stats::Scalar totGap;
|
|
|
|
Stats::Vector readPktSize;
|
|
|
|
Stats::Vector writePktSize;
|
|
|
|
Stats::Vector rdQLenPdf;
|
|
|
|
Stats::Vector wrQLenPdf;
|
2013-05-30 18:54:13 +02:00
|
|
|
Stats::Histogram bytesPerActivate;
|
2014-03-23 16:12:14 +01:00
|
|
|
Stats::Histogram rdPerTurnAround;
|
|
|
|
Stats::Histogram wrPerTurnAround;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
// Latencies summed over all requests
|
|
|
|
Stats::Scalar totQLat;
|
|
|
|
Stats::Scalar totMemAccLat;
|
|
|
|
Stats::Scalar totBusLat;
|
|
|
|
|
|
|
|
// Average latencies per request
|
|
|
|
Stats::Formula avgQLat;
|
|
|
|
Stats::Formula avgBusLat;
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Stats::Formula avgMemAccLat;
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// Average bandwidth
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Stats::Formula avgRdBW;
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Stats::Formula avgWrBW;
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2013-11-01 16:56:31 +01:00
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Stats::Formula avgRdBWSys;
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Stats::Formula avgWrBWSys;
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2012-09-21 17:48:13 +02:00
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Stats::Formula peakBW;
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Stats::Formula busUtil;
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2013-11-01 16:56:28 +01:00
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Stats::Formula busUtilRead;
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Stats::Formula busUtilWrite;
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2012-09-21 17:48:13 +02:00
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// Average queue lengths
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Stats::Average avgRdQLen;
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Stats::Average avgWrQLen;
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// Row hit count and rate
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Stats::Scalar readRowHits;
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Stats::Scalar writeRowHits;
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Stats::Formula readRowHitRate;
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Stats::Formula writeRowHitRate;
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Stats::Formula avgGap;
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|
|
2013-11-01 16:56:28 +01:00
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|
// DRAM Power Calculation
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|
|
Stats::Formula pageHitRate;
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2014-05-10 00:58:48 +02:00
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|
Stats::Vector pwrStateTime;
|
2013-11-01 16:56:28 +01:00
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|
2014-05-10 00:58:48 +02:00
|
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// Track when we transitioned to the current power state
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|
|
Tick pwrStateTick;
|
2014-05-10 00:58:48 +02:00
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|
2013-11-01 16:56:28 +01:00
|
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|
// To track number of banks which are currently active
|
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|
|
unsigned int numBanksActive;
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|
|
2012-11-02 17:50:16 +01:00
|
|
|
/** @todo this is a temporary workaround until the 4-phase code is
|
|
|
|
* committed. upstream caches needs this packet until true is returned, so
|
|
|
|
* hold onto it for deletion until a subsequent call
|
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|
|
*/
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|
|
std::vector<PacketPtr> pendingDelete;
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|
|
2012-09-21 17:48:13 +02:00
|
|
|
public:
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|
|
void regStats();
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|
|
|
2014-03-23 16:12:12 +01:00
|
|
|
DRAMCtrl(const DRAMCtrlParams* p);
|
2012-09-21 17:48:13 +02:00
|
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|
2012-11-02 17:32:01 +01:00
|
|
|
unsigned int drain(DrainManager* dm);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2012-10-15 14:12:35 +02:00
|
|
|
virtual BaseSlavePort& getSlavePort(const std::string& if_name,
|
|
|
|
PortID idx = InvalidPortID);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
virtual void init();
|
|
|
|
virtual void startup();
|
|
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|
|
protected:
|
|
|
|
|
|
|
|
Tick recvAtomic(PacketPtr pkt);
|
|
|
|
void recvFunctional(PacketPtr pkt);
|
|
|
|
bool recvTimingReq(PacketPtr pkt);
|
|
|
|
|
|
|
|
};
|
|
|
|
|
2014-03-23 16:12:12 +01:00
|
|
|
#endif //__MEM_DRAM_CTRL_HH__
|