2012-09-21 17:48:13 +02:00
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/*
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* Copyright (c) 2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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2013-08-19 09:52:30 +02:00
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* Copyright (c) 2013 Amin Farmahini-Farahani
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* All rights reserved.
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*
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2012-09-21 17:48:13 +02:00
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Andreas Hansson
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* Ani Udipi
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2013-11-01 16:56:20 +01:00
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* Neha Agarwal
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2012-09-21 17:48:13 +02:00
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*/
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/**
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* @file
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* SimpleDRAM declaration
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*/
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#ifndef __MEM_SIMPLE_DRAM_HH__
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#define __MEM_SIMPLE_DRAM_HH__
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2013-01-31 13:49:14 +01:00
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#include <deque>
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2012-09-21 17:48:13 +02:00
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#include "base/statistics.hh"
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#include "enums/AddrMap.hh"
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#include "enums/MemSched.hh"
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#include "enums/PageManage.hh"
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#include "mem/abstract_mem.hh"
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#include "mem/qport.hh"
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#include "params/SimpleDRAM.hh"
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#include "sim/eventq.hh"
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/**
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* The simple DRAM is a basic single-channel memory controller aiming
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* to mimic a high-level DRAM controller and the most important timing
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* constraints associated with the DRAM. The focus is really on
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* modelling the impact on the system rather than the DRAM itself,
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* hence the focus is on the controller model and not on the
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* memory. By adhering to the correct timing constraints, ultimately
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* there is no need for a memory model in addition to the controller
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* model.
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*
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* As a basic design principle, this controller is not cycle callable,
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* but instead uses events to decide when new decisions can be made,
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* when resources become available, when things are to be considered
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* done, and when to send things back. Through these simple
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* principles, we achieve a performant model that is not
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* cycle-accurate, but enables us to evaluate the system impact of a
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* wide range of memory technologies, and also collect statistics
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* about the use of the memory.
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*/
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class SimpleDRAM : public AbstractMemory
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{
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private:
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// For now, make use of a queued slave port to avoid dealing with
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// flow control for the responses being sent back
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class MemoryPort : public QueuedSlavePort
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{
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SlavePacketQueue queue;
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SimpleDRAM& memory;
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public:
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MemoryPort(const std::string& name, SimpleDRAM& _memory);
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protected:
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Tick recvAtomic(PacketPtr pkt);
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void recvFunctional(PacketPtr pkt);
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bool recvTimingReq(PacketPtr);
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virtual AddrRangeList getAddrRanges() const;
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};
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/**
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* Our incoming port, for a multi-ported controller add a crossbar
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* in front of it
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*/
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MemoryPort port;
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/**
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* Remember if we have to retry a request when available.
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*/
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bool retryRdReq;
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bool retryWrReq;
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/**
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* Remember that a row buffer hit occured
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*/
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bool rowHitFlag;
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/**
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* Use this flag to shutoff reads, i.e. do not schedule any reads
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* beyond those already done so that we can turn the bus around
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* and do a few writes, or refresh, or whatever
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*/
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bool stopReads;
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2013-01-31 13:49:14 +01:00
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/** List to keep track of activate ticks */
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std::deque<Tick> actTicks;
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2012-09-21 17:48:13 +02:00
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/**
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2013-05-30 18:54:13 +02:00
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* A basic class to track the bank state indirectly via times
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* "freeAt" and "tRASDoneAt" and what page is currently open. The
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* bank also keeps track of how many bytes have been accessed in
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* the open row since it was opened.
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2012-09-21 17:48:13 +02:00
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*/
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class Bank
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{
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public:
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static const uint32_t INVALID_ROW = -1;
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uint32_t openRow;
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Tick freeAt;
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Tick tRASDoneAt;
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2013-05-30 18:54:13 +02:00
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uint32_t bytesAccessed;
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Bank() :
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openRow(INVALID_ROW), freeAt(0), tRASDoneAt(0), bytesAccessed(0)
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2012-09-21 17:48:13 +02:00
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{ }
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};
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2013-08-19 09:52:30 +02:00
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/**
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* A burst helper helps organize and manage a packet that is larger than
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* the DRAM burst size. A system packet that is larger than the burst size
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* is split into multiple DRAM packets and all those DRAM packets point to
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* a single burst helper such that we know when the whole packet is served.
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*/
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class BurstHelper {
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public:
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/** Number of DRAM bursts requred for a system packet **/
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const unsigned int burstCount;
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/** Number of DRAM bursts serviced so far for a system packet **/
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unsigned int burstsServiced;
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BurstHelper(unsigned int _burstCount)
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: burstCount(_burstCount), burstsServiced(0)
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{ }
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};
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2012-09-21 17:48:13 +02:00
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/**
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* A DRAM packet stores packets along with the timestamp of when
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* the packet entered the queue, and also the decoded address.
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*/
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class DRAMPacket {
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public:
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/** When did request enter the controller */
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const Tick entryTime;
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/** When will request leave the controller */
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Tick readyTime;
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/** This comes from the outside world */
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const PacketPtr pkt;
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2013-11-01 16:56:19 +01:00
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const bool isRead;
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2012-09-21 17:48:13 +02:00
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/** Will be populated by address decoder */
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const uint8_t rank;
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2013-11-01 16:56:20 +01:00
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const uint8_t bank;
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2012-09-21 17:48:13 +02:00
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const uint16_t row;
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2013-08-19 09:52:30 +02:00
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2013-11-01 16:56:20 +01:00
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/**
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* Bank id is calculated considering banks in all the ranks
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* eg: 2 ranks each with 8 banks, then bankId = 0 --> rank0, bank0 and
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* bankId = 8 --> rank1, bank0
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*/
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const uint16_t bankId;
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2013-08-19 09:52:30 +02:00
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/**
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* The starting address of the DRAM packet.
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* This address could be unaligned to burst size boundaries. The
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* reason is to keep the address offset so we can accurately check
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* incoming read packets with packets in the write queue.
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*/
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2013-08-19 09:52:31 +02:00
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Addr addr;
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2013-08-19 09:52:30 +02:00
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/**
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* The size of this dram packet in bytes
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* It is always equal or smaller than DRAM burst size
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*/
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2013-08-19 09:52:31 +02:00
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unsigned int size;
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2013-08-19 09:52:30 +02:00
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/**
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* A pointer to the BurstHelper if this DRAMPacket is a split packet
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* If not a split packet (common case), this is set to NULL
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*/
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BurstHelper* burstHelper;
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2013-11-01 16:56:20 +01:00
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Bank& bankRef;
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2012-09-21 17:48:13 +02:00
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2013-11-01 16:56:20 +01:00
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DRAMPacket(PacketPtr _pkt, bool is_read, uint8_t _rank, uint8_t _bank,
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uint16_t _row, uint16_t bank_id, Addr _addr,
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unsigned int _size, Bank& bank_ref)
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2012-09-21 17:48:13 +02:00
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: entryTime(curTick()), readyTime(curTick()),
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2013-11-01 16:56:20 +01:00
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pkt(_pkt), isRead(is_read), rank(_rank), bank(_bank), row(_row),
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bankId(bank_id), addr(_addr), size(_size), burstHelper(NULL),
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bankRef(bank_ref)
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2012-09-21 17:48:13 +02:00
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{ }
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};
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/**
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* Bunch of things requires to setup "events" in gem5
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* When event "writeEvent" occurs for example, the method
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* processWriteEvent is called; no parameters are allowed
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* in these methods
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*/
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void processWriteEvent();
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EventWrapper<SimpleDRAM, &SimpleDRAM::processWriteEvent> writeEvent;
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void processRespondEvent();
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EventWrapper<SimpleDRAM, &SimpleDRAM::processRespondEvent> respondEvent;
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void processRefreshEvent();
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EventWrapper<SimpleDRAM, &SimpleDRAM::processRefreshEvent> refreshEvent;
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void processNextReqEvent();
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EventWrapper<SimpleDRAM,&SimpleDRAM::processNextReqEvent> nextReqEvent;
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/**
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* Check if the read queue has room for more entries
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*
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2013-08-19 09:52:30 +02:00
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* @param pktCount The number of entries needed in the read queue
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2012-09-21 17:48:13 +02:00
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* @return true if read queue is full, false otherwise
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*/
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2013-08-19 09:52:30 +02:00
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bool readQueueFull(unsigned int pktCount) const;
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2012-09-21 17:48:13 +02:00
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/**
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* Check if the write queue has room for more entries
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*
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2013-08-19 09:52:30 +02:00
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* @param pktCount The number of entries needed in the write queue
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2012-09-21 17:48:13 +02:00
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* @return true if write queue is full, false otherwise
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*/
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2013-08-19 09:52:30 +02:00
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bool writeQueueFull(unsigned int pktCount) const;
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2012-09-21 17:48:13 +02:00
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/**
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* When a new read comes in, first check if the write q has a
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* pending request to the same address.\ If not, decode the
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2013-08-19 09:52:30 +02:00
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* address to populate rank/bank/row, create one or mutliple
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* "dram_pkt", and push them to the back of the read queue.\
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* If this is the only
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2012-09-21 17:48:13 +02:00
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* read request in the system, schedule an event to start
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* servicing it.
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*
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* @param pkt The request packet from the outside world
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2013-08-19 09:52:30 +02:00
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* @param pktCount The number of DRAM bursts the pkt
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* translate to. If pkt size is larger then one full burst,
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* then pktCount is greater than one.
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2012-09-21 17:48:13 +02:00
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*/
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2013-08-19 09:52:30 +02:00
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void addToReadQueue(PacketPtr pkt, unsigned int pktCount);
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2012-09-21 17:48:13 +02:00
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/**
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* Decode the incoming pkt, create a dram_pkt and push to the
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* back of the write queue. \If the write q length is more than
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* the threshold specified by the user, ie the queue is beginning
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* to get full, stop reads, and start draining writes.
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*
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* @param pkt The request packet from the outside world
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2013-08-19 09:52:30 +02:00
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* @param pktCount The number of DRAM bursts the pkt
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* translate to. If pkt size is larger then one full burst,
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* then pktCount is greater than one.
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2012-09-21 17:48:13 +02:00
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*/
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2013-08-19 09:52:30 +02:00
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void addToWriteQueue(PacketPtr pkt, unsigned int pktCount);
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2012-09-21 17:48:13 +02:00
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/**
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* Actually do the DRAM access - figure out the latency it
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* will take to service the req based on bank state, channel state etc
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* and then update those states to account for this request.\ Based
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* on this, update the packet's "readyTime" and move it to the
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* response q from where it will eventually go back to the outside
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* world.
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*
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* @param pkt The DRAM packet created from the outside world pkt
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*/
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void doDRAMAccess(DRAMPacket* dram_pkt);
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/**
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* Check when the channel is free to turnaround, add turnaround
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* delay and schedule a whole bunch of writes.
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*/
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void triggerWrites();
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/**
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* When a packet reaches its "readyTime" in the response Q,
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* use the "access()" method in AbstractMemory to actually
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* create the response packet, and send it back to the outside
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* world requestor.
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*
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* @param pkt The packet from the outside world
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2013-05-30 18:54:12 +02:00
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* @param static_latency Static latency to add before sending the packet
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2012-09-21 17:48:13 +02:00
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*/
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2013-05-30 18:54:12 +02:00
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void accessAndRespond(PacketPtr pkt, Tick static_latency);
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2012-09-21 17:48:13 +02:00
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/**
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* Address decoder to figure out physical mapping onto ranks,
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2013-08-19 09:52:30 +02:00
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* banks, and rows. This function is called multiple times on the same
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* system packet if the pakcet is larger than burst of the memory. The
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* dramPktAddr is used for the offset within the packet.
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2012-09-21 17:48:13 +02:00
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*
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* @param pkt The packet from the outside world
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2013-08-19 09:52:30 +02:00
|
|
|
* @param dramPktAddr The starting address of the DRAM packet
|
|
|
|
* @param size The size of the DRAM packet in bytes
|
2013-11-01 16:56:19 +01:00
|
|
|
* @param isRead Is the request for a read or a write to DRAM
|
2012-09-21 17:48:13 +02:00
|
|
|
* @return A DRAMPacket pointer with the decoded information
|
|
|
|
*/
|
2013-11-01 16:56:19 +01:00
|
|
|
DRAMPacket* decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned int size, bool isRead);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
/**
|
2013-03-01 19:20:24 +01:00
|
|
|
* The memory schduler/arbiter - picks which read request needs to
|
|
|
|
* go next, based on the specified policy such as FCFS or FR-FCFS
|
|
|
|
* and moves it to the head of the read queue.
|
2012-09-21 17:48:13 +02:00
|
|
|
*
|
2013-03-01 19:20:24 +01:00
|
|
|
* @return True if a request was chosen and false if queue is empty
|
2012-09-21 17:48:13 +02:00
|
|
|
*/
|
2013-03-01 19:20:24 +01:00
|
|
|
bool chooseNextRead();
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
/**
|
|
|
|
* Calls chooseNextReq() to pick the right request, then calls
|
|
|
|
* doDRAMAccess on that request in order to actually service
|
|
|
|
* that request
|
|
|
|
*/
|
|
|
|
void scheduleNextReq();
|
|
|
|
|
|
|
|
/**
|
|
|
|
*Looks at the state of the banks, channels, row buffer hits etc
|
|
|
|
* to estimate how long a request will take to complete.
|
|
|
|
*
|
|
|
|
* @param dram_pkt The request for which we want to estimate latency
|
|
|
|
* @param inTime The tick at which you want to probe the memory
|
|
|
|
*
|
|
|
|
* @return A pair of ticks, one indicating how many ticks *after*
|
|
|
|
* inTime the request require, and the other indicating how
|
|
|
|
* much of that was just the bank access time, ignoring the
|
|
|
|
* ticks spent simply waiting for resources to become free
|
|
|
|
*/
|
|
|
|
std::pair<Tick, Tick> estimateLatency(DRAMPacket* dram_pkt, Tick inTime);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Move the request at the head of the read queue to the response
|
|
|
|
* queue, sorting by readyTime.\ If it is the only packet in the
|
|
|
|
* response queue, schedule a respond event to send it back to the
|
|
|
|
* outside world
|
|
|
|
*/
|
|
|
|
void moveToRespQ();
|
|
|
|
|
|
|
|
/**
|
2013-03-01 19:20:24 +01:00
|
|
|
* Scheduling policy within the write queue
|
2012-09-21 17:48:13 +02:00
|
|
|
*/
|
|
|
|
void chooseNextWrite();
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Looking at all banks, determine the moment in time when they
|
|
|
|
* are all free.
|
|
|
|
*
|
|
|
|
* @return The tick when all banks are free
|
|
|
|
*/
|
|
|
|
Tick maxBankFreeAt() const;
|
|
|
|
|
2013-11-01 16:56:20 +01:00
|
|
|
/**
|
|
|
|
* Find which are the earliest available banks for the enqueued
|
|
|
|
* requests. Assumes maximum of 64 banks per DIMM
|
|
|
|
*
|
|
|
|
* @param Queued requests to consider
|
|
|
|
* @return One-hot encoded mask of bank indices
|
|
|
|
*/
|
|
|
|
uint64_t minBankFreeAt(const std::deque<DRAMPacket*>& queue) const;
|
2013-01-31 13:49:14 +01:00
|
|
|
|
|
|
|
/**
|
|
|
|
* Keep track of when row activations happen, in order to enforce
|
|
|
|
* the maximum number of activations in the activation window. The
|
|
|
|
* method updates the time that the banks become available based
|
|
|
|
* on the current limits.
|
|
|
|
*/
|
|
|
|
void recordActivate(Tick act_tick);
|
|
|
|
|
2012-09-21 17:48:13 +02:00
|
|
|
void printParams() const;
|
|
|
|
void printQs() const;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* The controller's main read and write queues
|
|
|
|
*/
|
2013-08-19 09:52:32 +02:00
|
|
|
std::deque<DRAMPacket*> readQueue;
|
|
|
|
std::deque<DRAMPacket*> writeQueue;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
/**
|
|
|
|
* Response queue where read packets wait after we're done working
|
2013-03-01 19:20:24 +01:00
|
|
|
* with them, but it's not time to send the response yet. The
|
|
|
|
* responses are stored seperately mostly to keep the code clean
|
|
|
|
* and help with events scheduling. For all logical purposes such
|
|
|
|
* as sizing the read queue, this and the main read queue need to
|
|
|
|
* be added together.
|
2012-09-21 17:48:13 +02:00
|
|
|
*/
|
2013-08-19 09:52:32 +02:00
|
|
|
std::deque<DRAMPacket*> respQueue;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2013-03-01 19:20:24 +01:00
|
|
|
/**
|
|
|
|
* If we need to drain, keep the drain manager around until we're
|
|
|
|
* done here.
|
2012-09-21 17:48:13 +02:00
|
|
|
*/
|
2012-11-02 17:32:01 +01:00
|
|
|
DrainManager *drainManager;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
/**
|
|
|
|
* Multi-dimensional vector of banks, first dimension is ranks,
|
|
|
|
* second is bank
|
|
|
|
*/
|
|
|
|
std::vector<std::vector<Bank> > banks;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* The following are basic design parameters of the memory
|
2013-08-19 09:52:30 +02:00
|
|
|
* controller, and are initialized based on parameter values.
|
|
|
|
* The rowsPerBank is determined based on the capacity, number of
|
|
|
|
* ranks and banks, the burst size, and the row buffer size.
|
|
|
|
*/
|
|
|
|
const uint32_t deviceBusWidth;
|
|
|
|
const uint32_t burstLength;
|
|
|
|
const uint32_t deviceRowBufferSize;
|
|
|
|
const uint32_t devicesPerRank;
|
|
|
|
const uint32_t burstSize;
|
|
|
|
const uint32_t rowBufferSize;
|
2012-09-21 17:48:13 +02:00
|
|
|
const uint32_t ranksPerChannel;
|
|
|
|
const uint32_t banksPerRank;
|
2013-03-01 19:20:22 +01:00
|
|
|
const uint32_t channels;
|
2012-09-21 17:48:13 +02:00
|
|
|
uint32_t rowsPerBank;
|
2013-08-19 09:52:30 +02:00
|
|
|
uint32_t columnsPerRowBuffer;
|
2012-09-21 17:48:13 +02:00
|
|
|
const uint32_t readBufferSize;
|
|
|
|
const uint32_t writeBufferSize;
|
|
|
|
const double writeThresholdPerc;
|
|
|
|
uint32_t writeThreshold;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Basic memory timing parameters initialized based on parameter
|
|
|
|
* values.
|
|
|
|
*/
|
|
|
|
const Tick tWTR;
|
|
|
|
const Tick tBURST;
|
|
|
|
const Tick tRCD;
|
|
|
|
const Tick tCL;
|
|
|
|
const Tick tRP;
|
2013-11-01 16:56:16 +01:00
|
|
|
const Tick tRAS;
|
2012-09-21 17:48:13 +02:00
|
|
|
const Tick tRFC;
|
|
|
|
const Tick tREFI;
|
2013-01-31 13:49:14 +01:00
|
|
|
const Tick tXAW;
|
|
|
|
const uint32_t activationLimit;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
/**
|
|
|
|
* Memory controller configuration initialized based on parameter
|
|
|
|
* values.
|
|
|
|
*/
|
|
|
|
Enums::MemSched memSchedPolicy;
|
|
|
|
Enums::AddrMap addrMapping;
|
|
|
|
Enums::PageManage pageMgmt;
|
|
|
|
|
2013-05-30 18:54:12 +02:00
|
|
|
/**
|
|
|
|
* Pipeline latency of the controller frontend. The frontend
|
|
|
|
* contribution is added to writes (that complete when they are in
|
|
|
|
* the write buffer) and reads that are serviced the write buffer.
|
|
|
|
*/
|
|
|
|
const Tick frontendLatency;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Pipeline latency of the backend and PHY. Along with the
|
|
|
|
* frontend contribution, this latency is added to reads serviced
|
|
|
|
* by the DRAM.
|
|
|
|
*/
|
|
|
|
const Tick backendLatency;
|
|
|
|
|
2012-09-21 17:48:13 +02:00
|
|
|
/**
|
|
|
|
* Till when has the main data bus been spoken for already?
|
|
|
|
*/
|
|
|
|
Tick busBusyUntil;
|
|
|
|
|
|
|
|
Tick writeStartTime;
|
|
|
|
Tick prevArrival;
|
|
|
|
int numReqs;
|
|
|
|
|
|
|
|
// All statistics that the model needs to capture
|
|
|
|
Stats::Scalar readReqs;
|
|
|
|
Stats::Scalar writeReqs;
|
2013-08-19 09:52:30 +02:00
|
|
|
Stats::Scalar readBursts;
|
|
|
|
Stats::Scalar writeBursts;
|
2012-09-21 17:48:13 +02:00
|
|
|
Stats::Scalar bytesRead;
|
|
|
|
Stats::Scalar bytesWritten;
|
|
|
|
Stats::Scalar bytesConsumedRd;
|
|
|
|
Stats::Scalar bytesConsumedWr;
|
|
|
|
Stats::Scalar servicedByWrQ;
|
|
|
|
Stats::Scalar neitherReadNorWrite;
|
|
|
|
Stats::Vector perBankRdReqs;
|
|
|
|
Stats::Vector perBankWrReqs;
|
|
|
|
Stats::Scalar numRdRetry;
|
|
|
|
Stats::Scalar numWrRetry;
|
|
|
|
Stats::Scalar totGap;
|
|
|
|
Stats::Vector readPktSize;
|
|
|
|
Stats::Vector writePktSize;
|
|
|
|
Stats::Vector rdQLenPdf;
|
|
|
|
Stats::Vector wrQLenPdf;
|
2013-05-30 18:54:13 +02:00
|
|
|
Stats::Histogram bytesPerActivate;
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
// Latencies summed over all requests
|
|
|
|
Stats::Scalar totQLat;
|
|
|
|
Stats::Scalar totMemAccLat;
|
|
|
|
Stats::Scalar totBusLat;
|
|
|
|
Stats::Scalar totBankLat;
|
|
|
|
|
|
|
|
// Average latencies per request
|
|
|
|
Stats::Formula avgQLat;
|
|
|
|
Stats::Formula avgBankLat;
|
|
|
|
Stats::Formula avgBusLat;
|
|
|
|
Stats::Formula avgMemAccLat;
|
|
|
|
|
|
|
|
// Average bandwidth
|
|
|
|
Stats::Formula avgRdBW;
|
|
|
|
Stats::Formula avgWrBW;
|
|
|
|
Stats::Formula avgConsumedRdBW;
|
|
|
|
Stats::Formula avgConsumedWrBW;
|
|
|
|
Stats::Formula peakBW;
|
|
|
|
Stats::Formula busUtil;
|
|
|
|
|
|
|
|
// Average queue lengths
|
|
|
|
Stats::Average avgRdQLen;
|
|
|
|
Stats::Average avgWrQLen;
|
|
|
|
|
|
|
|
// Row hit count and rate
|
|
|
|
Stats::Scalar readRowHits;
|
|
|
|
Stats::Scalar writeRowHits;
|
|
|
|
Stats::Formula readRowHitRate;
|
|
|
|
Stats::Formula writeRowHitRate;
|
|
|
|
Stats::Formula avgGap;
|
|
|
|
|
2012-11-02 17:50:16 +01:00
|
|
|
/** @todo this is a temporary workaround until the 4-phase code is
|
|
|
|
* committed. upstream caches needs this packet until true is returned, so
|
|
|
|
* hold onto it for deletion until a subsequent call
|
|
|
|
*/
|
|
|
|
std::vector<PacketPtr> pendingDelete;
|
|
|
|
|
2012-09-21 17:48:13 +02:00
|
|
|
public:
|
|
|
|
|
|
|
|
void regStats();
|
|
|
|
|
|
|
|
SimpleDRAM(const SimpleDRAMParams* p);
|
|
|
|
|
2012-11-02 17:32:01 +01:00
|
|
|
unsigned int drain(DrainManager* dm);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
2012-10-15 14:12:35 +02:00
|
|
|
virtual BaseSlavePort& getSlavePort(const std::string& if_name,
|
|
|
|
PortID idx = InvalidPortID);
|
2012-09-21 17:48:13 +02:00
|
|
|
|
|
|
|
virtual void init();
|
|
|
|
virtual void startup();
|
|
|
|
|
|
|
|
protected:
|
|
|
|
|
|
|
|
Tick recvAtomic(PacketPtr pkt);
|
|
|
|
void recvFunctional(PacketPtr pkt);
|
|
|
|
bool recvTimingReq(PacketPtr pkt);
|
|
|
|
|
|
|
|
};
|
|
|
|
|
|
|
|
#endif //__MEM_SIMPLE_DRAM_HH__
|