2010-01-30 05:29:17 +01:00
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/*
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
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* Copyright (c) 2012 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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2010-01-30 05:29:17 +01:00
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* Copyright (c) 2009 Advanced Micro Devices, Inc.
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2012-01-23 18:07:14 +01:00
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* Copyright (c) 2011 Mark D. Hill and David A. Wood
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2010-01-30 05:29:17 +01:00
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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2010-08-24 21:07:22 +02:00
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#include "cpu/testers/rubytest/RubyTester.hh"
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2012-01-11 20:48:48 +01:00
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#include "debug/Config.hh"
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2012-08-15 16:38:08 +02:00
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#include "debug/Drain.hh"
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2011-04-15 19:44:32 +02:00
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#include "debug/Ruby.hh"
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2011-07-01 02:49:26 +02:00
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#include "mem/protocol/AccessPermission.hh"
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2010-01-30 05:29:17 +01:00
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#include "mem/ruby/slicc_interface/AbstractController.hh"
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2010-03-23 02:43:53 +01:00
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#include "mem/ruby/system/RubyPort.hh"
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2012-03-30 15:42:36 +02:00
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#include "sim/system.hh"
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2009-07-07 00:49:47 +02:00
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2010-01-30 05:29:17 +01:00
|
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|
RubyPort::RubyPort(const Params *p)
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
: MemObject(p), m_version(p->version), m_controller(NULL),
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m_mandatory_q_ptr(NULL),
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pio_port(csprintf("%s-pio-port", name()), this),
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m_usingRubyTester(p->using_ruby_tester), m_request_cnt(0),
|
2012-03-30 15:42:36 +02:00
|
|
|
drainEvent(NULL), ruby_system(p->ruby_system), system(p->system),
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
waitingOnSequencer(false), access_phys_mem(p->access_phys_mem)
|
2010-01-30 05:29:17 +01:00
|
|
|
{
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|
|
|
assert(m_version != -1);
|
|
|
|
|
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
// create the slave ports based on the number of connected ports
|
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|
for (size_t i = 0; i < p->port_slave_connection_count; ++i) {
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slave_ports.push_back(new M5Port(csprintf("%s-slave%d", name(), i),
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this, ruby_system, access_phys_mem));
|
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|
|
|
}
|
2012-01-11 20:48:48 +01:00
|
|
|
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
// create the master ports based on the number of connected ports
|
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|
|
|
for (size_t i = 0; i < p->port_master_connection_count; ++i) {
|
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master_ports.push_back(new PioPort(csprintf("%s-master%d", name(), i),
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this));
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}
|
2010-01-30 05:29:17 +01:00
|
|
|
}
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|
2010-03-23 02:43:53 +01:00
|
|
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void
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RubyPort::init()
|
2010-01-30 05:29:19 +01:00
|
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{
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assert(m_controller != NULL);
|
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m_mandatory_q_ptr = m_controller->getMandatoryQueue();
|
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|
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}
|
|
|
|
|
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
MasterPort &
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|
RubyPort::getMasterPort(const std::string &if_name, int idx)
|
2010-01-30 05:29:17 +01:00
|
|
|
{
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
if (if_name == "pio_port") {
|
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return pio_port;
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}
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2012-02-13 12:43:09 +01:00
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|
// used by the x86 CPUs to connect the interrupt PIO and interrupt slave
|
|
|
|
|
// port
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
if (if_name != "master") {
|
|
|
|
|
// pass it along to our super class
|
|
|
|
|
return MemObject::getMasterPort(if_name, idx);
|
|
|
|
|
} else {
|
|
|
|
|
if (idx >= static_cast<int>(master_ports.size())) {
|
|
|
|
|
panic("RubyPort::getMasterPort: unknown index %d\n", idx);
|
|
|
|
|
}
|
2012-02-13 12:43:09 +01:00
|
|
|
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
return *master_ports[idx];
|
2012-02-13 12:43:09 +01:00
|
|
|
}
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
}
|
2012-02-13 12:43:09 +01:00
|
|
|
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
SlavePort &
|
|
|
|
|
RubyPort::getSlavePort(const std::string &if_name, int idx)
|
|
|
|
|
{
|
|
|
|
|
// used by the CPUs to connect the caches to the interconnect, and
|
|
|
|
|
// for the x86 case also the interrupt master
|
|
|
|
|
if (if_name != "slave") {
|
|
|
|
|
// pass it along to our super class
|
|
|
|
|
return MemObject::getSlavePort(if_name, idx);
|
|
|
|
|
} else {
|
|
|
|
|
if (idx >= static_cast<int>(slave_ports.size())) {
|
|
|
|
|
panic("RubyPort::getSlavePort: unknown index %d\n", idx);
|
|
|
|
|
}
|
2010-03-23 02:43:53 +01:00
|
|
|
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
return *slave_ports[idx];
|
2010-03-23 02:43:53 +01:00
|
|
|
}
|
2010-01-30 05:29:17 +01:00
|
|
|
}
|
2010-01-30 05:29:19 +01:00
|
|
|
|
2010-03-23 02:43:53 +01:00
|
|
|
RubyPort::PioPort::PioPort(const std::string &_name,
|
2010-01-30 05:29:19 +01:00
|
|
|
RubyPort *_port)
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
: QueuedMasterPort(_name, _port, queue), queue(*_port, *this),
|
|
|
|
|
ruby_port(_port)
|
2010-01-30 05:29:19 +01:00
|
|
|
{
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
DPRINTF(RubyPort, "creating master port on ruby sequencer %s\n", _name);
|
2010-01-30 05:29:19 +01:00
|
|
|
}
|
|
|
|
|
|
2011-07-01 02:49:26 +02:00
|
|
|
RubyPort::M5Port::M5Port(const std::string &_name, RubyPort *_port,
|
|
|
|
|
RubySystem *_system, bool _access_phys_mem)
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
: QueuedSlavePort(_name, _port, queue), queue(*_port, *this),
|
2012-03-22 11:36:27 +01:00
|
|
|
ruby_port(_port), ruby_system(_system),
|
|
|
|
|
_onRetryList(false), access_phys_mem(_access_phys_mem)
|
2010-01-30 05:29:19 +01:00
|
|
|
{
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
DPRINTF(RubyPort, "creating slave port on ruby sequencer %s\n", _name);
|
2010-01-30 05:29:19 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
Tick
|
|
|
|
|
RubyPort::M5Port::recvAtomic(PacketPtr pkt)
|
|
|
|
|
{
|
|
|
|
|
panic("RubyPort::M5Port::recvAtomic() not implemented!\n");
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
bool
|
MEM: Separate requests and responses for timing accesses
This patch moves send/recvTiming and send/recvTimingSnoop from the
Port base class to the MasterPort and SlavePort, and also splits them
into separate member functions for requests and responses:
send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq,
send/recvTimingSnoopResp. A master port sends requests and receives
responses, and also receives snoop requests and sends snoop
responses. A slave port has the reciprocal behaviour as it receives
requests and sends responses, and sends snoop requests and receives
snoop responses.
For all MemObjects that have only master ports or slave ports (but not
both), e.g. a CPU, or a PIO device, this patch merely adds more
clarity to what kind of access is taking place. For example, a CPU
port used to call sendTiming, and will now call
sendTimingReq. Similarly, a response previously came back through
recvTiming, which is now recvTimingResp. For the modules that have
both master and slave ports, e.g. the bus, the behaviour was
previously relying on branches based on pkt->isRequest(), and this is
now replaced with a direct call to the apprioriate member function
depending on the type of access. Please note that send/recvRetry is
still shared by all the timing accessors and remains in the Port base
class for now (to maintain the current bus functionality and avoid
changing the statistics of all regressions).
The packet queue is split into a MasterPort and SlavePort version to
facilitate the use of the new timing accessors. All uses of the
PacketQueue are updated accordingly.
With this patch, the type of packet (request or response) is now well
defined for each type of access, and asserts on pkt->isRequest() and
pkt->isResponse() are now moved to the appropriate send member
functions. It is also worth noting that sendTimingSnoopReq no longer
returns a boolean, as the semantics do not alow snoop requests to be
rejected or stalled. All these assumptions are now excplicitly part of
the port interface itself.
2012-05-01 19:40:42 +02:00
|
|
|
RubyPort::PioPort::recvTimingResp(PacketPtr pkt)
|
2010-01-30 05:29:19 +01:00
|
|
|
{
|
2010-03-23 02:43:53 +01:00
|
|
|
// In FS mode, ruby memory will receive pio responses from devices
|
|
|
|
|
// and it must forward these responses back to the particular CPU.
|
2011-03-19 22:17:48 +01:00
|
|
|
DPRINTF(RubyPort, "Pio response for address %#x\n", pkt->getAddr());
|
2010-01-30 05:29:19 +01:00
|
|
|
|
|
|
|
|
// First we must retrieve the request port from the sender State
|
2010-03-23 02:43:53 +01:00
|
|
|
RubyPort::SenderState *senderState =
|
2010-01-30 05:29:19 +01:00
|
|
|
safe_cast<RubyPort::SenderState *>(pkt->senderState);
|
|
|
|
|
M5Port *port = senderState->port;
|
|
|
|
|
assert(port != NULL);
|
2010-03-23 02:43:53 +01:00
|
|
|
|
2010-01-30 05:29:19 +01:00
|
|
|
// pop the sender state from the packet
|
|
|
|
|
pkt->senderState = senderState->saved;
|
|
|
|
|
delete senderState;
|
2010-03-23 02:43:53 +01:00
|
|
|
|
MEM: Separate requests and responses for timing accesses
This patch moves send/recvTiming and send/recvTimingSnoop from the
Port base class to the MasterPort and SlavePort, and also splits them
into separate member functions for requests and responses:
send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq,
send/recvTimingSnoopResp. A master port sends requests and receives
responses, and also receives snoop requests and sends snoop
responses. A slave port has the reciprocal behaviour as it receives
requests and sends responses, and sends snoop requests and receives
snoop responses.
For all MemObjects that have only master ports or slave ports (but not
both), e.g. a CPU, or a PIO device, this patch merely adds more
clarity to what kind of access is taking place. For example, a CPU
port used to call sendTiming, and will now call
sendTimingReq. Similarly, a response previously came back through
recvTiming, which is now recvTimingResp. For the modules that have
both master and slave ports, e.g. the bus, the behaviour was
previously relying on branches based on pkt->isRequest(), and this is
now replaced with a direct call to the apprioriate member function
depending on the type of access. Please note that send/recvRetry is
still shared by all the timing accessors and remains in the Port base
class for now (to maintain the current bus functionality and avoid
changing the statistics of all regressions).
The packet queue is split into a MasterPort and SlavePort version to
facilitate the use of the new timing accessors. All uses of the
PacketQueue are updated accordingly.
With this patch, the type of packet (request or response) is now well
defined for each type of access, and asserts on pkt->isRequest() and
pkt->isResponse() are now moved to the appropriate send member
functions. It is also worth noting that sendTimingSnoopReq no longer
returns a boolean, as the semantics do not alow snoop requests to be
rejected or stalled. All these assumptions are now excplicitly part of
the port interface itself.
2012-05-01 19:40:42 +02:00
|
|
|
port->sendTimingResp(pkt);
|
2010-03-23 02:43:53 +01:00
|
|
|
|
2010-01-30 05:29:19 +01:00
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool
|
MEM: Separate requests and responses for timing accesses
This patch moves send/recvTiming and send/recvTimingSnoop from the
Port base class to the MasterPort and SlavePort, and also splits them
into separate member functions for requests and responses:
send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq,
send/recvTimingSnoopResp. A master port sends requests and receives
responses, and also receives snoop requests and sends snoop
responses. A slave port has the reciprocal behaviour as it receives
requests and sends responses, and sends snoop requests and receives
snoop responses.
For all MemObjects that have only master ports or slave ports (but not
both), e.g. a CPU, or a PIO device, this patch merely adds more
clarity to what kind of access is taking place. For example, a CPU
port used to call sendTiming, and will now call
sendTimingReq. Similarly, a response previously came back through
recvTiming, which is now recvTimingResp. For the modules that have
both master and slave ports, e.g. the bus, the behaviour was
previously relying on branches based on pkt->isRequest(), and this is
now replaced with a direct call to the apprioriate member function
depending on the type of access. Please note that send/recvRetry is
still shared by all the timing accessors and remains in the Port base
class for now (to maintain the current bus functionality and avoid
changing the statistics of all regressions).
The packet queue is split into a MasterPort and SlavePort version to
facilitate the use of the new timing accessors. All uses of the
PacketQueue are updated accordingly.
With this patch, the type of packet (request or response) is now well
defined for each type of access, and asserts on pkt->isRequest() and
pkt->isResponse() are now moved to the appropriate send member
functions. It is also worth noting that sendTimingSnoopReq no longer
returns a boolean, as the semantics do not alow snoop requests to be
rejected or stalled. All these assumptions are now excplicitly part of
the port interface itself.
2012-05-01 19:40:42 +02:00
|
|
|
RubyPort::M5Port::recvTimingReq(PacketPtr pkt)
|
2010-01-30 05:29:19 +01:00
|
|
|
{
|
2011-03-19 22:17:48 +01:00
|
|
|
DPRINTF(RubyPort,
|
2010-03-23 02:43:53 +01:00
|
|
|
"Timing access caught for address %#x\n", pkt->getAddr());
|
2010-01-30 05:29:19 +01:00
|
|
|
|
MEM: Separate requests and responses for timing accesses
This patch moves send/recvTiming and send/recvTimingSnoop from the
Port base class to the MasterPort and SlavePort, and also splits them
into separate member functions for requests and responses:
send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq,
send/recvTimingSnoopResp. A master port sends requests and receives
responses, and also receives snoop requests and sends snoop
responses. A slave port has the reciprocal behaviour as it receives
requests and sends responses, and sends snoop requests and receives
snoop responses.
For all MemObjects that have only master ports or slave ports (but not
both), e.g. a CPU, or a PIO device, this patch merely adds more
clarity to what kind of access is taking place. For example, a CPU
port used to call sendTiming, and will now call
sendTimingReq. Similarly, a response previously came back through
recvTiming, which is now recvTimingResp. For the modules that have
both master and slave ports, e.g. the bus, the behaviour was
previously relying on branches based on pkt->isRequest(), and this is
now replaced with a direct call to the apprioriate member function
depending on the type of access. Please note that send/recvRetry is
still shared by all the timing accessors and remains in the Port base
class for now (to maintain the current bus functionality and avoid
changing the statistics of all regressions).
The packet queue is split into a MasterPort and SlavePort version to
facilitate the use of the new timing accessors. All uses of the
PacketQueue are updated accordingly.
With this patch, the type of packet (request or response) is now well
defined for each type of access, and asserts on pkt->isRequest() and
pkt->isResponse() are now moved to the appropriate send member
functions. It is also worth noting that sendTimingSnoopReq no longer
returns a boolean, as the semantics do not alow snoop requests to be
rejected or stalled. All these assumptions are now excplicitly part of
the port interface itself.
2012-05-01 19:40:42 +02:00
|
|
|
//dsm: based on SimpleTimingPort::recvTimingReq(pkt);
|
2010-01-30 05:29:19 +01:00
|
|
|
|
2010-03-23 02:43:53 +01:00
|
|
|
// The received packets should only be M5 requests, which should never
|
|
|
|
|
// get nacked. There used to be code to hanldle nacks here, but
|
|
|
|
|
// I'm pretty sure it didn't work correctly with the drain code,
|
2010-01-30 05:29:19 +01:00
|
|
|
// so that would need to be fixed if we ever added it back.
|
|
|
|
|
|
|
|
|
|
if (pkt->memInhibitAsserted()) {
|
|
|
|
|
warn("memInhibitAsserted???");
|
|
|
|
|
// snooper will supply based on copy of packet
|
|
|
|
|
// still target's responsibility to delete packet
|
|
|
|
|
delete pkt;
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
|
2010-01-30 05:29:33 +01:00
|
|
|
// Save the port in the sender state object to be used later to
|
|
|
|
|
// route the response
|
|
|
|
|
pkt->senderState = new SenderState(this, pkt->senderState);
|
|
|
|
|
|
2010-01-30 05:29:19 +01:00
|
|
|
// Check for pio requests and directly send them to the dedicated
|
|
|
|
|
// pio port.
|
|
|
|
|
if (!isPhysMemAddress(pkt->getAddr())) {
|
2012-02-24 17:43:53 +01:00
|
|
|
assert(ruby_port->pio_port.isConnected());
|
2011-03-19 22:17:48 +01:00
|
|
|
DPRINTF(RubyPort,
|
2010-01-30 05:29:33 +01:00
|
|
|
"Request for address 0x%#x is assumed to be a pio request\n",
|
|
|
|
|
pkt->getAddr());
|
2010-01-30 05:29:19 +01:00
|
|
|
|
2012-08-22 17:39:56 +02:00
|
|
|
// send next cycle
|
2012-09-10 19:21:01 +02:00
|
|
|
ruby_port->pio_port.schedTimingReq(pkt,
|
|
|
|
|
curTick() + g_system_ptr->clockPeriod());
|
2012-08-22 17:39:56 +02:00
|
|
|
return true;
|
2010-01-30 05:29:19 +01:00
|
|
|
}
|
|
|
|
|
|
2011-11-15 00:44:35 +01:00
|
|
|
assert(Address(pkt->getAddr()).getOffset() + pkt->getSize() <=
|
|
|
|
|
RubySystem::getBlockSizeBytes());
|
2011-02-07 07:14:18 +01:00
|
|
|
|
2010-01-30 05:29:19 +01:00
|
|
|
// Submit the ruby request
|
2011-11-15 00:44:35 +01:00
|
|
|
RequestStatus requestStatus = ruby_port->makeRequest(pkt);
|
2010-03-22 05:22:21 +01:00
|
|
|
|
2010-08-20 20:46:12 +02:00
|
|
|
// If the request successfully issued then we should return true.
|
2010-03-22 05:22:21 +01:00
|
|
|
// Otherwise, we need to delete the senderStatus we just created and return
|
|
|
|
|
// false.
|
2010-08-20 20:46:12 +02:00
|
|
|
if (requestStatus == RequestStatus_Issued) {
|
2011-03-19 22:17:48 +01:00
|
|
|
DPRINTF(RubyPort, "Request %#x issued\n", pkt->getAddr());
|
2010-01-30 05:29:33 +01:00
|
|
|
return true;
|
2010-01-30 05:29:19 +01:00
|
|
|
}
|
2010-03-22 05:22:21 +01:00
|
|
|
|
2011-02-07 07:14:18 +01:00
|
|
|
//
|
|
|
|
|
// Unless one is using the ruby tester, record the stalled M5 port for
|
|
|
|
|
// later retry when the sequencer becomes free.
|
|
|
|
|
//
|
|
|
|
|
if (!ruby_port->m_usingRubyTester) {
|
|
|
|
|
ruby_port->addToRetryList(this);
|
|
|
|
|
}
|
|
|
|
|
|
2011-03-19 22:17:48 +01:00
|
|
|
DPRINTF(RubyPort,
|
2011-02-07 07:14:18 +01:00
|
|
|
"Request for address %#x did not issue because %s\n",
|
2010-03-23 02:43:53 +01:00
|
|
|
pkt->getAddr(), RequestStatus_to_string(requestStatus));
|
|
|
|
|
|
2010-01-30 05:29:33 +01:00
|
|
|
SenderState* senderState = safe_cast<SenderState*>(pkt->senderState);
|
|
|
|
|
pkt->senderState = senderState->saved;
|
|
|
|
|
delete senderState;
|
|
|
|
|
return false;
|
2010-01-30 05:29:19 +01:00
|
|
|
}
|
|
|
|
|
|
2011-07-01 02:49:26 +02:00
|
|
|
bool
|
|
|
|
|
RubyPort::M5Port::doFunctionalRead(PacketPtr pkt)
|
|
|
|
|
{
|
|
|
|
|
Address address(pkt->getAddr());
|
|
|
|
|
Address line_address(address);
|
|
|
|
|
line_address.makeLineAddress();
|
|
|
|
|
|
2011-09-01 20:41:44 +02:00
|
|
|
AccessPermission access_perm = AccessPermission_NotPresent;
|
2011-07-01 02:49:26 +02:00
|
|
|
int num_controllers = ruby_system->m_abs_cntrl_vec.size();
|
|
|
|
|
|
|
|
|
|
DPRINTF(RubyPort, "Functional Read request for %s\n",address);
|
2011-09-01 20:41:44 +02:00
|
|
|
|
|
|
|
|
unsigned int num_ro = 0;
|
|
|
|
|
unsigned int num_rw = 0;
|
|
|
|
|
unsigned int num_busy = 0;
|
|
|
|
|
unsigned int num_backing_store = 0;
|
|
|
|
|
unsigned int num_invalid = 0;
|
|
|
|
|
|
|
|
|
|
// In this loop we count the number of controllers that have the given
|
|
|
|
|
// address in read only, read write and busy states.
|
|
|
|
|
for (int i = 0; i < num_controllers; ++i) {
|
|
|
|
|
access_perm = ruby_system->m_abs_cntrl_vec[i]->
|
|
|
|
|
getAccessPermission(line_address);
|
|
|
|
|
if (access_perm == AccessPermission_Read_Only)
|
|
|
|
|
num_ro++;
|
|
|
|
|
else if (access_perm == AccessPermission_Read_Write)
|
|
|
|
|
num_rw++;
|
|
|
|
|
else if (access_perm == AccessPermission_Busy)
|
|
|
|
|
num_busy++;
|
|
|
|
|
else if (access_perm == AccessPermission_Backing_Store)
|
|
|
|
|
// See RubySlicc_Exports.sm for details, but Backing_Store is meant
|
|
|
|
|
// to represent blocks in memory *for Broadcast/Snooping protocols*,
|
|
|
|
|
// where memory has no idea whether it has an exclusive copy of data
|
|
|
|
|
// or not.
|
|
|
|
|
num_backing_store++;
|
|
|
|
|
else if (access_perm == AccessPermission_Invalid ||
|
|
|
|
|
access_perm == AccessPermission_NotPresent)
|
|
|
|
|
num_invalid++;
|
|
|
|
|
}
|
|
|
|
|
assert(num_rw <= 1);
|
|
|
|
|
|
2012-09-11 16:23:56 +02:00
|
|
|
uint8_t *data = pkt->getPtr<uint8_t>(true);
|
2011-09-01 20:41:44 +02:00
|
|
|
unsigned int size_in_bytes = pkt->getSize();
|
|
|
|
|
unsigned startByte = address.getAddress() - line_address.getAddress();
|
|
|
|
|
|
|
|
|
|
// This if case is meant to capture what happens in a Broadcast/Snoop
|
|
|
|
|
// protocol where the block does not exist in the cache hierarchy. You
|
|
|
|
|
// only want to read from the Backing_Store memory if there is no copy in
|
|
|
|
|
// the cache hierarchy, otherwise you want to try to read the RO or RW
|
|
|
|
|
// copies existing in the cache hierarchy (covered by the else statement).
|
|
|
|
|
// The reason is because the Backing_Store memory could easily be stale, if
|
|
|
|
|
// there are copies floating around the cache hierarchy, so you want to read
|
|
|
|
|
// it only if it's not in the cache hierarchy at all.
|
|
|
|
|
if (num_invalid == (num_controllers - 1) &&
|
|
|
|
|
num_backing_store == 1)
|
2011-07-01 02:49:26 +02:00
|
|
|
{
|
2011-09-01 20:41:44 +02:00
|
|
|
DPRINTF(RubyPort, "only copy in Backing_Store memory, read from it\n");
|
|
|
|
|
for (int i = 0; i < num_controllers; ++i) {
|
|
|
|
|
access_perm = ruby_system->m_abs_cntrl_vec[i]
|
|
|
|
|
->getAccessPermission(line_address);
|
|
|
|
|
if (access_perm == AccessPermission_Backing_Store) {
|
|
|
|
|
DataBlock& block = ruby_system->m_abs_cntrl_vec[i]
|
2011-07-01 02:49:26 +02:00
|
|
|
->getDataBlock(line_address);
|
|
|
|
|
|
2011-09-01 20:41:44 +02:00
|
|
|
DPRINTF(RubyPort, "reading from %s block %s\n",
|
|
|
|
|
ruby_system->m_abs_cntrl_vec[i]->name(), block);
|
|
|
|
|
for (unsigned i = 0; i < size_in_bytes; ++i) {
|
|
|
|
|
data[i] = block.getByte(i + startByte);
|
|
|
|
|
}
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
// In Broadcast/Snoop protocols, this covers if you know the block
|
|
|
|
|
// exists somewhere in the caching hierarchy, then you want to read any
|
|
|
|
|
// valid RO or RW block. In directory protocols, same thing, you want
|
|
|
|
|
// to read any valid readable copy of the block.
|
|
|
|
|
DPRINTF(RubyPort, "num_busy = %d, num_ro = %d, num_rw = %d\n",
|
|
|
|
|
num_busy, num_ro, num_rw);
|
|
|
|
|
// In this loop, we try to figure which controller has a read only or
|
|
|
|
|
// a read write copy of the given address. Any valid copy would suffice
|
|
|
|
|
// for a functional read.
|
|
|
|
|
for(int i = 0;i < num_controllers;++i) {
|
|
|
|
|
access_perm = ruby_system->m_abs_cntrl_vec[i]
|
|
|
|
|
->getAccessPermission(line_address);
|
|
|
|
|
if(access_perm == AccessPermission_Read_Only ||
|
|
|
|
|
access_perm == AccessPermission_Read_Write)
|
2011-07-01 02:49:26 +02:00
|
|
|
{
|
2011-09-01 20:41:44 +02:00
|
|
|
DataBlock& block = ruby_system->m_abs_cntrl_vec[i]
|
|
|
|
|
->getDataBlock(line_address);
|
|
|
|
|
|
|
|
|
|
DPRINTF(RubyPort, "reading from %s block %s\n",
|
|
|
|
|
ruby_system->m_abs_cntrl_vec[i]->name(), block);
|
|
|
|
|
for (unsigned i = 0; i < size_in_bytes; ++i) {
|
|
|
|
|
data[i] = block.getByte(i + startByte);
|
|
|
|
|
}
|
|
|
|
|
return true;
|
2011-07-01 02:49:26 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool
|
|
|
|
|
RubyPort::M5Port::doFunctionalWrite(PacketPtr pkt)
|
|
|
|
|
{
|
|
|
|
|
Address addr(pkt->getAddr());
|
|
|
|
|
Address line_addr = line_address(addr);
|
2011-09-01 20:41:44 +02:00
|
|
|
AccessPermission access_perm = AccessPermission_NotPresent;
|
2011-07-01 02:49:26 +02:00
|
|
|
int num_controllers = ruby_system->m_abs_cntrl_vec.size();
|
|
|
|
|
|
|
|
|
|
DPRINTF(RubyPort, "Functional Write request for %s\n",addr);
|
|
|
|
|
|
|
|
|
|
unsigned int num_ro = 0;
|
|
|
|
|
unsigned int num_rw = 0;
|
|
|
|
|
unsigned int num_busy = 0;
|
2011-09-01 20:41:44 +02:00
|
|
|
unsigned int num_backing_store = 0;
|
|
|
|
|
unsigned int num_invalid = 0;
|
2011-07-01 02:49:26 +02:00
|
|
|
|
|
|
|
|
// In this loop we count the number of controllers that have the given
|
|
|
|
|
// address in read only, read write and busy states.
|
2011-09-01 20:41:44 +02:00
|
|
|
for(int i = 0;i < num_controllers;++i) {
|
|
|
|
|
access_perm = ruby_system->m_abs_cntrl_vec[i]->
|
2011-07-01 02:49:26 +02:00
|
|
|
getAccessPermission(line_addr);
|
2011-09-01 20:41:44 +02:00
|
|
|
if (access_perm == AccessPermission_Read_Only)
|
|
|
|
|
num_ro++;
|
|
|
|
|
else if (access_perm == AccessPermission_Read_Write)
|
|
|
|
|
num_rw++;
|
|
|
|
|
else if (access_perm == AccessPermission_Busy)
|
|
|
|
|
num_busy++;
|
|
|
|
|
else if (access_perm == AccessPermission_Backing_Store)
|
|
|
|
|
// See RubySlicc_Exports.sm for details, but Backing_Store is meant
|
|
|
|
|
// to represent blocks in memory *for Broadcast/Snooping protocols*,
|
|
|
|
|
// where memory has no idea whether it has an exclusive copy of data
|
|
|
|
|
// or not.
|
|
|
|
|
num_backing_store++;
|
|
|
|
|
else if (access_perm == AccessPermission_Invalid ||
|
|
|
|
|
access_perm == AccessPermission_NotPresent)
|
|
|
|
|
num_invalid++;
|
2011-07-01 02:49:26 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// If the number of read write copies is more than 1, then there is bug in
|
|
|
|
|
// coherence protocol. Otherwise, if all copies are in stable states, i.e.
|
|
|
|
|
// num_busy == 0, we update all the copies. If there is at least one copy
|
|
|
|
|
// in busy state, then we check if there is read write copy. If yes, then
|
2011-09-01 20:41:44 +02:00
|
|
|
// also we let the access go through. Or, if there is no copy in the cache
|
|
|
|
|
// hierarchy at all, we still want to do the write to the memory
|
|
|
|
|
// (Backing_Store) instead of failing.
|
2011-07-01 02:49:26 +02:00
|
|
|
|
|
|
|
|
DPRINTF(RubyPort, "num_busy = %d, num_ro = %d, num_rw = %d\n",
|
|
|
|
|
num_busy, num_ro, num_rw);
|
|
|
|
|
assert(num_rw <= 1);
|
|
|
|
|
|
2012-09-11 16:23:56 +02:00
|
|
|
uint8_t *data = pkt->getPtr<uint8_t>(true);
|
2011-09-01 20:41:44 +02:00
|
|
|
unsigned int size_in_bytes = pkt->getSize();
|
|
|
|
|
unsigned startByte = addr.getAddress() - line_addr.getAddress();
|
|
|
|
|
|
|
|
|
|
if ((num_busy == 0 && num_ro > 0) || num_rw == 1 ||
|
|
|
|
|
(num_invalid == (num_controllers - 1) && num_backing_store == 1))
|
|
|
|
|
{
|
|
|
|
|
for(int i = 0; i < num_controllers;++i) {
|
|
|
|
|
access_perm = ruby_system->m_abs_cntrl_vec[i]->
|
2011-07-01 02:49:26 +02:00
|
|
|
getAccessPermission(line_addr);
|
2011-09-01 20:41:44 +02:00
|
|
|
if(access_perm == AccessPermission_Read_Only ||
|
|
|
|
|
access_perm == AccessPermission_Read_Write||
|
|
|
|
|
access_perm == AccessPermission_Maybe_Stale ||
|
|
|
|
|
access_perm == AccessPermission_Backing_Store)
|
2011-07-01 02:49:26 +02:00
|
|
|
{
|
|
|
|
|
DataBlock& block = ruby_system->m_abs_cntrl_vec[i]
|
|
|
|
|
->getDataBlock(line_addr);
|
|
|
|
|
|
|
|
|
|
DPRINTF(RubyPort, "%s\n",block);
|
2011-09-01 20:41:44 +02:00
|
|
|
for (unsigned i = 0; i < size_in_bytes; ++i) {
|
2011-07-01 02:49:26 +02:00
|
|
|
block.setByte(i + startByte, data[i]);
|
|
|
|
|
}
|
|
|
|
|
DPRINTF(RubyPort, "%s\n",block);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
RubyPort::M5Port::recvFunctional(PacketPtr pkt)
|
|
|
|
|
{
|
|
|
|
|
DPRINTF(RubyPort, "Functional access caught for address %#x\n",
|
|
|
|
|
pkt->getAddr());
|
|
|
|
|
|
|
|
|
|
// Check for pio requests and directly send them to the dedicated
|
|
|
|
|
// pio port.
|
|
|
|
|
if (!isPhysMemAddress(pkt->getAddr())) {
|
2012-02-24 17:43:53 +01:00
|
|
|
assert(ruby_port->pio_port.isConnected());
|
2011-07-01 02:49:26 +02:00
|
|
|
DPRINTF(RubyPort, "Request for address 0x%#x is a pio request\n",
|
|
|
|
|
pkt->getAddr());
|
|
|
|
|
panic("RubyPort::PioPort::recvFunctional() not implemented!\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
assert(pkt->getAddr() + pkt->getSize() <=
|
|
|
|
|
line_address(Address(pkt->getAddr())).getAddress() +
|
|
|
|
|
RubySystem::getBlockSizeBytes());
|
|
|
|
|
|
|
|
|
|
bool accessSucceeded = false;
|
|
|
|
|
bool needsResponse = pkt->needsResponse();
|
|
|
|
|
|
|
|
|
|
// Do the functional access on ruby memory
|
|
|
|
|
if (pkt->isRead()) {
|
|
|
|
|
accessSucceeded = doFunctionalRead(pkt);
|
|
|
|
|
} else if (pkt->isWrite()) {
|
|
|
|
|
accessSucceeded = doFunctionalWrite(pkt);
|
|
|
|
|
} else {
|
|
|
|
|
panic("RubyPort: unsupported functional command %s\n",
|
|
|
|
|
pkt->cmdString());
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Unless the requester explicitly said otherwise, generate an error if
|
|
|
|
|
// the functional request failed
|
|
|
|
|
if (!accessSucceeded && !pkt->suppressFuncError()) {
|
|
|
|
|
fatal("Ruby functional %s failed for address %#x\n",
|
|
|
|
|
pkt->isWrite() ? "write" : "read", pkt->getAddr());
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (access_phys_mem) {
|
|
|
|
|
// The attached physmem contains the official version of data.
|
|
|
|
|
// The following command performs the real functional access.
|
|
|
|
|
// This line should be removed once Ruby supplies the official version
|
|
|
|
|
// of data.
|
2012-04-06 19:46:31 +02:00
|
|
|
ruby_port->system->getPhysMem().functionalAccess(pkt);
|
2011-07-01 02:49:26 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// turn packet around to go back to requester if response expected
|
|
|
|
|
if (needsResponse) {
|
|
|
|
|
pkt->setFunctionalResponseStatus(accessSucceeded);
|
2012-01-17 19:55:08 +01:00
|
|
|
|
|
|
|
|
// @todo There should not be a reverse call since the response is
|
|
|
|
|
// communicated through the packet pointer
|
|
|
|
|
// DPRINTF(RubyPort, "Sending packet back over port\n");
|
|
|
|
|
// sendFunctional(pkt);
|
2011-07-01 02:49:26 +02:00
|
|
|
}
|
|
|
|
|
DPRINTF(RubyPort, "Functional access %s!\n",
|
|
|
|
|
accessSucceeded ? "successful":"failed");
|
|
|
|
|
}
|
|
|
|
|
|
2010-01-30 05:29:19 +01:00
|
|
|
void
|
2010-01-30 05:29:33 +01:00
|
|
|
RubyPort::ruby_hit_callback(PacketPtr pkt)
|
2010-01-30 05:29:19 +01:00
|
|
|
{
|
2010-01-30 05:29:33 +01:00
|
|
|
// Retrieve the request port from the sender State
|
2010-03-23 02:43:53 +01:00
|
|
|
RubyPort::SenderState *senderState =
|
2010-01-30 05:29:33 +01:00
|
|
|
safe_cast<RubyPort::SenderState *>(pkt->senderState);
|
|
|
|
|
M5Port *port = senderState->port;
|
|
|
|
|
assert(port != NULL);
|
2010-03-23 02:43:53 +01:00
|
|
|
|
2010-01-30 05:29:33 +01:00
|
|
|
// pop the sender state from the packet
|
|
|
|
|
pkt->senderState = senderState->saved;
|
|
|
|
|
delete senderState;
|
2010-01-30 05:29:19 +01:00
|
|
|
|
|
|
|
|
port->hitCallback(pkt);
|
2011-02-07 07:14:18 +01:00
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// If we had to stall the M5Ports, wake them up because the sequencer
|
|
|
|
|
// likely has free resources now.
|
|
|
|
|
//
|
|
|
|
|
if (waitingOnSequencer) {
|
2011-03-19 22:17:48 +01:00
|
|
|
//
|
|
|
|
|
// Record the current list of ports to retry on a temporary list before
|
|
|
|
|
// calling sendRetry on those ports. sendRetry will cause an
|
|
|
|
|
// immediate retry, which may result in the ports being put back on the
|
|
|
|
|
// list. Therefore we want to clear the retryList before calling
|
|
|
|
|
// sendRetry.
|
|
|
|
|
//
|
|
|
|
|
std::list<M5Port*> curRetryList(retryList);
|
|
|
|
|
|
|
|
|
|
retryList.clear();
|
|
|
|
|
waitingOnSequencer = false;
|
|
|
|
|
|
|
|
|
|
for (std::list<M5Port*>::iterator i = curRetryList.begin();
|
|
|
|
|
i != curRetryList.end(); ++i) {
|
|
|
|
|
DPRINTF(RubyPort,
|
2011-02-07 07:14:18 +01:00
|
|
|
"Sequencer may now be free. SendRetry to port %s\n",
|
|
|
|
|
(*i)->name());
|
2011-03-19 22:17:48 +01:00
|
|
|
(*i)->onRetryList(false);
|
|
|
|
|
(*i)->sendRetry();
|
2011-02-07 07:14:18 +01:00
|
|
|
}
|
|
|
|
|
}
|
2012-01-11 20:48:48 +01:00
|
|
|
|
|
|
|
|
testDrainComplete();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
RubyPort::testDrainComplete()
|
|
|
|
|
{
|
|
|
|
|
//If we weren't able to drain before, we might be able to now.
|
|
|
|
|
if (drainEvent != NULL) {
|
2012-09-23 20:57:08 +02:00
|
|
|
unsigned int drainCount = outstandingCount();
|
2012-08-15 16:38:08 +02:00
|
|
|
DPRINTF(Drain, "Drain count: %u\n", drainCount);
|
2012-01-11 20:48:48 +01:00
|
|
|
if (drainCount == 0) {
|
2012-08-15 16:38:08 +02:00
|
|
|
DPRINTF(Drain, "RubyPort done draining, processing drain event\n");
|
2012-01-11 20:48:48 +01:00
|
|
|
drainEvent->process();
|
|
|
|
|
// Clear the drain event once we're done with it.
|
|
|
|
|
drainEvent = NULL;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
unsigned int
|
2012-09-23 20:57:08 +02:00
|
|
|
RubyPort::getChildDrainCount(Event *de)
|
2012-01-11 20:48:48 +01:00
|
|
|
{
|
|
|
|
|
int count = 0;
|
|
|
|
|
|
2012-02-24 17:43:53 +01:00
|
|
|
if (pio_port.isConnected()) {
|
|
|
|
|
count += pio_port.drain(de);
|
2012-01-11 20:48:48 +01:00
|
|
|
DPRINTF(Config, "count after pio check %d\n", count);
|
|
|
|
|
}
|
|
|
|
|
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) {
|
|
|
|
|
count += (*p)->drain(de);
|
|
|
|
|
DPRINTF(Config, "count after slave port check %d\n", count);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
for (std::vector<PioPort*>::iterator p = master_ports.begin();
|
|
|
|
|
p != master_ports.end(); ++p) {
|
|
|
|
|
count += (*p)->drain(de);
|
|
|
|
|
DPRINTF(Config, "count after master port check %d\n", count);
|
2012-01-11 20:48:48 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
DPRINTF(Config, "final count %d\n", count);
|
|
|
|
|
|
|
|
|
|
return count;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
unsigned int
|
|
|
|
|
RubyPort::drain(Event *de)
|
|
|
|
|
{
|
|
|
|
|
if (isDeadlockEventScheduled()) {
|
|
|
|
|
descheduleDeadlockEvent();
|
|
|
|
|
}
|
|
|
|
|
|
2012-09-23 20:57:08 +02:00
|
|
|
//
|
|
|
|
|
// If the RubyPort is not empty, then it needs to clear all outstanding
|
|
|
|
|
// requests before it should call drainEvent->process()
|
|
|
|
|
//
|
|
|
|
|
DPRINTF(Config, "outstanding count %d\n", outstandingCount());
|
|
|
|
|
bool need_drain = outstandingCount() > 0;
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Also, get the number of child ports that will also need to clear
|
|
|
|
|
// their buffered requests before they call drainEvent->process()
|
|
|
|
|
//
|
|
|
|
|
unsigned int child_drain_count = getChildDrainCount(de);
|
2012-01-11 20:48:48 +01:00
|
|
|
|
|
|
|
|
// Set status
|
2012-09-23 20:57:08 +02:00
|
|
|
if (need_drain) {
|
2012-01-11 20:48:48 +01:00
|
|
|
drainEvent = de;
|
|
|
|
|
|
2012-08-15 16:38:08 +02:00
|
|
|
DPRINTF(Drain, "RubyPort not drained\n");
|
2012-01-11 20:48:48 +01:00
|
|
|
changeState(SimObject::Draining);
|
2012-09-23 20:57:08 +02:00
|
|
|
return child_drain_count + 1;
|
2012-01-11 20:48:48 +01:00
|
|
|
}
|
|
|
|
|
|
2012-09-23 20:57:08 +02:00
|
|
|
drainEvent = NULL;
|
2012-01-11 20:48:48 +01:00
|
|
|
changeState(SimObject::Drained);
|
2012-09-23 20:57:08 +02:00
|
|
|
return child_drain_count;
|
2010-01-30 05:29:19 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
RubyPort::M5Port::hitCallback(PacketPtr pkt)
|
|
|
|
|
{
|
|
|
|
|
bool needsResponse = pkt->needsResponse();
|
|
|
|
|
|
2010-08-20 20:46:12 +02:00
|
|
|
//
|
2011-02-07 07:14:19 +01:00
|
|
|
// Unless specified at configuraiton, all responses except failed SC
|
2011-03-28 17:49:45 +02:00
|
|
|
// and Flush operations access M5 physical memory.
|
2010-08-20 20:46:12 +02:00
|
|
|
//
|
2011-02-07 07:14:19 +01:00
|
|
|
bool accessPhysMem = access_phys_mem;
|
2010-08-20 20:46:12 +02:00
|
|
|
|
|
|
|
|
if (pkt->isLLSC()) {
|
|
|
|
|
if (pkt->isWrite()) {
|
|
|
|
|
if (pkt->req->getExtraData() != 0) {
|
|
|
|
|
//
|
|
|
|
|
// Successful SC packets convert to normal writes
|
|
|
|
|
//
|
|
|
|
|
pkt->convertScToWrite();
|
|
|
|
|
} else {
|
|
|
|
|
//
|
|
|
|
|
// Failed SC packets don't access physical memory and thus
|
|
|
|
|
// the RubyPort itself must convert it to a response.
|
|
|
|
|
//
|
|
|
|
|
accessPhysMem = false;
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
//
|
|
|
|
|
// All LL packets convert to normal loads so that M5 PhysMem does
|
|
|
|
|
// not lock the blocks.
|
|
|
|
|
//
|
|
|
|
|
pkt->convertLlToRead();
|
|
|
|
|
}
|
|
|
|
|
}
|
2011-03-28 17:49:45 +02:00
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// Flush requests don't access physical memory
|
|
|
|
|
//
|
|
|
|
|
if (pkt->isFlush()) {
|
|
|
|
|
accessPhysMem = false;
|
|
|
|
|
}
|
|
|
|
|
|
2011-03-19 22:17:48 +01:00
|
|
|
DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse);
|
2010-01-30 05:29:19 +01:00
|
|
|
|
2010-08-20 20:46:12 +02:00
|
|
|
if (accessPhysMem) {
|
2012-04-06 19:46:31 +02:00
|
|
|
ruby_port->system->getPhysMem().access(pkt);
|
2011-03-28 17:49:45 +02:00
|
|
|
} else if (needsResponse) {
|
2011-02-07 07:14:19 +01:00
|
|
|
pkt->makeResponse();
|
2010-08-20 20:46:12 +02:00
|
|
|
}
|
2010-01-30 05:29:19 +01:00
|
|
|
|
|
|
|
|
// turn packet around to go back to requester if response expected
|
|
|
|
|
if (needsResponse) {
|
2011-03-19 22:17:48 +01:00
|
|
|
DPRINTF(RubyPort, "Sending packet back over port\n");
|
2012-08-22 17:39:56 +02:00
|
|
|
// send next cycle
|
2012-09-10 19:21:01 +02:00
|
|
|
schedTimingResp(pkt, curTick() + g_system_ptr->clockPeriod());
|
2010-01-30 05:29:19 +01:00
|
|
|
} else {
|
|
|
|
|
delete pkt;
|
|
|
|
|
}
|
2011-03-19 22:17:48 +01:00
|
|
|
DPRINTF(RubyPort, "Hit callback done!\n");
|
2010-01-30 05:29:19 +01:00
|
|
|
}
|
|
|
|
|
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
AddrRangeList
|
2012-07-09 18:35:34 +02:00
|
|
|
RubyPort::M5Port::getAddrRanges() const
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
{
|
|
|
|
|
// at the moment the assumption is that the master does not care
|
|
|
|
|
AddrRangeList ranges;
|
|
|
|
|
return ranges;
|
|
|
|
|
}
|
|
|
|
|
|
2010-01-30 05:29:19 +01:00
|
|
|
bool
|
|
|
|
|
RubyPort::M5Port::isPhysMemAddress(Addr addr)
|
|
|
|
|
{
|
2012-04-06 19:46:31 +02:00
|
|
|
return ruby_port->system->isMemAddr(addr);
|
2010-01-30 05:29:19 +01:00
|
|
|
}
|
2011-02-07 07:14:18 +01:00
|
|
|
|
|
|
|
|
unsigned
|
|
|
|
|
RubyPort::M5Port::deviceBlockSize() const
|
|
|
|
|
{
|
|
|
|
|
return (unsigned) RubySystem::getBlockSizeBytes();
|
|
|
|
|
}
|
2012-01-23 18:07:14 +01:00
|
|
|
|
|
|
|
|
void
|
|
|
|
|
RubyPort::ruby_eviction_callback(const Address& address)
|
|
|
|
|
{
|
|
|
|
|
DPRINTF(RubyPort, "Sending invalidations.\n");
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
// should this really be using funcMasterId?
|
2012-02-12 23:07:38 +01:00
|
|
|
Request req(address.getAddress(), 0, 0, Request::funcMasterId);
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) {
|
2012-07-09 18:35:32 +02:00
|
|
|
// check if the connected master port is snooping
|
|
|
|
|
if ((*p)->isSnooping()) {
|
MEM: Remove the Broadcast destination from the packet
This patch simplifies the packet by removing the broadcast flag and
instead more firmly relying on (and enforcing) the semantics of
transactions in the classic memory system, i.e. request packets are
routed from a master to a slave based on the address, and when they
are created they have neither a valid source, nor destination. On
their way to the slave, the request packet is updated with a source
field for all modules that multiplex packets from multiple master
(e.g. a bus). When a request packet is turned into a response packet
(at the final slave), it moves the potentially populated source field
to the destination field, and the response packet is routed through
any multiplexing components back to the master based on the
destination field.
Modules that connect multiplexing components, such as caches and
bridges store any existing source and destination field in the sender
state as a stack (just as before).
The packet constructor is simplified in that there is no longer a need
to pass the Packet::Broadcast as the destination (this was always the
case for the classic memory system). In the case of Ruby, rather than
using the parameter to the constructor we now rely on setDest, as
there is already another three-argument constructor in the packet
class.
In many places where the packet information was printed as part of
DPRINTFs, request packets would be printed with a numeric "dest" that
would always be -1 (Broadcast) and that field is now removed from the
printing.
2012-04-14 11:45:55 +02:00
|
|
|
Packet *pkt = new Packet(&req, MemCmd::InvalidationReq);
|
MEM: Separate snoops and normal memory requests/responses
This patch introduces port access methods that separates snoop
request/responses from normal memory request/responses. The
differentiation is made for functional, atomic and timing accesses and
builds on the introduction of master and slave ports.
Before the introduction of this patch, the packets belonging to the
different phases of the protocol (request -> [forwarded snoop request
-> snoop response]* -> response) all use the same port access
functions, even though the snoop packets flow in the opposite
direction to the normal packet. That is, a coherent master sends
normal request and receives responses, but receives snoop requests and
sends snoop responses (vice versa for the slave). These two distinct
phases now use different access functions, as described below.
Starting with the functional access, a master sends a request to a
slave through sendFunctional, and the request packet is turned into a
response before the call returns. In a system without cache coherence,
this is all that is needed from the functional interface. For the
cache-coherent scenario, a slave also sends snoop requests to coherent
masters through sendFunctionalSnoop, with responses returned within
the same packet pointer. This is currently used by the bus and caches,
and the LSQ of the O3 CPU. The send/recvFunctional and
send/recvFunctionalSnoop are moved from the Port super class to the
appropriate subclass.
Atomic accesses follow the same flow as functional accesses, with
request being sent from master to slave through sendAtomic. In the
case of cache-coherent ports, a slave can send snoop requests to a
master through sendAtomicSnoop. Just as for the functional access
methods, the atomic send and receive member functions are moved to the
appropriate subclasses.
The timing access methods are different from the functional and atomic
in that requests and responses are separated in time and
send/recvTiming are used for both directions. Hence, a master uses
sendTiming to send a request to a slave, and a slave uses sendTiming
to send a response back to a master, at a later point in time. Snoop
requests and responses travel in the opposite direction, similar to
what happens in functional and atomic accesses. With the introduction
of this patch, it is possible to determine the direction of packets in
the bus, and no longer necessary to look for both a master and a slave
port with the requested port id.
In contrast to the normal recvFunctional, recvAtomic and recvTiming
that are pure virtual functions, the recvFunctionalSnoop,
recvAtomicSnoop and recvTimingSnoop have a default implementation that
calls panic. This is to allow non-coherent master and slave ports to
not implement these functions.
2012-04-14 11:45:07 +02:00
|
|
|
// send as a snoop request
|
2012-05-04 09:30:02 +02:00
|
|
|
(*p)->sendTimingSnoopReq(pkt);
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
}
|
2012-01-23 18:07:14 +01:00
|
|
|
}
|
|
|
|
|
}
|
