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gem5/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt

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ruby: Initial references for ruby regressions
2009-05-11 19:38:46 +02:00
---------- Begin Simulation Statistics ----------
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
sim_seconds 0.000095 # Number of seconds simulated
sim_ticks 95241 # Number of ticks simulated
final_tick 95241 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sparc: update simple cpu regressions use stats file generated by zizzer
2011-06-10 09:45:24 +02:00
sim_freq 1000000000 # Frequency of simulated ticks
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
host_inst_rate 71470 # Simulator instruction rate (inst/s)
host_op_rate 71456 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1277340 # Simulator tick rate (ticks/s)
host_mem_usage 449880 # Number of bytes of host memory used
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
host_seconds 0.07 # Real time elapsed on the host
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 82496 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 82496 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 82240 # Number of bytes written to this memory
system.mem_ctrls.bytes_written::total 82240 # Number of bytes written to this memory
system.mem_ctrls.num_reads::ruby.dir_cntrl0 1289 # Number of read requests responded to by this memory
system.mem_ctrls.num_reads::total 1289 # Number of read requests responded to by this memory
system.mem_ctrls.num_writes::ruby.dir_cntrl0 1285 # Number of write requests responded to by this memory
system.mem_ctrls.num_writes::total 1285 # Number of write requests responded to by this memory
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls.bw_read::ruby.dir_cntrl0 866181581 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_read::total 866181581 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::ruby.dir_cntrl0 863493663 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::total 863493663 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_total::ruby.dir_cntrl0 1729675245 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.bw_total::total 1729675245 # Total bandwidth to/from this memory (bytes/s)
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.readReqs 1289 # Number of read requests accepted
system.mem_ctrls.writeReqs 1285 # Number of write requests accepted
system.mem_ctrls.readBursts 1289 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.writeBursts 1285 # Number of DRAM write bursts, including those merged in the write queue
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls.bytesReadDRAM 43328 # Total number of bytes read from DRAM
system.mem_ctrls.bytesReadWrQ 39168 # Total number of bytes read from write queue
system.mem_ctrls.bytesWritten 43904 # Total number of bytes written to DRAM
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.bytesReadSys 82496 # Total read bytes from the system interface side
system.mem_ctrls.bytesWrittenSys 82240 # Total written bytes from the system interface side
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls.servicedByWrQ 612 # Number of DRAM read bursts serviced by the write queue
system.mem_ctrls.mergedWrBursts 580 # Number of DRAM write bursts merged with an existing one
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls.perBankRdBursts::0 32 # Per bank write bursts
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.perBankRdBursts::1 16 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::2 1 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::3 8 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls.perBankRdBursts::5 113 # Per bank write bursts
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.perBankRdBursts::6 121 # Per bank write bursts
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls.perBankRdBursts::7 123 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::8 59 # Per bank write bursts
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.perBankRdBursts::9 34 # Per bank write bursts
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls.perBankRdBursts::10 11 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::11 58 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::12 21 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13 61 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14 11 # Per bank write bursts
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.perBankRdBursts::15 8 # Per bank write bursts
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls.perBankWrBursts::0 32 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::1 16 # Per bank write bursts
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.perBankWrBursts::2 1 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::3 8 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::5 111 # Per bank write bursts
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls.perBankWrBursts::6 113 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::7 127 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::8 65 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::9 35 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::10 11 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::11 56 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::12 22 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::13 66 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::14 14 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::15 9 # Per bank write bursts
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls.totGap 95177 # Total gap between requests
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::6 1289 # Read request sizes (log2)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::6 1285 # Write request sizes (log2)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls.rdQLenPdf::0 677 # What read queue length does an incoming req see
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls.wrQLenPdf::15 5 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::16 5 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::17 41 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::18 43 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::19 45 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::20 43 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::21 45 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::22 42 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::23 42 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::24 42 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::25 42 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::26 42 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::27 42 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::28 42 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::29 42 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::30 42 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::31 42 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::32 42 # What write queue length does an incoming req see
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.wrQLenPdf::33 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls.bytesPerActivate::samples 241 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::mean 353.991701 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::gmean 236.521382 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::stdev 306.711183 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::0-127 49 20.33% 20.33% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::128-255 67 27.80% 48.13% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::256-383 30 12.45% 60.58% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::384-511 30 12.45% 73.03% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::512-639 18 7.47% 80.50% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::640-767 7 2.90% 83.40% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::768-895 9 3.73% 87.14% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::896-1023 14 5.81% 92.95% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::1024-1151 17 7.05% 100.00% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::total 241 # Bytes accessed per row activation
system.mem_ctrls.rdPerTurnAround::samples 42 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::mean 16.047619 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::gmean 15.828866 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::stdev 3.297837 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::12-13 1 2.38% 2.38% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::14-15 18 42.86% 45.24% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::16-17 17 40.48% 85.71% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::18-19 5 11.90% 97.62% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::34-35 1 2.38% 100.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::total 42 # Reads before turning the bus around for writes
system.mem_ctrls.wrPerTurnAround::samples 42 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::mean 16.333333 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::gmean 16.313589 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::stdev 0.845841 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::16 35 83.33% 83.33% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::17 3 7.14% 90.48% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::18 1 2.38% 92.86% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::19 3 7.14% 100.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::total 42 # Writes before turning the bus around for reads
system.mem_ctrls.totQLat 8633 # Total ticks spent queuing
system.mem_ctrls.totMemAccLat 21496 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrls.totBusLat 3385 # Total ticks spent in databus transfers
system.mem_ctrls.avgQLat 12.75 # Average queueing delay per DRAM burst
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls.avgMemAccLat 31.75 # Average memory access latency per DRAM burst
system.mem_ctrls.avgRdBW 454.93 # Average DRAM read bandwidth in MiByte/s
system.mem_ctrls.avgWrBW 460.98 # Average achieved write bandwidth in MiByte/s
system.mem_ctrls.avgRdBWSys 866.18 # Average system read bandwidth in MiByte/s
system.mem_ctrls.avgWrBWSys 863.49 # Average system write bandwidth in MiByte/s
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls.busUtil 7.16 # Data bus utilization in percentage
system.mem_ctrls.busUtilRead 3.55 # Data bus utilization in percentage for reads
system.mem_ctrls.busUtilWrite 3.60 # Data bus utilization in percentage for writes
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls.avgWrQLen 25.53 # Average write queue length when enqueuing
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.readRowHits 496 # Number of row buffer hits during reads
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls.writeRowHits 621 # Number of row buffer hits during writes
system.mem_ctrls.readRowHitRate 73.26 # Row buffer hit rate for reads
system.mem_ctrls.writeRowHitRate 88.09 # Row buffer hit rate for writes
system.mem_ctrls.avgGap 36.98 # Average gap between requests
system.mem_ctrls.pageHitRate 80.82 # Row buffer hit rate, read and write combined
system.mem_ctrls_0.actEnergy 1141560 # Energy for activate commands per rank (pJ)
system.mem_ctrls_0.preEnergy 634200 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_0.readEnergy 5079360 # Energy for read commands per rank (pJ)
system.mem_ctrls_0.writeEnergy 4178304 # Energy for write commands per rank (pJ)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.mem_ctrls_0.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls_0.actBackEnergy 60945084 # Energy for active background per rank (pJ)
system.mem_ctrls_0.preBackEnergy 2754600 # Energy for precharge background per rank (pJ)
system.mem_ctrls_0.totalEnergy 80835828 # Total energy per rank (pJ)
system.mem_ctrls_0.averagePower 862.782607 # Core power per rank (mW)
system.mem_ctrls_0.memoryStateTime::IDLE 4199 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.mem_ctrls_0.memoryStateTime::REF 3120 # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls_0.memoryStateTime::ACT 86387 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls_1.actEnergy 680400 # Energy for activate commands per rank (pJ)
system.mem_ctrls_1.preEnergy 378000 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_1.readEnergy 3194880 # Energy for read commands per rank (pJ)
system.mem_ctrls_1.writeEnergy 2768256 # Energy for write commands per rank (pJ)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.mem_ctrls_1.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls_1.actBackEnergy 57004560 # Energy for active background per rank (pJ)
system.mem_ctrls_1.preBackEnergy 6211200 # Energy for precharge background per rank (pJ)
system.mem_ctrls_1.totalEnergy 76340016 # Total energy per rank (pJ)
system.mem_ctrls_1.averagePower 814.797592 # Core power per rank (mW)
system.mem_ctrls_1.memoryStateTime::IDLE 10140 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.mem_ctrls_1.memoryStateTime::REF 3120 # Time in different power states
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls_1.memoryStateTime::ACT 80556 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.workload.num_syscalls 11 # Number of system calls
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.numCycles 95241 # number of cpu cycles simulated
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 5327 # Number of instructions committed
system.cpu.committedOps 5327 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 146 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 773 # number of instructions that are conditional controls
system.cpu.num_int_insts 4505 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 10598 # number of times the integer registers were read
system.cpu.num_int_register_writes 4845 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 1401 # number of memory refs
system.cpu.num_load_insts 723 # Number of load instructions
system.cpu.num_store_insts 678 # Number of store instructions
system.cpu.num_idle_cycles 0.999990 # Number of idle cycles
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.num_busy_cycles 95240.000010 # Number of busy cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.not_idle_fraction 0.999990 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000010 # Percentage of idle cycles
system.cpu.Branches 1121 # Number of branches fetched
system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction
system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction
system.cpu.op_class::IntMult 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction
system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction
system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 5370 # Class of executed instruction
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.ruby.clk_domain.clock 1 # Clock period in ticks
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
system.ruby.delayHist::samples 2574 # delay histogram for all message
system.ruby.delayHist | 2574 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
system.ruby.delayHist::total 2574 # delay histogram for all message
system.ruby.outstanding_req_hist::bucket_size 1
system.ruby.outstanding_req_hist::max_bucket 9
system.ruby.outstanding_req_hist::samples 6759
system.ruby.outstanding_req_hist::mean 1
system.ruby.outstanding_req_hist::gmean 1
system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 6759 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.outstanding_req_hist::total 6759
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.ruby.latency_hist::bucket_size 64
system.ruby.latency_hist::max_bucket 639
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.latency_hist::samples 6758
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.latency_hist::mean 13.093075
system.ruby.latency_hist::gmean 5.137326
system.ruby.latency_hist::stdev 25.295268
system.ruby.latency_hist | 6551 96.94% 96.94% | 168 2.49% 99.42% | 27 0.40% 99.82% | 4 0.06% 99.88% | 3 0.04% 99.93% | 5 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.latency_hist::total 6758
system.ruby.hit_latency_hist::bucket_size 1
system.ruby.hit_latency_hist::max_bucket 9
system.ruby.hit_latency_hist::samples 5469
system.ruby.hit_latency_hist::mean 3
system.ruby.hit_latency_hist::gmean 3.000000
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5469 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.hit_latency_hist::total 5469
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.ruby.miss_latency_hist::bucket_size 64
system.ruby.miss_latency_hist::max_bucket 639
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.miss_latency_hist::samples 1289
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.miss_latency_hist::mean 55.916214
system.ruby.miss_latency_hist::gmean 50.341721
system.ruby.miss_latency_hist::stdev 32.999000
system.ruby.miss_latency_hist | 1082 83.94% 83.94% | 168 13.03% 96.97% | 27 2.09% 99.07% | 4 0.31% 99.38% | 3 0.23% 99.61% | 5 0.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.miss_latency_hist::total 1289
system.ruby.Directory.incomplete_times 1288
stats: updates statistics for ruby regressions
2013-05-21 18:32:57 +02:00
system.ruby.l1_cntrl0.cacheMemory.demand_hits 5469 # Number of cache demand hits
system.ruby.l1_cntrl0.cacheMemory.demand_misses 1289 # Number of cache demand misses
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 6758 # Number of cache demand accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.network.routers0.percent_links_utilized 6.756544
stats: ruby: updates due to recent changes.
2013-09-06 23:21:36 +02:00
system.ruby.network.routers0.msg_count.Control::2 1289
system.ruby.network.routers0.msg_count.Data::2 1285
system.ruby.network.routers0.msg_count.Response_Data::4 1289
system.ruby.network.routers0.msg_count.Writeback_Control::3 1285
system.ruby.network.routers0.msg_bytes.Control::2 10312
system.ruby.network.routers0.msg_bytes.Data::2 92520
system.ruby.network.routers0.msg_bytes.Response_Data::4 92808
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 10280
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.network.routers1.percent_links_utilized 6.756544
stats: ruby: updates due to recent changes.
2013-09-06 23:21:36 +02:00
system.ruby.network.routers1.msg_count.Control::2 1289
system.ruby.network.routers1.msg_count.Data::2 1285
system.ruby.network.routers1.msg_count.Response_Data::4 1289
system.ruby.network.routers1.msg_count.Writeback_Control::3 1285
system.ruby.network.routers1.msg_bytes.Control::2 10312
system.ruby.network.routers1.msg_bytes.Data::2 92520
system.ruby.network.routers1.msg_bytes.Response_Data::4 92808
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 10280
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.network.routers2.percent_links_utilized 6.756544
stats: ruby: updates due to recent changes.
2013-09-06 23:21:36 +02:00
system.ruby.network.routers2.msg_count.Control::2 1289
system.ruby.network.routers2.msg_count.Data::2 1285
system.ruby.network.routers2.msg_count.Response_Data::4 1289
system.ruby.network.routers2.msg_count.Writeback_Control::3 1285
system.ruby.network.routers2.msg_bytes.Control::2 10312
system.ruby.network.routers2.msg_bytes.Data::2 92520
system.ruby.network.routers2.msg_bytes.Response_Data::4 92808
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 10280
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
system.ruby.network.msg_count.Control 3867
system.ruby.network.msg_count.Data 3855
system.ruby.network.msg_count.Response_Data 3867
system.ruby.network.msg_count.Writeback_Control 3855
system.ruby.network.msg_byte.Control 30936
system.ruby.network.msg_byte.Data 277560
system.ruby.network.msg_byte.Response_Data 278424
system.ruby.network.msg_byte.Writeback_Control 30840
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.network.routers0.throttle0.link_utilization 6.764944
stats: ruby: updates due to recent changes.
2013-09-06 23:21:36 +02:00
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1289
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1285
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 92808
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 10280
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.network.routers0.throttle1.link_utilization 6.748144
stats: ruby: updates due to recent changes.
2013-09-06 23:21:36 +02:00
system.ruby.network.routers0.throttle1.msg_count.Control::2 1289
system.ruby.network.routers0.throttle1.msg_count.Data::2 1285
system.ruby.network.routers0.throttle1.msg_bytes.Control::2 10312
system.ruby.network.routers0.throttle1.msg_bytes.Data::2 92520
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.network.routers1.throttle0.link_utilization 6.748144
stats: ruby: updates due to recent changes.
2013-09-06 23:21:36 +02:00
system.ruby.network.routers1.throttle0.msg_count.Control::2 1289
system.ruby.network.routers1.throttle0.msg_count.Data::2 1285
system.ruby.network.routers1.throttle0.msg_bytes.Control::2 10312
system.ruby.network.routers1.throttle0.msg_bytes.Data::2 92520
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.network.routers1.throttle1.link_utilization 6.764944
stats: ruby: updates due to recent changes.
2013-09-06 23:21:36 +02:00
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1289
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1285
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 92808
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 10280
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.network.routers2.throttle0.link_utilization 6.764944
stats: ruby: updates due to recent changes.
2013-09-06 23:21:36 +02:00
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1289
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1285
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 92808
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 10280
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.network.routers2.throttle1.link_utilization 6.748144
stats: ruby: updates due to recent changes.
2013-09-06 23:21:36 +02:00
system.ruby.network.routers2.throttle1.msg_count.Control::2 1289
system.ruby.network.routers2.throttle1.msg_count.Data::2 1285
system.ruby.network.routers2.throttle1.msg_bytes.Control::2 10312
system.ruby.network.routers2.throttle1.msg_bytes.Data::2 92520
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::samples 1289 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1 | 1289 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::total 1289 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::samples 1285 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2 | 1285 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::total 1285 # delay histogram for vnet_2
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.ruby.LD.latency_hist::bucket_size 32
system.ruby.LD.latency_hist::max_bucket 319
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.LD.latency_hist::samples 715
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.LD.latency_hist::mean 29.991608
system.ruby.LD.latency_hist::gmean 13.799155
system.ruby.LD.latency_hist::stdev 30.436552
system.ruby.LD.latency_hist | 320 44.76% 44.76% | 332 46.43% 91.19% | 50 6.99% 98.18% | 5 0.70% 98.88% | 4 0.56% 99.44% | 4 0.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.LD.latency_hist::total 715
system.ruby.LD.hit_latency_hist::bucket_size 1
system.ruby.LD.hit_latency_hist::max_bucket 9
system.ruby.LD.hit_latency_hist::samples 320
system.ruby.LD.hit_latency_hist::mean 3
system.ruby.LD.hit_latency_hist::gmean 3.000000
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 320 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.hit_latency_hist::total 320
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.ruby.LD.miss_latency_hist::bucket_size 32
system.ruby.LD.miss_latency_hist::max_bucket 319
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.LD.miss_latency_hist::samples 395
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.LD.miss_latency_hist::mean 51.858228
system.ruby.LD.miss_latency_hist::gmean 47.506026
system.ruby.LD.miss_latency_hist::stdev 24.651585
system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 332 84.05% 84.05% | 50 12.66% 96.71% | 5 1.27% 97.97% | 4 1.01% 98.99% | 4 1.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.LD.miss_latency_hist::total 395
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.ST.latency_hist::bucket_size 64
system.ruby.ST.latency_hist::max_bucket 639
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.ST.latency_hist::samples 673
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.ST.latency_hist::mean 18.735513
system.ruby.ST.latency_hist::gmean 6.548753
system.ruby.ST.latency_hist::stdev 31.370836
system.ruby.ST.latency_hist | 639 94.95% 94.95% | 25 3.71% 98.66% | 8 1.19% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.ST.latency_hist::total 673
system.ruby.ST.hit_latency_hist::bucket_size 1
system.ruby.ST.hit_latency_hist::max_bucket 9
system.ruby.ST.hit_latency_hist::samples 494
system.ruby.ST.hit_latency_hist::mean 3
system.ruby.ST.hit_latency_hist::gmean 3.000000
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 494 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.hit_latency_hist::total 494
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.ST.miss_latency_hist::bucket_size 64
system.ruby.ST.miss_latency_hist::max_bucket 639
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.ST.miss_latency_hist::samples 179
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.ST.miss_latency_hist::mean 62.162011
system.ruby.ST.miss_latency_hist::gmean 56.471067
system.ruby.ST.miss_latency_hist::stdev 33.641225
system.ruby.ST.miss_latency_hist | 145 81.01% 81.01% | 25 13.97% 94.97% | 8 4.47% 99.44% | 0 0.00% 99.44% | 0 0.00% 99.44% | 1 0.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.ST.miss_latency_hist::total 179
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.ruby.IFETCH.latency_hist::bucket_size 64
system.ruby.IFETCH.latency_hist::max_bucket 639
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.IFETCH.latency_hist::samples 5370
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.IFETCH.latency_hist::mean 10.135940
system.ruby.IFETCH.latency_hist::gmean 4.369076
system.ruby.IFETCH.latency_hist::stdev 22.541685
system.ruby.IFETCH.latency_hist | 5260 97.95% 97.95% | 88 1.64% 99.59% | 11 0.20% 99.80% | 4 0.07% 99.87% | 3 0.06% 99.93% | 4 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.IFETCH.latency_hist::total 5370
system.ruby.IFETCH.hit_latency_hist::bucket_size 1
system.ruby.IFETCH.hit_latency_hist::max_bucket 9
system.ruby.IFETCH.hit_latency_hist::samples 4655
system.ruby.IFETCH.hit_latency_hist::mean 3
system.ruby.IFETCH.hit_latency_hist::gmean 3.000000
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 4655 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.hit_latency_hist::total 4655
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.ruby.IFETCH.miss_latency_hist::bucket_size 64
system.ruby.IFETCH.miss_latency_hist::max_bucket 639
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.IFETCH.miss_latency_hist::samples 715
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.IFETCH.miss_latency_hist::mean 56.594406
system.ruby.IFETCH.miss_latency_hist::gmean 50.506398
system.ruby.IFETCH.miss_latency_hist::stdev 36.435131
system.ruby.IFETCH.miss_latency_hist | 605 84.62% 84.62% | 88 12.31% 96.92% | 11 1.54% 98.46% | 4 0.56% 99.02% | 3 0.42% 99.44% | 4 0.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.IFETCH.miss_latency_hist::total 715
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.ruby.Directory.miss_mach_latency_hist::bucket_size 64
system.ruby.Directory.miss_mach_latency_hist::max_bucket 639
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.Directory.miss_mach_latency_hist::samples 1289
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.Directory.miss_mach_latency_hist::mean 55.916214
system.ruby.Directory.miss_mach_latency_hist::gmean 50.341721
system.ruby.Directory.miss_mach_latency_hist::stdev 32.999000
system.ruby.Directory.miss_mach_latency_hist | 1082 83.94% 83.94% | 168 13.03% 96.97% | 27 2.09% 99.07% | 4 0.31% 99.38% | 3 0.23% 99.61% | 5 0.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.Directory.miss_mach_latency_hist::total 1289
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 1
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev nan
system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 1
system.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 1
system.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 9
system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 1
system.ruby.Directory.miss_latency_hist.initial_to_forward::stdev nan
system.ruby.Directory.miss_latency_hist.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_latency_hist.initial_to_forward::total 1
system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 1
system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 9
system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 1
system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev nan
system.ruby.Directory.miss_latency_hist.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 1
system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 8
system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 79
system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 75
system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 75.000000
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 395
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 51.858228
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 47.506026
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 24.651585
system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 332 84.05% 84.05% | 50 12.66% 96.71% | 5 1.27% 97.97% | 4 1.01% 98.99% | 4 1.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.LD.Directory.miss_type_mach_latency_hist::total 395
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 64
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 639
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 179
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 62.162011
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 56.471067
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 33.641225
system.ruby.ST.Directory.miss_type_mach_latency_hist | 145 81.01% 81.01% | 25 13.97% 94.97% | 8 4.47% 99.44% | 0 0.00% 99.44% | 0 0.00% 99.44% | 1 0.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.ST.Directory.miss_type_mach_latency_hist::total 179
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 715
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 56.594406
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 50.506398
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 36.435131
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 605 84.62% 84.62% | 88 12.31% 96.92% | 11 1.54% 98.46% | 4 0.56% 99.02% | 3 0.42% 99.44% | 4 0.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 715
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.ruby.Directory_Controller.GETX 1289 0.00% 0.00%
system.ruby.Directory_Controller.PUTX 1285 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Data 1289 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Ack 1285 0.00% 0.00%
system.ruby.Directory_Controller.I.GETX 1289 0.00% 0.00%
system.ruby.Directory_Controller.M.PUTX 1285 0.00% 0.00%
system.ruby.Directory_Controller.IM.Memory_Data 1289 0.00% 0.00%
system.ruby.Directory_Controller.MI.Memory_Ack 1285 0.00% 0.00%
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.L1Cache_Controller.Load 715 0.00% 0.00%
system.ruby.L1Cache_Controller.Ifetch 5370 0.00% 0.00%
system.ruby.L1Cache_Controller.Store 673 0.00% 0.00%
system.ruby.L1Cache_Controller.Data 1289 0.00% 0.00%
system.ruby.L1Cache_Controller.Replacement 1285 0.00% 0.00%
system.ruby.L1Cache_Controller.Writeback_Ack 1285 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Load 395 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Ifetch 715 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Store 179 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Load 320 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Ifetch 4655 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Store 494 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Replacement 1285 0.00% 0.00%
system.ruby.L1Cache_Controller.MI.Writeback_Ack 1285 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Data 1110 0.00% 0.00%
system.ruby.L1Cache_Controller.IM.Data 179 0.00% 0.00%
ruby: Initial references for ruby regressions
2009-05-11 19:38:46 +02:00
---------- End Simulation Statistics ----------
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