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gem5/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt

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ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
---------- Begin Simulation Statistics ----------
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
sim_seconds 0.075917 # Number of seconds simulated
sim_ticks 75916922000 # Number of ticks simulated
final_tick 75916922000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
host_inst_rate 139176 # Simulator instruction rate (inst/s)
host_op_rate 152383 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 61310301 # Simulator tick rate (ticks/s)
host_mem_usage 236468 # Number of bytes of host memory used
host_seconds 1238.24 # Real time elapsed on the host
sim_insts 172333316 # Number of instructions simulated
sim_ops 188686798 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 132736 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 112320 # Number of bytes read from this memory
system.physmem.bytes_read::total 245056 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 132736 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 132736 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 2074 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1755 # Number of read requests responded to by this memory
system.physmem.num_reads::total 3829 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1748438 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1479512 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 3227950 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1748438 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1748438 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1748438 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1479512 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3227950 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 3829 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 3829 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 245056 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 245056 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 320 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 234 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 192 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 239 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 228 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 195 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 224 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 283 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 245 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 249 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 248 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 265 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 250 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 236 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 181 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 240 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 75916775000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 3829 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
system.physmem.writePktSize::6 0 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 2774 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 838 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 153 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 44 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 12309321 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 87055321 # Sum of mem lat for all requests
system.physmem.totBusLat 15316000 # Total cycles spent in databus access
system.physmem.totBankLat 59430000 # Total cycles spent in bank access
system.physmem.avgQLat 3214.76 # Average queueing delay per request
system.physmem.avgBankLat 15521.02 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 22735.79 # Average memory access latency
system.physmem.avgRdBW 3.23 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 3.23 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
system.physmem.readRowHits 3315 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 86.58 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 19826788.98 # Average gap between requests
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 400 # Number of system calls
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.numCycles 151833845 # number of cpu cycles simulated
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.BPredUnit.lookups 96840599 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 76060531 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 6557597 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 46497854 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 44230275 # Number of BTB hits
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.BPredUnit.usedRAS 4471070 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 89483 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 40605581 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 388281645 # Number of instructions fetch has processed
system.cpu.fetch.Branches 96840599 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 48701345 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 82243787 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 28438511 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 7066827 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 8646 # Number of stall cycles due to pending traps
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.fetch.CacheLines 37664937 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 1885880 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 151789722 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.799994 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.153176 # Number of instructions fetched each cycle (Total)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.fetch.rateDist::0 69716020 45.93% 45.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 5494868 3.62% 49.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 10713361 7.06% 56.61% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 10448438 6.88% 63.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 8787039 5.79% 69.28% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 6829673 4.50% 73.78% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 6296859 4.15% 77.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 8361926 5.51% 83.44% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 25141538 16.56% 100.00% # Number of instructions fetched each cycle (Total)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.fetch.rateDist::total 151789722 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.637806 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.557280 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 46630303 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 5777884 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 76557243 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 1112705 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 21711587 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 14823931 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 162890 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 401294311 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 730539 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 21711587 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 52135013 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 698137 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 692737 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 72105161 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 4447087 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 379004822 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 6 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 318070 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 3558685 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 642471315 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 1614529203 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1596934770 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 17594433 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 298092611 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 344378704 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 33379 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 33376 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 12572106 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 43979277 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 16887724 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 5767479 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 3738298 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 334855562 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 55454 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 252836764 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 889769 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 145001031 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 373941866 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 4179 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 151789722 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.665704 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.759623 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.issued_per_cycle::0 58337035 38.43% 38.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 22987248 15.14% 53.58% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 25139726 16.56% 70.14% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 20501728 13.51% 83.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 12883464 8.49% 92.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 6586273 4.34% 96.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 4061259 2.68% 99.15% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 1111807 0.73% 99.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 181182 0.12% 100.00% # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.issued_per_cycle::total 151789722 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.fu_full::IntAlu 964155 37.62% 37.62% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 5594 0.22% 37.84% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 37.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 37.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 37.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 37.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 37.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 37.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 37.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 37.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 37.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 37.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 37.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 37.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 37.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 37.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 37.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 37.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 37.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 37.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 94 0.00% 37.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 37.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 37.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 1 0.00% 37.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 37.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 24 0.00% 37.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 37.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 37.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 37.85% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 1191140 46.48% 84.32% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 401719 15.68% 100.00% # attempts to use FU when none available
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.FU_type_0::IntAlu 197361954 78.06% 78.06% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 995375 0.39% 78.45% # Type of FU issued
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.45% # Type of FU issued
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.FU_type_0::SimdFloatAdd 33153 0.01% 78.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 164117 0.06% 78.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 255226 0.10% 78.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 76451 0.03% 78.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 467799 0.19% 78.85% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 206454 0.08% 78.93% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 71861 0.03% 78.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 78.96% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 39017631 15.43% 94.39% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 14186422 5.61% 100.00% # Type of FU issued
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.FU_type_0::total 252836764 # Type of FU issued
system.cpu.iq.rate 1.665220 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2562727 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.010136 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 657141484 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 477682512 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 240592268 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 3774262 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 2248392 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 1852132 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 253504217 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 1895274 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 2034571 # Number of loads that had data forwarded from stores
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 14123734 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 16793 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 19636 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 4237031 # Number of stores squashed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled
bp: fix up stats for changes to branch predictor
2012-02-13 19:30:30 +01:00
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iew.iewSquashCycles 21711587 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 4884 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 553 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 334928786 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 838607 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 43979277 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 16887724 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 32914 # Number of dispatched non-speculative instructions
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.iew.iewIQFullEvents 159 # Number of times the IQ has become full, causing a stall
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iew.iewLSQFullEvents 218 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 19636 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 4106046 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 3927041 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 8033087 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 245835770 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 37393574 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 7000994 # Number of squashed instructions skipped in execute
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iew.exec_nop 17770 # number of nop insts executed
system.cpu.iew.exec_refs 51200144 # number of memory reference insts executed
system.cpu.iew.exec_branches 54041718 # Number of branches executed
system.cpu.iew.exec_stores 13806570 # Number of stores executed
system.cpu.iew.exec_rate 1.619110 # Inst execution rate
system.cpu.iew.wb_sent 243578722 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 242444400 # cumulative count of insts written-back
system.cpu.iew.wb_producers 150079170 # num instructions producing a value
system.cpu.iew.wb_consumers 269183647 # num instructions consuming a value
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iew.wb_rate 1.596774 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.557534 # average fanout of values written-back
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.commit.commitSquashedInsts 146227575 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 51275 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 6404316 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 130078136 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.450676 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.162324 # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.commit.committed_per_cycle::0 59851320 46.01% 46.01% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 32072665 24.66% 70.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 13982527 10.75% 81.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 7658050 5.89% 87.30% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 4412794 3.39% 90.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1335206 1.03% 91.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 1737015 1.34% 93.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1288451 0.99% 94.05% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 7740108 5.95% 100.00% # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.commit.committed_per_cycle::total 130078136 # Number of insts commited each cycle
system.cpu.commit.committedInsts 172347704 # Number of instructions committed
system.cpu.commit.committedOps 188701186 # Number of ops (including micro ops) committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.commit.refs 42506236 # Number of memory references committed
system.cpu.commit.loads 29855543 # Number of loads committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.membars 22408 # Number of memory barriers committed
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.commit.branches 40306370 # Number of branches committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions.
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.commit.int_insts 150130453 # Number of committed integer instructions.
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.function_calls 1848934 # Number of function calls committed.
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.commit.bw_lim_events 7740108 # number cycles where commit BW limit reached
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.rob.rob_reads 457261588 # The number of ROB reads
system.cpu.rob.rob_writes 691688263 # The number of ROB writes
system.cpu.timesIdled 1182 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 44123 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 172333316 # Number of Instructions Simulated
system.cpu.committedOps 188686798 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 172333316 # Number of Instructions Simulated
system.cpu.cpi 0.881048 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.881048 # CPI: Total CPI of All Threads
system.cpu.ipc 1.135013 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.135013 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 1091959933 # number of integer regfile reads
system.cpu.int_regfile_writes 388658885 # number of integer regfile writes
system.cpu.fp_regfile_reads 2913610 # number of floating regfile reads
system.cpu.fp_regfile_writes 2511674 # number of floating regfile writes
system.cpu.misc_regfile_reads 474503072 # number of misc regfile reads
system.cpu.misc_regfile_writes 832154 # number of misc regfile writes
system.cpu.icache.replacements 2619 # number of replacements
system.cpu.icache.tagsinuse 1372.300046 # Cycle average of tags in use
system.cpu.icache.total_refs 37659845 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 4361 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 8635.598487 # Average number of references to valid blocks.
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.icache.occ_blocks::cpu.inst 1372.300046 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.670068 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.670068 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 37659851 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 37659851 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 37659851 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 37659851 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 37659851 # number of overall hits
system.cpu.icache.overall_hits::total 37659851 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 5086 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 5086 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 5086 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 5086 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 5086 # number of overall misses
system.cpu.icache.overall_misses::total 5086 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 90441000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 90441000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 90441000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 90441000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 90441000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 90441000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 37664937 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 37664937 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 37664937 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 37664937 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 37664937 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 37664937 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000135 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000135 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000135 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000135 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000135 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000135 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17782.343689 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 17782.343689 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 17782.343689 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 17782.343689 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 17782.343689 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 17782.343689 # average overall miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 719 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 719 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 719 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 719 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 719 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 719 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4367 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 4367 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 4367 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 4367 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 4367 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 4367 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 67648000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 67648000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 67648000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 67648000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 67648000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 67648000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000116 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000116 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000116 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000116 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15490.725899 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15490.725899 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15490.725899 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 15490.725899 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15490.725899 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 15490.725899 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.replacements 59 # number of replacements
system.cpu.dcache.tagsinuse 1419.994069 # Cycle average of tags in use
system.cpu.dcache.total_refs 47294954 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1868 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 25318.497859 # Average number of references to valid blocks.
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.occ_blocks::cpu.data 1419.994069 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.346678 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.346678 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 34879202 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 34879202 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 12356978 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 12356978 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 30300 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 30300 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 28466 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 28466 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 47236180 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 47236180 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 47236180 # number of overall hits
system.cpu.dcache.overall_hits::total 47236180 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1958 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1958 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 7309 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 7309 # number of WriteReq misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.demand_misses::cpu.data 9267 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 9267 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9267 # number of overall misses
system.cpu.dcache.overall_misses::total 9267 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 54618000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 54618000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 158059500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 158059500 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 66000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 66000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 212677500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 212677500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 212677500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 212677500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 34881160 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 34881160 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 30302 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 30302 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 28466 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 28466 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 47245447 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 47245447 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 47245447 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 47245447 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000056 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000056 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000591 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000591 # miss rate for WriteReq accesses
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000066 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000066 # miss rate for LoadLockedReq accesses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.000196 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000196 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000196 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000196 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27894.790603 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 27894.790603 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21625.324942 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 21625.324942 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 33000 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 33000 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22949.983814 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 22949.983814 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22949.983814 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 22949.983814 # average overall miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.blocked_cycles::no_targets 8 # number of cycles access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.avg_blocked_cycles::no_targets 8 # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
system.cpu.dcache.writebacks::writebacks 18 # number of writebacks
system.cpu.dcache.writebacks::total 18 # number of writebacks
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1172 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 1172 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6221 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 6221 # number of WriteReq MSHR hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.demand_mshr_hits::cpu.data 7393 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 7393 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 7393 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 7393 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 786 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 786 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1088 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1088 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1874 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1874 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1874 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1874 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23408500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 23408500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 28137000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 28137000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 51545500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 51545500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 51545500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 51545500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29781.806616 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29781.806616 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25861.213235 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25861.213235 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27505.602988 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 27505.602988 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27505.602988 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 27505.602988 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.tagsinuse 1993.584817 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2372 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 2758 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.860044 # Average number of references to valid blocks.
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.occ_blocks::writebacks 4.994984 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 1448.115408 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 540.474425 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.044193 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.016494 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.060839 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 2281 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 92 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2373 # number of ReadReq hits
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
system.cpu.l2cache.Writeback_hits::writebacks 18 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 18 # number of Writeback hits
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.UpgradeReq_hits::cpu.data 6 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 6 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2281 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 100 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2381 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 2281 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 100 # number of overall hits
system.cpu.l2cache.overall_hits::total 2381 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 2082 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 693 # number of ReadReq misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_misses::total 2775 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 1075 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 1075 # number of ReadExReq misses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.demand_misses::cpu.inst 2082 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 1768 # number of demand (read+write) misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.demand_misses::total 3850 # number of demand (read+write) misses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.overall_misses::cpu.inst 2082 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1768 # number of overall misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.overall_misses::total 3850 # number of overall misses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 60972000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22472000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 83444000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 27053500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 27053500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 60972000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 49525500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 110497500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 60972000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 49525500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 110497500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 4363 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 785 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 5148 # number of ReadReq accesses(hits+misses)
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses)
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 6 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 6 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1083 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1083 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 4363 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1868 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 6231 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 4363 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1868 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 6231 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.477195 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.882803 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.539044 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992613 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.992613 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.477195 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.946467 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.617878 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.477195 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.946467 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.617878 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 29285.302594 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 32427.128427 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 30069.909910 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 25166.046512 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 25166.046512 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 29285.302594 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 28012.160633 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 28700.649351 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 29285.302594 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 28012.160633 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 28700.649351 # average overall miss latency
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 13 # number of ReadReq MSHR hits
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.ReadReq_mshr_hits::total 21 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
system.cpu.l2cache.demand_mshr_hits::cpu.data 13 # number of demand (read+write) MSHR hits
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.demand_mshr_hits::total 21 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
system.cpu.l2cache.overall_mshr_hits::cpu.data 13 # number of overall MSHR hits
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.overall_mshr_hits::total 21 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2074 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 680 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 2754 # number of ReadReq MSHR misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1075 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1075 # number of ReadExReq MSHR misses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2074 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1755 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 3829 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2074 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1755 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 3829 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 53338835 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19774493 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 73113328 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 23276655 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 23276655 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53338835 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 43051148 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 96389983 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53338835 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 43051148 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 96389983 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.475361 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.866242 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.534965 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992613 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992613 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.475361 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.939507 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.614508 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.475361 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.939507 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.614508 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 25717.856798 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 29080.136765 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 26548.049383 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 21652.702326 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 21652.702326 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 25717.856798 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 24530.568661 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 25173.670149 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 25717.856798 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 24530.568661 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 25173.670149 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink