gem5/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect                         0                       # Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBHits                     38296034                       # Number of BTB hits
global.BPredUnit.BTBLookups                  45834466                       # Number of BTB lookups
global.BPredUnit.RASInCorrect                    1077                       # Number of incorrect RAS predictions.
global.BPredUnit.condIncorrect                5781170                       # Number of conditional branches incorrect
global.BPredUnit.condPredicted               35418150                       # Number of conditional branches predicted
global.BPredUnit.lookups                     62209737                       # Number of BP lookups
global.BPredUnit.usedRAS                     12344504                       # Number of times the RAS was used to get a target.
host_inst_rate                                 183215                       # Simulator instruction rate (inst/s)
host_mem_usage                                 211568                       # Number of bytes of host memory used
host_seconds                                  2049.91                       # Real time elapsed on the host
host_tick_rate                               65854919                       # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads           73961217                       # Number of conflicting loads.
memdepunit.memDep.conflictingStores          54131405                       # Number of conflicting stores.
memdepunit.memDep.insertedLoads             124841223                       # Number of loads inserted to the mem dependence unit.
memdepunit.memDep.insertedStores             92324076                       # Number of stores inserted to the mem dependence unit.
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                   375574819                       # Number of instructions simulated
sim_seconds                                  0.134997                       # Number of seconds simulated
sim_ticks                                134996684500                       # Number of ticks simulated
system.cpu.commit.COM:branches               44587532                       # Number of branches committed
system.cpu.commit.COM:bw_lim_events          13163574                       # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist                     # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle.samples    254545672                      
system.cpu.commit.COM:committed_per_cycle.min_value            0                      
                               0    123085209   4835.49%           
                               1     50466868   1982.63%           
                               2     18758377    736.94%           
                               3     19955031    783.95%           
                               4     11844121    465.30%           
                               5      8478667    333.09%           
                               6      5819307    228.62%           
                               7      2974518    116.86%           
                               8     13163574    517.14%           
system.cpu.commit.COM:committed_per_cycle.max_value            8                      
system.cpu.commit.COM:committed_per_cycle.end_dist

system.cpu.commit.COM:count                 398664594                       # Number of instructions committed
system.cpu.commit.COM:loads                 100651995                       # Number of loads committed
system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
system.cpu.commit.COM:refs                  174183397                       # Number of memory references committed
system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts           5776994                       # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts      398664594                       # The number of committed instructions
system.cpu.commit.commitNonSpecStalls             215                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts        94782663                       # The number of squashed insts skipped by commit
system.cpu.committedInsts                   375574819                       # Number of Instructions Simulated
system.cpu.committedInsts_total             375574819                       # Number of Instructions Simulated
system.cpu.cpi                               0.718880                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.718880                       # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses            1                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits                1                       # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_accesses           95501309                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 33016.637478                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31966.971545                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits               95499596                       # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency       56557500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate          0.000018                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses                 1713                       # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits               729                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency     31455500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate     0.000010                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses             984                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses          73520729                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 30310.747349                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36196.886371                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits              73502716                       # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency     545987492                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate         0.000245                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses               18013                       # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits            14704                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency    119775497                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate     0.000045                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses           3309                       # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs  3249.700000                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.dcache.avg_refs               40460.272684                       # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs                 10                       # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs        32497                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.demand_accesses           169022038                       # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 30545.726047                       # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 35227.346145                       # average overall mshr miss latency
system.cpu.dcache.demand_hits               169002312                       # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency       602544992                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate           0.000117                       # miss rate for demand accesses
system.cpu.dcache.demand_misses                 19726                       # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits              15433                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency    151230997                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate      0.000025                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses             4293                       # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses          169022038                       # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 30545.726047                       # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 35227.346145                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits              169002312                       # number of overall hits
system.cpu.dcache.overall_miss_latency      602544992                       # number of overall miss cycles
system.cpu.dcache.overall_miss_rate          0.000117                       # miss rate for overall accesses
system.cpu.dcache.overall_misses                19726                       # number of overall misses
system.cpu.dcache.overall_mshr_hits             15433                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency    151230997                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate     0.000025                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses            4293                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements                    782                       # number of replacements
system.cpu.dcache.sampled_refs                   4177                       # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse               3293.970402                       # Cycle average of tags in use
system.cpu.dcache.total_refs                169002559                       # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks                      635                       # number of writebacks
system.cpu.decode.DECODE:BlockedCycles       18875032                       # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred           4277                       # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved      11323346                       # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts       531939828                       # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles         132443197                       # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles          101952317                       # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles        15306974                       # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts          12561                       # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles        1275127                       # Number of cycles decode is unblocking
system.cpu.dtb.accesses                     185115437                       # DTB accesses
system.cpu.dtb.acv                                  1                       # DTB access violations
system.cpu.dtb.hits                         185076670                       # DTB hits
system.cpu.dtb.misses                           38767                       # DTB misses
system.cpu.dtb.read_accesses                104449499                       # DTB read accesses
system.cpu.dtb.read_acv                             0                       # DTB read access violations
system.cpu.dtb.read_hits                    104412186                       # DTB read hits
system.cpu.dtb.read_misses                      37313                       # DTB read misses
system.cpu.dtb.write_accesses                80665938                       # DTB write accesses
system.cpu.dtb.write_acv                            1                       # DTB write access violations
system.cpu.dtb.write_hits                    80664484                       # DTB write hits
system.cpu.dtb.write_misses                      1454                       # DTB write misses
system.cpu.fetch.Branches                    62209737                       # Number of branches that fetch encountered
system.cpu.fetch.CacheLines                  63866189                       # Number of cache lines fetched
system.cpu.fetch.Cycles                     169616790                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes               1519057                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts                      544903543                       # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles                 6123543                       # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate                  0.230412                       # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles           63866189                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches           50640538                       # Number of branches that fetch has predicted taken
system.cpu.fetch.rate                        2.018211                       # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist                           # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist.samples           269852647                      
system.cpu.fetch.rateDist.min_value                 0                      
                               0    164102333   6081.18%           
                               1     12367121    458.29%           
                               2     12410556    459.90%           
                               3      6615129    245.14%           
                               4     15923029    590.06%           
                               5      8709903    322.77%           
                               6      6580254    243.85%           
                               7      4007808    148.52%           
                               8     39136514   1450.29%           
system.cpu.fetch.rateDist.max_value                 8                      
system.cpu.fetch.rateDist.end_dist

system.cpu.icache.ReadReq_accesses           63866189                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 32249.018798                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 30883.598563                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits               63861348                       # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency      156117500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate          0.000076                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses                 4841                       # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits               945                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency    120322500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate     0.000061                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses            3896                       # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.icache.avg_refs               16391.516427                       # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.demand_accesses            63866189                       # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 32249.018798                       # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 30883.598563                       # average overall mshr miss latency
system.cpu.icache.demand_hits                63861348                       # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency       156117500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate           0.000076                       # miss rate for demand accesses
system.cpu.icache.demand_misses                  4841                       # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits                945                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency    120322500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate      0.000061                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses             3896                       # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.overall_accesses           63866189                       # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 32249.018798                       # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 30883.598563                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.icache.overall_hits               63861348                       # number of overall hits
system.cpu.icache.overall_miss_latency      156117500                       # number of overall miss cycles
system.cpu.icache.overall_miss_rate          0.000076                       # miss rate for overall accesses
system.cpu.icache.overall_misses                 4841                       # number of overall misses
system.cpu.icache.overall_mshr_hits               945                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency    120322500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate     0.000061                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses            3896                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.replacements                   1975                       # number of replacements
system.cpu.icache.sampled_refs                   3896                       # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse               1823.540410                       # Cycle average of tags in use
system.cpu.icache.total_refs                 63861348                       # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks                        0                       # number of writebacks
system.cpu.idleCycles                          140725                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches                 50976851                       # Number of branches executed
system.cpu.iew.EXEC:nop                      27164335                       # number of nop insts executed
system.cpu.iew.EXEC:rate                     1.553144                       # Inst execution rate
system.cpu.iew.EXEC:refs                    191842297                       # number of memory reference insts executed
system.cpu.iew.EXEC:stores                   80676625                       # Number of stores executed
system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
system.cpu.iew.WB:consumers                 285463485                       # num instructions consuming a value
system.cpu.iew.WB:count                     415481237                       # cumulative count of insts written-back
system.cpu.iew.WB:fanout                     0.703314                       # average fanout of values written-back
system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers                 200770520                       # num instructions producing a value
system.cpu.iew.WB:rate                       1.538857                       # insts written-back per cycle
system.cpu.iew.WB:sent                      416287464                       # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts              6390313                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles                 2178518                       # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts             124841223                       # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts                239                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts           6302760                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts             92324076                       # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts           493447669                       # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts             111165672                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          10261544                       # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts             419338652                       # Number of executed instructions
system.cpu.iew.iewIQFullEvents                  25079                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents                 23746                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles               15306974                       # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles                341836                       # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked           30                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads         8734674                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses         2193                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation       436213                       # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads       176181                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads     24189228                       # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores     18792674                       # Number of stores squashed
system.cpu.iew.memOrderViolationEvents         436213                       # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect       847804                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect        5542509                       # Number of branches that were predicted taken incorrectly
system.cpu.ipc                               1.391052                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.391052                       # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0               429600196                       # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
                      No_OpClass        33581      0.01%            # Type of FU issued
                          IntAlu    166319014     38.71%            # Type of FU issued
                         IntMult      2152935      0.50%            # Type of FU issued
                          IntDiv            0      0.00%            # Type of FU issued
                        FloatAdd     35077566      8.17%            # Type of FU issued
                        FloatCmp      7830879      1.82%            # Type of FU issued
                        FloatCvt      2898460      0.67%            # Type of FU issued
                       FloatMult     16788316      3.91%            # Type of FU issued
                        FloatDiv      1569716      0.37%            # Type of FU issued
                       FloatSqrt            0      0.00%            # Type of FU issued
                         MemRead    113503270     26.42%            # Type of FU issued
                        MemWrite     83426459     19.42%            # Type of FU issued
                       IprAccess            0      0.00%            # Type of FU issued
                    InstPrefetch            0      0.00%            # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt              10457046                       # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate             0.024341                       # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
                      No_OpClass            0      0.00%            # attempts to use FU when none available
                          IntAlu        40640      0.39%            # attempts to use FU when none available
                         IntMult            0      0.00%            # attempts to use FU when none available
                          IntDiv            0      0.00%            # attempts to use FU when none available
                        FloatAdd        76056      0.73%            # attempts to use FU when none available
                        FloatCmp        13381      0.13%            # attempts to use FU when none available
                        FloatCvt        12891      0.12%            # attempts to use FU when none available
                       FloatMult      1723474     16.48%            # attempts to use FU when none available
                        FloatDiv      1473560     14.09%            # attempts to use FU when none available
                       FloatSqrt            0      0.00%            # attempts to use FU when none available
                         MemRead      5907144     56.49%            # attempts to use FU when none available
                        MemWrite      1209900     11.57%            # attempts to use FU when none available
                       IprAccess            0      0.00%            # attempts to use FU when none available
                    InstPrefetch            0      0.00%            # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist                     # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle.samples    269852647                      
system.cpu.iq.ISSUE:issued_per_cycle.min_value            0                      
                               0     99465935   3685.94%           
                               1     57766030   2140.65%           
                               2     39984554   1481.72%           
                               3     29664959   1099.30%           
                               4     23966120    888.12%           
                               5     10452563    387.34%           
                               6      5712016    211.67%           
                               7      2252970     83.49%           
                               8       587500     21.77%           
system.cpu.iq.ISSUE:issued_per_cycle.max_value            8                      
system.cpu.iq.ISSUE:issued_per_cycle.end_dist

system.cpu.iq.ISSUE:rate                     1.591151                       # Inst issue rate
system.cpu.iq.iqInstsAdded                  466283095                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued                 429600196                       # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded                 239                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined        89615992                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued            918381                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved             24                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined     68228113                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses                      63866476                       # ITB accesses
system.cpu.itb.acv                                  0                       # ITB acv
system.cpu.itb.hits                          63866189                       # ITB hits
system.cpu.itb.misses                             287                       # ITB misses
system.cpu.l2cache.ReadExReq_accesses            3197                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34596.340006                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31467.625899                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency    110604499                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses              3197                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency    100602000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses         3197                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses              4876                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34359.867330                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31168.325041                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits                   655                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency     145033000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate         0.865669                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses                4221                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency    131561500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate     0.865669                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses           4221                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_accesses            119                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34441.176471                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31285.714286                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_miss_latency      4098500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_misses              119                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency      3723000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_misses          119                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses             635                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits                 635                       # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles_no_mshrs         3000                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs                  0.130240                       # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs                 2                       # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs         6000                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.demand_accesses               8073                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34461.782017                       # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31297.317336                       # average overall mshr miss latency
system.cpu.l2cache.demand_hits                    655                       # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency      255637499                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate          0.918865                       # miss rate for demand accesses
system.cpu.l2cache.demand_misses                 7418                       # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency    232163500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate     0.918865                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses            7418                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses              8073                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34461.782017                       # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31297.317336                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits                   655                       # number of overall hits
system.cpu.l2cache.overall_miss_latency     255637499                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate         0.918865                       # miss rate for overall accesses
system.cpu.l2cache.overall_misses                7418                       # number of overall misses
system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency    232163500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate     0.918865                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses           7418                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements                    14                       # number of replacements
system.cpu.l2cache.sampled_refs                  4676                       # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse              3875.343408                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                     609                       # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks                       0                       # number of writebacks
system.cpu.numCycles                        269993372                       # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles          8452992                       # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps      259532341                       # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents         1780176                       # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles         137359458                       # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents        7392558                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents              2                       # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups      684397837                       # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts       518816398                       # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands    335732022                       # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles           97960614                       # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles        15306974                       # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles       10399659                       # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps          76199681                       # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles       372950                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts        37950                       # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts           22290547                       # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts          251                       # count of temporary serializing insts renamed
system.cpu.timesIdled                            3086                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls             215                       # Number of system calls

---------- End Simulation Statistics   ----------