2007-02-01 00:47:23 +01:00
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---------- Begin Simulation Statistics ----------
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global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2007-08-13 01:43:55 +02:00
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global.BPredUnit.BTBHits 38073438 # Number of BTB hits
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global.BPredUnit.BTBLookups 45542237 # Number of BTB lookups
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global.BPredUnit.RASInCorrect 1066 # Number of incorrect RAS predictions.
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global.BPredUnit.condIncorrect 5897861 # Number of conditional branches incorrect
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global.BPredUnit.condPredicted 35152227 # Number of conditional branches predicted
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global.BPredUnit.lookups 62262084 # Number of BP lookups
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global.BPredUnit.usedRAS 12565322 # Number of times the RAS was used to get a target.
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host_inst_rate 169929 # Simulator instruction rate (inst/s)
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host_mem_usage 207944 # Number of bytes of host memory used
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host_seconds 2210.19 # Real time elapsed on the host
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host_tick_rate 59827386 # Simulator tick rate (ticks/s)
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memdepunit.memDep.conflictingLoads 71764383 # Number of conflicting loads.
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memdepunit.memDep.conflictingStores 51661369 # Number of conflicting stores.
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memdepunit.memDep.insertedLoads 124318593 # Number of loads inserted to the mem dependence unit.
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memdepunit.memDep.insertedStores 91863744 # Number of stores inserted to the mem dependence unit.
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2007-02-01 00:47:23 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2007-08-13 01:43:55 +02:00
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sim_insts 375574833 # Number of instructions simulated
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sim_seconds 0.132230 # Number of seconds simulated
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sim_ticks 132229900500 # Number of ticks simulated
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system.cpu.commit.COM:branches 44587535 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 12177812 # number cycles where commit BW limit reached
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2007-02-01 00:47:23 +01:00
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
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2007-08-13 01:43:55 +02:00
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system.cpu.commit.COM:committed_per_cycle.samples 249309209
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2007-02-01 00:47:23 +01:00
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system.cpu.commit.COM:committed_per_cycle.min_value 0
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2007-08-13 01:43:55 +02:00
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0 114305349 4584.88%
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1 51380693 2060.92%
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2 21363734 856.92%
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3 20883024 837.64%
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4 12699516 509.39%
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5 8486510 340.40%
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6 4833732 193.89%
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7 3178839 127.51%
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8 12177812 488.46%
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2007-02-01 00:47:23 +01:00
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system.cpu.commit.COM:committed_per_cycle.max_value 8
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system.cpu.commit.COM:committed_per_cycle.end_dist
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2007-08-13 01:43:55 +02:00
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system.cpu.commit.COM:count 398664608 # Number of instructions committed
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system.cpu.commit.COM:loads 100651996 # Number of loads committed
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2007-02-01 00:47:23 +01:00
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system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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2007-08-13 01:43:55 +02:00
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system.cpu.commit.COM:refs 174183399 # Number of memory references committed
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2007-02-01 00:47:23 +01:00
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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2007-08-13 01:43:55 +02:00
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system.cpu.commit.branchMispredicts 5893662 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 398664608 # The number of committed instructions
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2007-02-01 00:47:23 +01:00
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system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
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2007-08-13 01:43:55 +02:00
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system.cpu.commit.commitSquashedInsts 93436434 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 375574833 # Number of Instructions Simulated
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system.cpu.committedInsts_total 375574833 # Number of Instructions Simulated
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system.cpu.cpi 0.704145 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.704145 # CPI: Total CPI of All Threads
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system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits
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system.cpu.dcache.ReadReq_accesses 96516428 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 11350.662589 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5775.739042 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 96515447 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 11135000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 981 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 512 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 5666000 # number of ReadReq MSHR miss cycles
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2007-02-01 00:47:23 +01:00
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
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2007-08-13 01:43:55 +02:00
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system.cpu.dcache.ReadReq_mshr_misses 981 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 73513288 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 23676.737160 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6083.836858 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 73509978 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 78370000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.000045 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 3310 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 7442 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 20137500 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 3310 # number of WriteReq MSHR misses
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2007-04-27 20:35:58 +02:00
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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2007-04-16 04:29:37 +02:00
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system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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2007-08-13 01:43:55 +02:00
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system.cpu.dcache.avg_refs 40714.928400 # Average number of references to valid blocks.
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2007-04-27 20:35:58 +02:00
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system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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2007-04-16 04:29:37 +02:00
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system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
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2007-04-27 20:35:58 +02:00
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system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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2007-04-16 04:29:37 +02:00
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system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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2007-02-01 00:47:23 +01:00
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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2007-08-13 01:43:55 +02:00
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system.cpu.dcache.demand_accesses 170029716 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 20858.774179 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 6013.400140 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 170025425 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 89505000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 4291 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 7954 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 25803500 # number of demand (read+write) MSHR miss cycles
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2007-02-01 00:47:23 +01:00
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system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
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2007-08-13 01:43:55 +02:00
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system.cpu.dcache.demand_mshr_misses 4291 # number of demand (read+write) MSHR misses
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2007-02-01 00:47:23 +01:00
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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2007-08-13 01:43:55 +02:00
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system.cpu.dcache.overall_accesses 170029716 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 20858.774179 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 6013.400140 # average overall mshr miss latency
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2007-02-01 00:47:23 +01:00
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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2007-08-13 01:43:55 +02:00
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system.cpu.dcache.overall_hits 170025425 # number of overall hits
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system.cpu.dcache.overall_miss_latency 89505000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 4291 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 7954 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 25803500 # number of overall MSHR miss cycles
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2007-02-01 00:47:23 +01:00
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system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
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2007-08-13 01:43:55 +02:00
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system.cpu.dcache.overall_mshr_misses 4291 # number of overall MSHR misses
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2007-02-01 00:47:23 +01:00
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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2007-08-13 01:43:55 +02:00
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system.cpu.dcache.replacements 780 # number of replacements
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2007-05-16 01:25:35 +02:00
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system.cpu.dcache.sampled_refs 4176 # Sample count of references to valid blocks.
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2007-02-01 00:47:23 +01:00
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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2007-08-13 01:43:55 +02:00
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system.cpu.dcache.tagsinuse 3294.806600 # Cycle average of tags in use
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system.cpu.dcache.total_refs 170025541 # Total number of references to valid blocks.
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2007-02-01 00:47:23 +01:00
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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2007-08-13 01:43:55 +02:00
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system.cpu.dcache.writebacks 635 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 14093330 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 4329 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 11426166 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 530907169 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 132358480 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 102072460 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 15149848 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 12784 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 784940 # Number of cycles decode is unblocking
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system.cpu.fetch.Branches 62262084 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 64149519 # Number of cache lines fetched
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system.cpu.fetch.Cycles 169628877 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 1267942 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 544672632 # Number of instructions fetch has processed
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system.cpu.fetch.SquashCycles 6256256 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.235432 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 64149519 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 50638760 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 2.059573 # Number of inst fetches per cycle
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2007-02-01 00:47:23 +01:00
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system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
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2007-08-13 01:43:55 +02:00
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system.cpu.fetch.rateDist.samples 264459058
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2007-02-01 00:47:23 +01:00
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system.cpu.fetch.rateDist.min_value 0
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2007-08-13 01:43:55 +02:00
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|
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0 158979701 6011.51%
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1 11898103 449.90%
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2 12511338 473.09%
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|
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|
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3 6558243 247.99%
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|
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|
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4 15951093 603.16%
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|
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|
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5 8933216 337.79%
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|
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|
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6 6667977 252.14%
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|
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7 4076286 154.14%
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8 38883101 1470.29%
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2007-02-01 00:47:23 +01:00
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system.cpu.fetch.rateDist.max_value 8
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system.cpu.fetch.rateDist.end_dist
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2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.icache.ReadReq_accesses 64149331 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 7193.164363 # average ReadReq miss latency
|
|
|
|
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 5001.152074 # average ReadReq mshr miss latency
|
|
|
|
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system.cpu.icache.ReadReq_hits 64145425 # number of ReadReq hits
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|
|
|
|
system.cpu.icache.ReadReq_miss_latency 28096500 # number of ReadReq miss cycles
|
|
|
|
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system.cpu.icache.ReadReq_miss_rate 0.000061 # miss rate for ReadReq accesses
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|
|
|
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system.cpu.icache.ReadReq_misses 3906 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 188 # number of ReadReq MSHR hits
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|
|
|
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system.cpu.icache.ReadReq_mshr_miss_latency 19534500 # number of ReadReq MSHR miss cycles
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|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000061 # mshr miss rate for ReadReq accesses
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|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 3906 # number of ReadReq MSHR misses
|
2007-04-16 04:29:37 +02:00
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|
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system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
2007-08-13 01:43:55 +02:00
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|
|
system.cpu.icache.avg_refs 16422.279826 # Average number of references to valid blocks.
|
2007-02-01 00:47:23 +01:00
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|
|
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
2007-04-16 04:29:37 +02:00
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|
|
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2007-08-13 01:43:55 +02:00
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|
|
system.cpu.icache.demand_accesses 64149331 # number of demand (read+write) accesses
|
|
|
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system.cpu.icache.demand_avg_miss_latency 7193.164363 # average overall miss latency
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|
|
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system.cpu.icache.demand_avg_mshr_miss_latency 5001.152074 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_hits 64145425 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_miss_latency 28096500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.000061 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_misses 3906 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 188 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 19534500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000061 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 3906 # number of demand (read+write) MSHR misses
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.icache.overall_accesses 64149331 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 7193.164363 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 5001.152074 # average overall mshr miss latency
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.icache.overall_hits 64145425 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_miss_latency 28096500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.000061 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_misses 3906 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 188 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 19534500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000061 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 3906 # number of overall MSHR misses
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.icache.replacements 1984 # number of replacements
|
|
|
|
|
system.cpu.icache.sampled_refs 3906 # Sample count of references to valid blocks.
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.icache.tagsinuse 1827.150129 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 64145425 # Total number of references to valid blocks.
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.idleCycles 557628 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.iew.EXEC:branches 51104102 # Number of branches executed
|
|
|
|
|
system.cpu.iew.EXEC:nop 27319155 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.EXEC:rate 1.584545 # Inst execution rate
|
|
|
|
|
system.cpu.iew.EXEC:refs 191326029 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.EXEC:stores 79588041 # Number of stores executed
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.iew.WB:consumers 282498519 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.WB:count 414521159 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.WB:fanout 0.706139 # average fanout of values written-back
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.iew.WB:producers 199483248 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.WB:rate 1.567430 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.WB:sent 415435713 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.branchMispredicts 6236762 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewBlockCycles 2781988 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 124318593 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 240 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 6814163 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 91863744 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 492099709 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 111737988 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 8739319 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 419047233 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 168412 # Number of times the IQ has become full, causing a stall
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.iew.iewLSQFullEvents 50946 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewSquashCycles 15149848 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 506738 # Number of cycles IEW is unblocking
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2007-04-27 20:35:58 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.forwLoads 8219638 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 31016 # Number of memory responses ignored because the instruction is squashed
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 502753 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 178119 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 23666597 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedStores 18332341 # Number of stores squashed
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 502753 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 955669 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 5281093 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.ipc 1.420162 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.420162 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0 427786552 # Type of FU issued
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
2007-08-13 01:43:55 +02:00
|
|
|
No_OpClass 33581 0.01% # Type of FU issued
|
|
|
|
|
IntAlu 166519693 38.93% # Type of FU issued
|
|
|
|
|
IntMult 2147905 0.50% # Type of FU issued
|
2007-02-01 00:47:23 +01:00
|
|
|
IntDiv 0 0.00% # Type of FU issued
|
2007-08-13 01:43:55 +02:00
|
|
|
FloatAdd 35254026 8.24% # Type of FU issued
|
|
|
|
|
FloatCmp 7817685 1.83% # Type of FU issued
|
|
|
|
|
FloatCvt 2969947 0.69% # Type of FU issued
|
|
|
|
|
FloatMult 16787400 3.92% # Type of FU issued
|
|
|
|
|
FloatDiv 1570522 0.37% # Type of FU issued
|
2007-02-01 00:47:23 +01:00
|
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
2007-08-13 01:43:55 +02:00
|
|
|
MemRead 113248293 26.47% # Type of FU issued
|
|
|
|
|
MemWrite 81437500 19.04% # Type of FU issued
|
2007-02-01 00:47:23 +01:00
|
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
|
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 9448608 # FU busy when requested
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.022087 # FU busy rate (busy events/executed inst)
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
2007-08-13 01:43:55 +02:00
|
|
|
No_OpClass 0 0.00% # attempts to use FU when none available
|
|
|
|
|
IntAlu 17181 0.18% # attempts to use FU when none available
|
2007-02-01 00:47:23 +01:00
|
|
|
IntMult 0 0.00% # attempts to use FU when none available
|
|
|
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
2007-08-13 01:43:55 +02:00
|
|
|
FloatAdd 604 0.01% # attempts to use FU when none available
|
|
|
|
|
FloatCmp 32516 0.34% # attempts to use FU when none available
|
|
|
|
|
FloatCvt 8012 0.08% # attempts to use FU when none available
|
|
|
|
|
FloatMult 2137313 22.62% # attempts to use FU when none available
|
|
|
|
|
FloatDiv 917798 9.71% # attempts to use FU when none available
|
2007-02-01 00:47:23 +01:00
|
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
2007-08-13 01:43:55 +02:00
|
|
|
MemRead 5261958 55.69% # attempts to use FU when none available
|
|
|
|
|
MemWrite 1073226 11.36% # attempts to use FU when none available
|
2007-02-01 00:47:23 +01:00
|
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
|
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.samples 264459058
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
2007-08-13 01:43:55 +02:00
|
|
|
0 94473273 3572.32%
|
|
|
|
|
1 57538428 2175.70%
|
|
|
|
|
2 41283183 1561.04%
|
|
|
|
|
3 28951087 1094.73%
|
|
|
|
|
4 22152944 837.67%
|
|
|
|
|
5 11939207 451.46%
|
|
|
|
|
6 5137200 194.25%
|
|
|
|
|
7 2172402 82.15%
|
|
|
|
|
8 811334 30.68%
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
|
|
|
|
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.iq.ISSUE:rate 1.617591 # Inst issue rate
|
|
|
|
|
system.cpu.iq.iqInstsAdded 464780314 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqInstsIssued 427786552 # Number of instructions issued
|
|
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 240 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu.iq.iqSquashedInstsExamined 88460147 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 742026 # Number of squashed instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 25 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 67499517 # Number of squashed operands that are examined and possibly removed from graph
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses 3199 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 4646.764614 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2646.764614 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 14865000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 3199 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 8467000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 3199 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 4883 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 4356.375525 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2356.375525 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 601 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 18654000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.876920 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 4282 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 10090000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.876920 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 4282 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses 117 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 4482.905983 # average UpgradeReq miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2482.905983 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_latency 524500 # number of UpgradeReq miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses 117 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 290500 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 117 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 635 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
|
|
|
|
|
system.cpu.l2cache.Writeback_misses 635 # number of Writeback misses
|
|
|
|
|
system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
|
|
|
|
|
system.cpu.l2cache.Writeback_mshr_misses 635 # number of Writeback MSHR misses
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.l2cache.avg_refs 0.139496 # Average number of references to valid blocks.
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.l2cache.demand_accesses 8082 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 4480.550729 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 2480.550729 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_hits 601 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 33519000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.925637 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_misses 7481 # number of demand (read+write) misses
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 18557000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.925637 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 7481 # number of demand (read+write) MSHR misses
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.l2cache.overall_accesses 8082 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 4480.550729 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 2480.550729 # average overall mshr miss latency
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.l2cache.overall_hits 601 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 33519000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.925637 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_misses 7481 # number of overall misses
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 18557000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.925637 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 7481 # number of overall MSHR misses
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.l2cache.replacements 6 # number of replacements
|
|
|
|
|
system.cpu.l2cache.sampled_refs 4165 # Sample count of references to valid blocks.
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 3521.188558 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 581 # Total number of references to valid blocks.
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.numCycles 264459058 # number of cpu cycles simulated
|
|
|
|
|
system.cpu.rename.RENAME:BlockCycles 6942912 # Number of cycles rename is blocking
|
|
|
|
|
system.cpu.rename.RENAME:CommittedMaps 259532351 # Number of HB maps that are committed
|
|
|
|
|
system.cpu.rename.RENAME:IQFullEvents 1128496 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.RENAME:IdleCycles 136398173 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.RENAME:LSQFullEvents 4996172 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu.rename.RENAME:RenameLookups 682131973 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.RENAME:RenamedInsts 517993086 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.RENAME:RenamedOperands 334891535 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RENAME:RunCycles 98637930 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.RENAME:SquashCycles 15149848 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.RENAME:UnblockCycles 6975590 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RENAME:UndoneMaps 75359184 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.RENAME:serializeStallCycles 354605 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RENAME:serializingInsts 37909 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.RENAME:skidInsts 15667924 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.rename.RENAME:tempSerializingInsts 253 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu.timesIdled 375 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
