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gem5/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt

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Add short memtest run to quick regressions. Caveats: - Even though memtest is ISA-independent, it will only run for the Alpha builds, since there's no way to specify ISA-independent reference files and I didn't want to commit 3 copies since I'm not sure we want to run it for all the different ISAs anyway. - Reference outputs were generated on my laptop, so performance numbers will be low compared to zizzer. --HG-- extra : convert_revision : 210fe4abecc19fbab0b15402c6cb4863650bab66
2007-02-07 06:16:33 +01:00
---------- Begin Simulation Statistics ----------
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
sim_seconds 0.000473 # Number of seconds simulated
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
sim_ticks 473398500 # Number of ticks simulated
final_tick 473398500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
host_tick_rate 74773462 # Simulator tick rate (ticks/s)
host_mem_usage 221944 # Number of bytes of host memory used
host_seconds 6.33 # Real time elapsed on the host
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.physmem.bytes_read::cpu0 85610 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1 86349 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2 81279 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3 82686 # Number of bytes read from this memory
system.physmem.bytes_read::cpu4 83314 # Number of bytes read from this memory
system.physmem.bytes_read::cpu5 81031 # Number of bytes read from this memory
system.physmem.bytes_read::cpu6 83113 # Number of bytes read from this memory
system.physmem.bytes_read::cpu7 86498 # Number of bytes read from this memory
system.physmem.bytes_read::total 669880 # Number of bytes read from this memory
system.physmem.bytes_written::writebacks 430080 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0 5517 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1 5460 # Number of bytes written to this memory
system.physmem.bytes_written::cpu2 5549 # Number of bytes written to this memory
system.physmem.bytes_written::cpu3 5366 # Number of bytes written to this memory
system.physmem.bytes_written::cpu4 5369 # Number of bytes written to this memory
system.physmem.bytes_written::cpu5 5497 # Number of bytes written to this memory
system.physmem.bytes_written::cpu6 5427 # Number of bytes written to this memory
system.physmem.bytes_written::cpu7 5336 # Number of bytes written to this memory
system.physmem.bytes_written::total 473601 # Number of bytes written to this memory
system.physmem.num_reads::cpu0 11018 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1 11064 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2 10845 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3 10992 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu4 10927 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu5 11038 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu6 10915 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu7 10898 # Number of read requests responded to by this memory
system.physmem.num_reads::total 87697 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 6720 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0 5517 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1 5460 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu2 5549 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu3 5366 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu4 5369 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu5 5497 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu6 5427 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu7 5336 # Number of write requests responded to by this memory
system.physmem.num_writes::total 50241 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0 180841300 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1 182402352 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2 171692559 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3 174664685 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu4 175991263 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu5 171168688 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu6 175566674 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu7 182717098 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1415044619 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 908494640 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0 11654029 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1 11533623 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu2 11721626 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu3 11335059 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu4 11341396 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu5 11611782 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu6 11463915 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu7 11271688 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1000427758 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 908494640 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0 192495329 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1 193935976 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2 183414185 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3 185999744 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu4 187332659 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu5 182780469 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu6 187030588 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu7 193988785 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2415472377 # Total bandwidth to/from this memory (bytes/s)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu0.num_reads 99308 # number of read accesses completed
system.cpu0.num_writes 55247 # number of write accesses completed
system.cpu0.l1c.tags.replacements 22271 # number of replacements
system.cpu0.l1c.tags.tagsinuse 390.476059 # Cycle average of tags in use
system.cpu0.l1c.tags.total_refs 13537 # Total number of references to valid blocks.
system.cpu0.l1c.tags.sampled_refs 22673 # Sample count of references to valid blocks.
system.cpu0.l1c.tags.avg_refs 0.597054 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu0.l1c.tags.occ_blocks::cpu0 390.476059 # Average occupied blocks per requestor
system.cpu0.l1c.tags.occ_percent::cpu0 0.762649 # Average percentage of cache occupancy
system.cpu0.l1c.tags.occ_percent::total 0.762649 # Average percentage of cache occupancy
system.cpu0.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
system.cpu0.l1c.tags.age_task_id_blocks_1024::0 391 # Occupied blocks per task id
system.cpu0.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id
system.cpu0.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
system.cpu0.l1c.tags.tag_accesses 337706 # Number of tag accesses
system.cpu0.l1c.tags.data_accesses 337706 # Number of data accesses
system.cpu0.l1c.ReadReq_hits::cpu0 8778 # number of ReadReq hits
system.cpu0.l1c.ReadReq_hits::total 8778 # number of ReadReq hits
system.cpu0.l1c.WriteReq_hits::cpu0 1202 # number of WriteReq hits
system.cpu0.l1c.WriteReq_hits::total 1202 # number of WriteReq hits
system.cpu0.l1c.demand_hits::cpu0 9980 # number of demand (read+write) hits
system.cpu0.l1c.demand_hits::total 9980 # number of demand (read+write) hits
system.cpu0.l1c.overall_hits::cpu0 9980 # number of overall hits
system.cpu0.l1c.overall_hits::total 9980 # number of overall hits
system.cpu0.l1c.ReadReq_misses::cpu0 36312 # number of ReadReq misses
system.cpu0.l1c.ReadReq_misses::total 36312 # number of ReadReq misses
system.cpu0.l1c.WriteReq_misses::cpu0 23969 # number of WriteReq misses
system.cpu0.l1c.WriteReq_misses::total 23969 # number of WriteReq misses
system.cpu0.l1c.demand_misses::cpu0 60281 # number of demand (read+write) misses
system.cpu0.l1c.demand_misses::total 60281 # number of demand (read+write) misses
system.cpu0.l1c.overall_misses::cpu0 60281 # number of overall misses
system.cpu0.l1c.overall_misses::total 60281 # number of overall misses
system.cpu0.l1c.ReadReq_miss_latency::cpu0 585914746 # number of ReadReq miss cycles
system.cpu0.l1c.ReadReq_miss_latency::total 585914746 # number of ReadReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::cpu0 661973304 # number of WriteReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::total 661973304 # number of WriteReq miss cycles
system.cpu0.l1c.demand_miss_latency::cpu0 1247888050 # number of demand (read+write) miss cycles
system.cpu0.l1c.demand_miss_latency::total 1247888050 # number of demand (read+write) miss cycles
system.cpu0.l1c.overall_miss_latency::cpu0 1247888050 # number of overall miss cycles
system.cpu0.l1c.overall_miss_latency::total 1247888050 # number of overall miss cycles
system.cpu0.l1c.ReadReq_accesses::cpu0 45090 # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.ReadReq_accesses::total 45090 # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::cpu0 25171 # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::total 25171 # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.demand_accesses::cpu0 70261 # number of demand (read+write) accesses
system.cpu0.l1c.demand_accesses::total 70261 # number of demand (read+write) accesses
system.cpu0.l1c.overall_accesses::cpu0 70261 # number of overall (read+write) accesses
system.cpu0.l1c.overall_accesses::total 70261 # number of overall (read+write) accesses
system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.805323 # miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_miss_rate::total 0.805323 # miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.952247 # miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_miss_rate::total 0.952247 # miss rate for WriteReq accesses
system.cpu0.l1c.demand_miss_rate::cpu0 0.857958 # miss rate for demand accesses
system.cpu0.l1c.demand_miss_rate::total 0.857958 # miss rate for demand accesses
system.cpu0.l1c.overall_miss_rate::cpu0 0.857958 # miss rate for overall accesses
system.cpu0.l1c.overall_miss_rate::total 0.857958 # miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16135.568022 # average ReadReq miss latency
system.cpu0.l1c.ReadReq_avg_miss_latency::total 16135.568022 # average ReadReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 27617.894113 # average WriteReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::total 27617.894113 # average WriteReq miss latency
system.cpu0.l1c.demand_avg_miss_latency::cpu0 20701.183623 # average overall miss latency
system.cpu0.l1c.demand_avg_miss_latency::total 20701.183623 # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::cpu0 20701.183623 # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::total 20701.183623 # average overall miss latency
system.cpu0.l1c.blocked_cycles::no_mshrs 772989 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu0.l1c.blocked::no_mshrs 66053 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu0.l1c.avg_blocked_cycles::no_mshrs 11.702557 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.l1c.fast_writes 0 # number of fast writes performed
system.cpu0.l1c.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu0.l1c.writebacks::writebacks 9819 # number of writebacks
system.cpu0.l1c.writebacks::total 9819 # number of writebacks
system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36312 # number of ReadReq MSHR misses
system.cpu0.l1c.ReadReq_mshr_misses::total 36312 # number of ReadReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23969 # number of WriteReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::total 23969 # number of WriteReq MSHR misses
system.cpu0.l1c.demand_mshr_misses::cpu0 60281 # number of demand (read+write) MSHR misses
system.cpu0.l1c.demand_mshr_misses::total 60281 # number of demand (read+write) MSHR misses
system.cpu0.l1c.overall_mshr_misses::cpu0 60281 # number of overall MSHR misses
system.cpu0.l1c.overall_mshr_misses::total 60281 # number of overall MSHR misses
system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9835 # number of ReadReq MSHR uncacheable
system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9835 # number of ReadReq MSHR uncacheable
system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5519 # number of WriteReq MSHR uncacheable
system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5519 # number of WriteReq MSHR uncacheable
system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15354 # number of overall MSHR uncacheable misses
system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15354 # number of overall MSHR uncacheable misses
system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 529167946 # number of ReadReq MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_miss_latency::total 529167946 # number of ReadReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 625061532 # number of WriteReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::total 625061532 # number of WriteReq MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1154229478 # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::total 1154229478 # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1154229478 # number of overall MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::total 1154229478 # number of overall MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 639072193 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 639072193 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 970312557 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 970312557 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1609384750 # number of overall MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1609384750 # number of overall MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.805323 # mshr miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.805323 # mshr miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.952247 # mshr miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.952247 # mshr miss rate for WriteReq accesses
system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.857958 # mshr miss rate for demand accesses
system.cpu0.l1c.demand_mshr_miss_rate::total 0.857958 # mshr miss rate for demand accesses
system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.857958 # mshr miss rate for overall accesses
system.cpu0.l1c.overall_mshr_miss_rate::total 0.857958 # mshr miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 14572.811908 # average ReadReq mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 14572.811908 # average ReadReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 26077.914473 # average WriteReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 26077.914473 # average WriteReq mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 19147.483917 # average overall mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::total 19147.483917 # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 19147.483917 # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::total 19147.483917 # average overall mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 64979.379054 # average ReadReq mshr uncacheable latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64979.379054 # average ReadReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 175813.110527 # average WriteReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 175813.110527 # average WriteReq mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 104818.597760 # average overall mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 104818.597760 # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu1.num_reads 98972 # number of read accesses completed
system.cpu1.num_writes 54740 # number of write accesses completed
system.cpu1.l1c.tags.replacements 21894 # number of replacements
system.cpu1.l1c.tags.tagsinuse 389.013692 # Cycle average of tags in use
system.cpu1.l1c.tags.total_refs 13227 # Total number of references to valid blocks.
system.cpu1.l1c.tags.sampled_refs 22299 # Sample count of references to valid blocks.
system.cpu1.l1c.tags.avg_refs 0.593166 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu1.l1c.tags.occ_blocks::cpu1 389.013692 # Average occupied blocks per requestor
system.cpu1.l1c.tags.occ_percent::cpu1 0.759792 # Average percentage of cache occupancy
system.cpu1.l1c.tags.occ_percent::total 0.759792 # Average percentage of cache occupancy
system.cpu1.l1c.tags.occ_task_id_blocks::1024 405 # Occupied blocks per task id
system.cpu1.l1c.tags.age_task_id_blocks_1024::0 401 # Occupied blocks per task id
system.cpu1.l1c.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
system.cpu1.l1c.tags.occ_task_id_percent::1024 0.791016 # Percentage of cache occupancy per task id
system.cpu1.l1c.tags.tag_accesses 335323 # Number of tag accesses
system.cpu1.l1c.tags.data_accesses 335323 # Number of data accesses
system.cpu1.l1c.ReadReq_hits::cpu1 8521 # number of ReadReq hits
system.cpu1.l1c.ReadReq_hits::total 8521 # number of ReadReq hits
system.cpu1.l1c.WriteReq_hits::cpu1 1152 # number of WriteReq hits
system.cpu1.l1c.WriteReq_hits::total 1152 # number of WriteReq hits
system.cpu1.l1c.demand_hits::cpu1 9673 # number of demand (read+write) hits
system.cpu1.l1c.demand_hits::total 9673 # number of demand (read+write) hits
system.cpu1.l1c.overall_hits::cpu1 9673 # number of overall hits
system.cpu1.l1c.overall_hits::total 9673 # number of overall hits
system.cpu1.l1c.ReadReq_misses::cpu1 36191 # number of ReadReq misses
system.cpu1.l1c.ReadReq_misses::total 36191 # number of ReadReq misses
system.cpu1.l1c.WriteReq_misses::cpu1 23860 # number of WriteReq misses
system.cpu1.l1c.WriteReq_misses::total 23860 # number of WriteReq misses
system.cpu1.l1c.demand_misses::cpu1 60051 # number of demand (read+write) misses
system.cpu1.l1c.demand_misses::total 60051 # number of demand (read+write) misses
system.cpu1.l1c.overall_misses::cpu1 60051 # number of overall misses
system.cpu1.l1c.overall_misses::total 60051 # number of overall misses
system.cpu1.l1c.ReadReq_miss_latency::cpu1 587357926 # number of ReadReq miss cycles
system.cpu1.l1c.ReadReq_miss_latency::total 587357926 # number of ReadReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::cpu1 665550173 # number of WriteReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::total 665550173 # number of WriteReq miss cycles
system.cpu1.l1c.demand_miss_latency::cpu1 1252908099 # number of demand (read+write) miss cycles
system.cpu1.l1c.demand_miss_latency::total 1252908099 # number of demand (read+write) miss cycles
system.cpu1.l1c.overall_miss_latency::cpu1 1252908099 # number of overall miss cycles
system.cpu1.l1c.overall_miss_latency::total 1252908099 # number of overall miss cycles
system.cpu1.l1c.ReadReq_accesses::cpu1 44712 # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.ReadReq_accesses::total 44712 # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::cpu1 25012 # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::total 25012 # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.demand_accesses::cpu1 69724 # number of demand (read+write) accesses
system.cpu1.l1c.demand_accesses::total 69724 # number of demand (read+write) accesses
system.cpu1.l1c.overall_accesses::cpu1 69724 # number of overall (read+write) accesses
system.cpu1.l1c.overall_accesses::total 69724 # number of overall (read+write) accesses
system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.809425 # miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_miss_rate::total 0.809425 # miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.953942 # miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_miss_rate::total 0.953942 # miss rate for WriteReq accesses
system.cpu1.l1c.demand_miss_rate::cpu1 0.861267 # miss rate for demand accesses
system.cpu1.l1c.demand_miss_rate::total 0.861267 # miss rate for demand accesses
system.cpu1.l1c.overall_miss_rate::cpu1 0.861267 # miss rate for overall accesses
system.cpu1.l1c.overall_miss_rate::total 0.861267 # miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16229.392004 # average ReadReq miss latency
system.cpu1.l1c.ReadReq_avg_miss_latency::total 16229.392004 # average ReadReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 27893.972045 # average WriteReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::total 27893.972045 # average WriteReq miss latency
system.cpu1.l1c.demand_avg_miss_latency::cpu1 20864.067193 # average overall miss latency
system.cpu1.l1c.demand_avg_miss_latency::total 20864.067193 # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::cpu1 20864.067193 # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::total 20864.067193 # average overall miss latency
system.cpu1.l1c.blocked_cycles::no_mshrs 781068 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu1.l1c.blocked::no_mshrs 66159 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu1.l1c.avg_blocked_cycles::no_mshrs 11.805922 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.l1c.fast_writes 0 # number of fast writes performed
system.cpu1.l1c.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu1.l1c.writebacks::writebacks 9676 # number of writebacks
system.cpu1.l1c.writebacks::total 9676 # number of writebacks
system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36191 # number of ReadReq MSHR misses
system.cpu1.l1c.ReadReq_mshr_misses::total 36191 # number of ReadReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23860 # number of WriteReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::total 23860 # number of WriteReq MSHR misses
system.cpu1.l1c.demand_mshr_misses::cpu1 60051 # number of demand (read+write) MSHR misses
system.cpu1.l1c.demand_mshr_misses::total 60051 # number of demand (read+write) MSHR misses
system.cpu1.l1c.overall_mshr_misses::cpu1 60051 # number of overall MSHR misses
system.cpu1.l1c.overall_mshr_misses::total 60051 # number of overall MSHR misses
system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9870 # number of ReadReq MSHR uncacheable
system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9870 # number of ReadReq MSHR uncacheable
system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5462 # number of WriteReq MSHR uncacheable
system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5462 # number of WriteReq MSHR uncacheable
system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15332 # number of overall MSHR uncacheable misses
system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15332 # number of overall MSHR uncacheable misses
system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 530766130 # number of ReadReq MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_miss_latency::total 530766130 # number of ReadReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 628779775 # number of WriteReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::total 628779775 # number of WriteReq MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1159545905 # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::total 1159545905 # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1159545905 # number of overall MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::total 1159545905 # number of overall MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 639204350 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 639204350 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 954877634 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 954877634 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1594081984 # number of overall MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1594081984 # number of overall MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.809425 # mshr miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.809425 # mshr miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.953942 # mshr miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.953942 # mshr miss rate for WriteReq accesses
system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.861267 # mshr miss rate for demand accesses
system.cpu1.l1c.demand_mshr_miss_rate::total 0.861267 # mshr miss rate for demand accesses
system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.861267 # mshr miss rate for overall accesses
system.cpu1.l1c.overall_mshr_miss_rate::total 0.861267 # mshr miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 14665.693957 # average ReadReq mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 14665.693957 # average ReadReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 26352.882439 # average WriteReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 26352.882439 # average WriteReq mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 19309.352134 # average overall mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::total 19309.352134 # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 19309.352134 # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::total 19309.352134 # average overall mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 64762.345491 # average ReadReq mshr uncacheable latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64762.345491 # average ReadReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 174821.976199 # average WriteReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 174821.976199 # average WriteReq mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 103970.909470 # average overall mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 103970.909470 # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu2.num_reads 99459 # number of read accesses completed
system.cpu2.num_writes 55455 # number of write accesses completed
system.cpu2.l1c.tags.replacements 22538 # number of replacements
system.cpu2.l1c.tags.tagsinuse 392.681778 # Cycle average of tags in use
system.cpu2.l1c.tags.total_refs 13552 # Total number of references to valid blocks.
system.cpu2.l1c.tags.sampled_refs 22938 # Sample count of references to valid blocks.
system.cpu2.l1c.tags.avg_refs 0.590810 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu2.l1c.tags.occ_blocks::cpu2 392.681778 # Average occupied blocks per requestor
system.cpu2.l1c.tags.occ_percent::cpu2 0.766957 # Average percentage of cache occupancy
system.cpu2.l1c.tags.occ_percent::total 0.766957 # Average percentage of cache occupancy
system.cpu2.l1c.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id
system.cpu2.l1c.tags.age_task_id_blocks_1024::0 393 # Occupied blocks per task id
system.cpu2.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id
system.cpu2.l1c.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id
system.cpu2.l1c.tags.tag_accesses 337495 # Number of tag accesses
system.cpu2.l1c.tags.data_accesses 337495 # Number of data accesses
system.cpu2.l1c.ReadReq_hits::cpu2 8694 # number of ReadReq hits
system.cpu2.l1c.ReadReq_hits::total 8694 # number of ReadReq hits
system.cpu2.l1c.WriteReq_hits::cpu2 1182 # number of WriteReq hits
system.cpu2.l1c.WriteReq_hits::total 1182 # number of WriteReq hits
system.cpu2.l1c.demand_hits::cpu2 9876 # number of demand (read+write) hits
system.cpu2.l1c.demand_hits::total 9876 # number of demand (read+write) hits
system.cpu2.l1c.overall_hits::cpu2 9876 # number of overall hits
system.cpu2.l1c.overall_hits::total 9876 # number of overall hits
system.cpu2.l1c.ReadReq_misses::cpu2 36455 # number of ReadReq misses
system.cpu2.l1c.ReadReq_misses::total 36455 # number of ReadReq misses
system.cpu2.l1c.WriteReq_misses::cpu2 23891 # number of WriteReq misses
system.cpu2.l1c.WriteReq_misses::total 23891 # number of WriteReq misses
system.cpu2.l1c.demand_misses::cpu2 60346 # number of demand (read+write) misses
system.cpu2.l1c.demand_misses::total 60346 # number of demand (read+write) misses
system.cpu2.l1c.overall_misses::cpu2 60346 # number of overall misses
system.cpu2.l1c.overall_misses::total 60346 # number of overall misses
system.cpu2.l1c.ReadReq_miss_latency::cpu2 592802045 # number of ReadReq miss cycles
system.cpu2.l1c.ReadReq_miss_latency::total 592802045 # number of ReadReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::cpu2 663383699 # number of WriteReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::total 663383699 # number of WriteReq miss cycles
system.cpu2.l1c.demand_miss_latency::cpu2 1256185744 # number of demand (read+write) miss cycles
system.cpu2.l1c.demand_miss_latency::total 1256185744 # number of demand (read+write) miss cycles
system.cpu2.l1c.overall_miss_latency::cpu2 1256185744 # number of overall miss cycles
system.cpu2.l1c.overall_miss_latency::total 1256185744 # number of overall miss cycles
system.cpu2.l1c.ReadReq_accesses::cpu2 45149 # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.ReadReq_accesses::total 45149 # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::cpu2 25073 # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::total 25073 # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.demand_accesses::cpu2 70222 # number of demand (read+write) accesses
system.cpu2.l1c.demand_accesses::total 70222 # number of demand (read+write) accesses
system.cpu2.l1c.overall_accesses::cpu2 70222 # number of overall (read+write) accesses
system.cpu2.l1c.overall_accesses::total 70222 # number of overall (read+write) accesses
system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.807438 # miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_miss_rate::total 0.807438 # miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.952858 # miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_miss_rate::total 0.952858 # miss rate for WriteReq accesses
system.cpu2.l1c.demand_miss_rate::cpu2 0.859360 # miss rate for demand accesses
system.cpu2.l1c.demand_miss_rate::total 0.859360 # miss rate for demand accesses
system.cpu2.l1c.overall_miss_rate::cpu2 0.859360 # miss rate for overall accesses
system.cpu2.l1c.overall_miss_rate::total 0.859360 # miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16261.199973 # average ReadReq miss latency
system.cpu2.l1c.ReadReq_avg_miss_latency::total 16261.199973 # average ReadReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 27767.096354 # average WriteReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::total 27767.096354 # average WriteReq miss latency
system.cpu2.l1c.demand_avg_miss_latency::cpu2 20816.387896 # average overall miss latency
system.cpu2.l1c.demand_avg_miss_latency::total 20816.387896 # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::cpu2 20816.387896 # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::total 20816.387896 # average overall miss latency
system.cpu2.l1c.blocked_cycles::no_mshrs 773062 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu2.l1c.blocked::no_mshrs 66064 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu2.l1c.avg_blocked_cycles::no_mshrs 11.701713 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu2.l1c.fast_writes 0 # number of fast writes performed
system.cpu2.l1c.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu2.l1c.writebacks::writebacks 9793 # number of writebacks
system.cpu2.l1c.writebacks::total 9793 # number of writebacks
system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36455 # number of ReadReq MSHR misses
system.cpu2.l1c.ReadReq_mshr_misses::total 36455 # number of ReadReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23891 # number of WriteReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::total 23891 # number of WriteReq MSHR misses
system.cpu2.l1c.demand_mshr_misses::cpu2 60346 # number of demand (read+write) MSHR misses
system.cpu2.l1c.demand_mshr_misses::total 60346 # number of demand (read+write) MSHR misses
system.cpu2.l1c.overall_mshr_misses::cpu2 60346 # number of overall MSHR misses
system.cpu2.l1c.overall_mshr_misses::total 60346 # number of overall MSHR misses
system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9727 # number of ReadReq MSHR uncacheable
system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9727 # number of ReadReq MSHR uncacheable
system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5550 # number of WriteReq MSHR uncacheable
system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5550 # number of WriteReq MSHR uncacheable
system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15277 # number of overall MSHR uncacheable misses
system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15277 # number of overall MSHR uncacheable misses
system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 535820289 # number of ReadReq MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_miss_latency::total 535820289 # number of ReadReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 626605165 # number of WriteReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::total 626605165 # number of WriteReq MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1162425454 # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::total 1162425454 # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1162425454 # number of overall MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::total 1162425454 # number of overall MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 629981617 # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 629981617 # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 971621622 # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 971621622 # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1601603239 # number of overall MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1601603239 # number of overall MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.807438 # mshr miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.807438 # mshr miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.952858 # mshr miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.952858 # mshr miss rate for WriteReq accesses
system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.859360 # mshr miss rate for demand accesses
system.cpu2.l1c.demand_mshr_miss_rate::total 0.859360 # mshr miss rate for demand accesses
system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.859360 # mshr miss rate for overall accesses
system.cpu2.l1c.overall_mshr_miss_rate::total 0.859360 # mshr miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 14698.128899 # average ReadReq mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 14698.128899 # average ReadReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 26227.665857 # average WriteReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 26227.665857 # average WriteReq mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 19262.676134 # average overall mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::total 19262.676134 # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 19262.676134 # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::total 19262.676134 # average overall mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 64766.281176 # average ReadReq mshr uncacheable latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64766.281176 # average ReadReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 175066.958919 # average WriteReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 175066.958919 # average WriteReq mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 104837.549192 # average overall mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 104837.549192 # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu3.num_reads 99575 # number of read accesses completed
system.cpu3.num_writes 55091 # number of write accesses completed
system.cpu3.l1c.tags.replacements 22304 # number of replacements
system.cpu3.l1c.tags.tagsinuse 392.069306 # Cycle average of tags in use
system.cpu3.l1c.tags.total_refs 13533 # Total number of references to valid blocks.
system.cpu3.l1c.tags.sampled_refs 22710 # Sample count of references to valid blocks.
system.cpu3.l1c.tags.avg_refs 0.595905 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu3.l1c.tags.occ_blocks::cpu3 392.069306 # Average occupied blocks per requestor
system.cpu3.l1c.tags.occ_percent::cpu3 0.765760 # Average percentage of cache occupancy
system.cpu3.l1c.tags.occ_percent::total 0.765760 # Average percentage of cache occupancy
system.cpu3.l1c.tags.occ_task_id_blocks::1024 406 # Occupied blocks per task id
system.cpu3.l1c.tags.age_task_id_blocks_1024::0 399 # Occupied blocks per task id
system.cpu3.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id
system.cpu3.l1c.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id
system.cpu3.l1c.tags.tag_accesses 336765 # Number of tag accesses
system.cpu3.l1c.tags.data_accesses 336765 # Number of data accesses
system.cpu3.l1c.ReadReq_hits::cpu3 8633 # number of ReadReq hits
system.cpu3.l1c.ReadReq_hits::total 8633 # number of ReadReq hits
system.cpu3.l1c.WriteReq_hits::cpu3 1152 # number of WriteReq hits
system.cpu3.l1c.WriteReq_hits::total 1152 # number of WriteReq hits
system.cpu3.l1c.demand_hits::cpu3 9785 # number of demand (read+write) hits
system.cpu3.l1c.demand_hits::total 9785 # number of demand (read+write) hits
system.cpu3.l1c.overall_hits::cpu3 9785 # number of overall hits
system.cpu3.l1c.overall_hits::total 9785 # number of overall hits
system.cpu3.l1c.ReadReq_misses::cpu3 36428 # number of ReadReq misses
system.cpu3.l1c.ReadReq_misses::total 36428 # number of ReadReq misses
system.cpu3.l1c.WriteReq_misses::cpu3 23860 # number of WriteReq misses
system.cpu3.l1c.WriteReq_misses::total 23860 # number of WriteReq misses
system.cpu3.l1c.demand_misses::cpu3 60288 # number of demand (read+write) misses
system.cpu3.l1c.demand_misses::total 60288 # number of demand (read+write) misses
system.cpu3.l1c.overall_misses::cpu3 60288 # number of overall misses
system.cpu3.l1c.overall_misses::total 60288 # number of overall misses
system.cpu3.l1c.ReadReq_miss_latency::cpu3 584499068 # number of ReadReq miss cycles
system.cpu3.l1c.ReadReq_miss_latency::total 584499068 # number of ReadReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::cpu3 664565432 # number of WriteReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::total 664565432 # number of WriteReq miss cycles
system.cpu3.l1c.demand_miss_latency::cpu3 1249064500 # number of demand (read+write) miss cycles
system.cpu3.l1c.demand_miss_latency::total 1249064500 # number of demand (read+write) miss cycles
system.cpu3.l1c.overall_miss_latency::cpu3 1249064500 # number of overall miss cycles
system.cpu3.l1c.overall_miss_latency::total 1249064500 # number of overall miss cycles
system.cpu3.l1c.ReadReq_accesses::cpu3 45061 # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.ReadReq_accesses::total 45061 # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::cpu3 25012 # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::total 25012 # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.demand_accesses::cpu3 70073 # number of demand (read+write) accesses
system.cpu3.l1c.demand_accesses::total 70073 # number of demand (read+write) accesses
system.cpu3.l1c.overall_accesses::cpu3 70073 # number of overall (read+write) accesses
system.cpu3.l1c.overall_accesses::total 70073 # number of overall (read+write) accesses
system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.808415 # miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_miss_rate::total 0.808415 # miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.953942 # miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_miss_rate::total 0.953942 # miss rate for WriteReq accesses
system.cpu3.l1c.demand_miss_rate::cpu3 0.860360 # miss rate for demand accesses
system.cpu3.l1c.demand_miss_rate::total 0.860360 # miss rate for demand accesses
system.cpu3.l1c.overall_miss_rate::cpu3 0.860360 # miss rate for overall accesses
system.cpu3.l1c.overall_miss_rate::total 0.860360 # miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16045.324146 # average ReadReq miss latency
system.cpu3.l1c.ReadReq_avg_miss_latency::total 16045.324146 # average ReadReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 27852.700419 # average WriteReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::total 27852.700419 # average WriteReq miss latency
system.cpu3.l1c.demand_avg_miss_latency::cpu3 20718.293856 # average overall miss latency
system.cpu3.l1c.demand_avg_miss_latency::total 20718.293856 # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::cpu3 20718.293856 # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::total 20718.293856 # average overall miss latency
system.cpu3.l1c.blocked_cycles::no_mshrs 775679 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu3.l1c.blocked::no_mshrs 66211 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu3.l1c.avg_blocked_cycles::no_mshrs 11.715259 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu3.l1c.fast_writes 0 # number of fast writes performed
system.cpu3.l1c.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu3.l1c.writebacks::writebacks 9857 # number of writebacks
system.cpu3.l1c.writebacks::total 9857 # number of writebacks
system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36428 # number of ReadReq MSHR misses
system.cpu3.l1c.ReadReq_mshr_misses::total 36428 # number of ReadReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23860 # number of WriteReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::total 23860 # number of WriteReq MSHR misses
system.cpu3.l1c.demand_mshr_misses::cpu3 60288 # number of demand (read+write) MSHR misses
system.cpu3.l1c.demand_mshr_misses::total 60288 # number of demand (read+write) MSHR misses
system.cpu3.l1c.overall_mshr_misses::cpu3 60288 # number of overall MSHR misses
system.cpu3.l1c.overall_mshr_misses::total 60288 # number of overall MSHR misses
system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9854 # number of ReadReq MSHR uncacheable
system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9854 # number of ReadReq MSHR uncacheable
system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5367 # number of WriteReq MSHR uncacheable
system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5367 # number of WriteReq MSHR uncacheable
system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15221 # number of overall MSHR uncacheable misses
system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15221 # number of overall MSHR uncacheable misses
system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 527611348 # number of ReadReq MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_miss_latency::total 527611348 # number of ReadReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 627817964 # number of WriteReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::total 627817964 # number of WriteReq MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1155429312 # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::total 1155429312 # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1155429312 # number of overall MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::total 1155429312 # number of overall MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 639378023 # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 639378023 # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 962583192 # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 962583192 # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1601961215 # number of overall MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1601961215 # number of overall MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.808415 # mshr miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.808415 # mshr miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.953942 # mshr miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953942 # mshr miss rate for WriteReq accesses
system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.860360 # mshr miss rate for demand accesses
system.cpu3.l1c.demand_mshr_miss_rate::total 0.860360 # mshr miss rate for demand accesses
system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.860360 # mshr miss rate for overall accesses
system.cpu3.l1c.overall_mshr_miss_rate::total 0.860360 # mshr miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 14483.675964 # average ReadReq mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 14483.675964 # average ReadReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 26312.571836 # average WriteReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 26312.571836 # average WriteReq mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 19165.162420 # average overall mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::total 19165.162420 # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 19165.162420 # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::total 19165.162420 # average overall mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 64885.125127 # average ReadReq mshr uncacheable latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64885.125127 # average ReadReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 179352.187814 # average WriteReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 179352.187814 # average WriteReq mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 105246.778464 # average overall mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 105246.778464 # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu4.num_reads 99348 # number of read accesses completed
system.cpu4.num_writes 54723 # number of write accesses completed
system.cpu4.l1c.tags.replacements 22403 # number of replacements
system.cpu4.l1c.tags.tagsinuse 391.522543 # Cycle average of tags in use
system.cpu4.l1c.tags.total_refs 13385 # Total number of references to valid blocks.
system.cpu4.l1c.tags.sampled_refs 22785 # Sample count of references to valid blocks.
system.cpu4.l1c.tags.avg_refs 0.587448 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu4.l1c.tags.occ_blocks::cpu4 391.522543 # Average occupied blocks per requestor
system.cpu4.l1c.tags.occ_percent::cpu4 0.764692 # Average percentage of cache occupancy
system.cpu4.l1c.tags.occ_percent::total 0.764692 # Average percentage of cache occupancy
system.cpu4.l1c.tags.occ_task_id_blocks::1024 382 # Occupied blocks per task id
system.cpu4.l1c.tags.age_task_id_blocks_1024::0 381 # Occupied blocks per task id
system.cpu4.l1c.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
system.cpu4.l1c.tags.occ_task_id_percent::1024 0.746094 # Percentage of cache occupancy per task id
system.cpu4.l1c.tags.tag_accesses 337332 # Number of tag accesses
system.cpu4.l1c.tags.data_accesses 337332 # Number of data accesses
system.cpu4.l1c.ReadReq_hits::cpu4 8635 # number of ReadReq hits
system.cpu4.l1c.ReadReq_hits::total 8635 # number of ReadReq hits
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.cpu4.l1c.WriteReq_hits::cpu4 1108 # number of WriteReq hits
system.cpu4.l1c.WriteReq_hits::total 1108 # number of WriteReq hits
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu4.l1c.demand_hits::cpu4 9743 # number of demand (read+write) hits
system.cpu4.l1c.demand_hits::total 9743 # number of demand (read+write) hits
system.cpu4.l1c.overall_hits::cpu4 9743 # number of overall hits
system.cpu4.l1c.overall_hits::total 9743 # number of overall hits
system.cpu4.l1c.ReadReq_misses::cpu4 36706 # number of ReadReq misses
system.cpu4.l1c.ReadReq_misses::total 36706 # number of ReadReq misses
system.cpu4.l1c.WriteReq_misses::cpu4 23706 # number of WriteReq misses
system.cpu4.l1c.WriteReq_misses::total 23706 # number of WriteReq misses
system.cpu4.l1c.demand_misses::cpu4 60412 # number of demand (read+write) misses
system.cpu4.l1c.demand_misses::total 60412 # number of demand (read+write) misses
system.cpu4.l1c.overall_misses::cpu4 60412 # number of overall misses
system.cpu4.l1c.overall_misses::total 60412 # number of overall misses
system.cpu4.l1c.ReadReq_miss_latency::cpu4 597809741 # number of ReadReq miss cycles
system.cpu4.l1c.ReadReq_miss_latency::total 597809741 # number of ReadReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::cpu4 658168265 # number of WriteReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::total 658168265 # number of WriteReq miss cycles
system.cpu4.l1c.demand_miss_latency::cpu4 1255978006 # number of demand (read+write) miss cycles
system.cpu4.l1c.demand_miss_latency::total 1255978006 # number of demand (read+write) miss cycles
system.cpu4.l1c.overall_miss_latency::cpu4 1255978006 # number of overall miss cycles
system.cpu4.l1c.overall_miss_latency::total 1255978006 # number of overall miss cycles
system.cpu4.l1c.ReadReq_accesses::cpu4 45341 # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.ReadReq_accesses::total 45341 # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::cpu4 24814 # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::total 24814 # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.demand_accesses::cpu4 70155 # number of demand (read+write) accesses
system.cpu4.l1c.demand_accesses::total 70155 # number of demand (read+write) accesses
system.cpu4.l1c.overall_accesses::cpu4 70155 # number of overall (read+write) accesses
system.cpu4.l1c.overall_accesses::total 70155 # number of overall (read+write) accesses
system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.809554 # miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_miss_rate::total 0.809554 # miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.955348 # miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_miss_rate::total 0.955348 # miss rate for WriteReq accesses
system.cpu4.l1c.demand_miss_rate::cpu4 0.861122 # miss rate for demand accesses
system.cpu4.l1c.demand_miss_rate::total 0.861122 # miss rate for demand accesses
system.cpu4.l1c.overall_miss_rate::cpu4 0.861122 # miss rate for overall accesses
system.cpu4.l1c.overall_miss_rate::total 0.861122 # miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16286.431128 # average ReadReq miss latency
system.cpu4.l1c.ReadReq_avg_miss_latency::total 16286.431128 # average ReadReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 27763.784063 # average WriteReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::total 27763.784063 # average WriteReq miss latency
system.cpu4.l1c.demand_avg_miss_latency::cpu4 20790.207343 # average overall miss latency
system.cpu4.l1c.demand_avg_miss_latency::total 20790.207343 # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::cpu4 20790.207343 # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::total 20790.207343 # average overall miss latency
system.cpu4.l1c.blocked_cycles::no_mshrs 777995 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu4.l1c.blocked::no_mshrs 66371 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu4.l1c.avg_blocked_cycles::no_mshrs 11.721912 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu4.l1c.fast_writes 0 # number of fast writes performed
system.cpu4.l1c.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu4.l1c.writebacks::writebacks 9776 # number of writebacks
system.cpu4.l1c.writebacks::total 9776 # number of writebacks
system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36706 # number of ReadReq MSHR misses
system.cpu4.l1c.ReadReq_mshr_misses::total 36706 # number of ReadReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23706 # number of WriteReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::total 23706 # number of WriteReq MSHR misses
system.cpu4.l1c.demand_mshr_misses::cpu4 60412 # number of demand (read+write) MSHR misses
system.cpu4.l1c.demand_mshr_misses::total 60412 # number of demand (read+write) MSHR misses
system.cpu4.l1c.overall_mshr_misses::cpu4 60412 # number of overall MSHR misses
system.cpu4.l1c.overall_mshr_misses::total 60412 # number of overall MSHR misses
system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9778 # number of ReadReq MSHR uncacheable
system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9778 # number of ReadReq MSHR uncacheable
system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5370 # number of WriteReq MSHR uncacheable
system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5370 # number of WriteReq MSHR uncacheable
system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15148 # number of overall MSHR uncacheable misses
system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15148 # number of overall MSHR uncacheable misses
system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 540346315 # number of ReadReq MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_miss_latency::total 540346315 # number of ReadReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 621672271 # number of WriteReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::total 621672271 # number of WriteReq MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1162018586 # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::total 1162018586 # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1162018586 # number of overall MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::total 1162018586 # number of overall MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 636494546 # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 636494546 # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 958781259 # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 958781259 # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1595275805 # number of overall MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1595275805 # number of overall MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.809554 # mshr miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.809554 # mshr miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.955348 # mshr miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.955348 # mshr miss rate for WriteReq accesses
system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.861122 # mshr miss rate for demand accesses
system.cpu4.l1c.demand_mshr_miss_rate::total 0.861122 # mshr miss rate for demand accesses
system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.861122 # mshr miss rate for overall accesses
system.cpu4.l1c.overall_mshr_miss_rate::total 0.861122 # mshr miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 14720.926143 # average ReadReq mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 14720.926143 # average ReadReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 26224.258458 # average WriteReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 26224.258458 # average WriteReq mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 19234.896809 # average overall mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::total 19234.896809 # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 19234.896809 # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::total 19234.896809 # average overall mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 65094.553692 # average ReadReq mshr uncacheable latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65094.553692 # average ReadReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 178543.996089 # average WriteReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 178543.996089 # average WriteReq mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 105312.635661 # average overall mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 105312.635661 # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu5.num_reads 99076 # number of read accesses completed
system.cpu5.num_writes 54802 # number of write accesses completed
system.cpu5.l1c.tags.replacements 22210 # number of replacements
system.cpu5.l1c.tags.tagsinuse 392.101349 # Cycle average of tags in use
system.cpu5.l1c.tags.total_refs 13412 # Total number of references to valid blocks.
system.cpu5.l1c.tags.sampled_refs 22600 # Sample count of references to valid blocks.
system.cpu5.l1c.tags.avg_refs 0.593451 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu5.l1c.tags.occ_blocks::cpu5 392.101349 # Average occupied blocks per requestor
system.cpu5.l1c.tags.occ_percent::cpu5 0.765823 # Average percentage of cache occupancy
system.cpu5.l1c.tags.occ_percent::total 0.765823 # Average percentage of cache occupancy
system.cpu5.l1c.tags.occ_task_id_blocks::1024 390 # Occupied blocks per task id
system.cpu5.l1c.tags.age_task_id_blocks_1024::0 382 # Occupied blocks per task id
system.cpu5.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
system.cpu5.l1c.tags.occ_task_id_percent::1024 0.761719 # Percentage of cache occupancy per task id
system.cpu5.l1c.tags.tag_accesses 335763 # Number of tag accesses
system.cpu5.l1c.tags.data_accesses 335763 # Number of data accesses
system.cpu5.l1c.ReadReq_hits::cpu5 8687 # number of ReadReq hits
system.cpu5.l1c.ReadReq_hits::total 8687 # number of ReadReq hits
system.cpu5.l1c.WriteReq_hits::cpu5 1188 # number of WriteReq hits
system.cpu5.l1c.WriteReq_hits::total 1188 # number of WriteReq hits
system.cpu5.l1c.demand_hits::cpu5 9875 # number of demand (read+write) hits
system.cpu5.l1c.demand_hits::total 9875 # number of demand (read+write) hits
system.cpu5.l1c.overall_hits::cpu5 9875 # number of overall hits
system.cpu5.l1c.overall_hits::total 9875 # number of overall hits
system.cpu5.l1c.ReadReq_misses::cpu5 36386 # number of ReadReq misses
system.cpu5.l1c.ReadReq_misses::total 36386 # number of ReadReq misses
system.cpu5.l1c.WriteReq_misses::cpu5 23589 # number of WriteReq misses
system.cpu5.l1c.WriteReq_misses::total 23589 # number of WriteReq misses
system.cpu5.l1c.demand_misses::cpu5 59975 # number of demand (read+write) misses
system.cpu5.l1c.demand_misses::total 59975 # number of demand (read+write) misses
system.cpu5.l1c.overall_misses::cpu5 59975 # number of overall misses
system.cpu5.l1c.overall_misses::total 59975 # number of overall misses
system.cpu5.l1c.ReadReq_miss_latency::cpu5 587220514 # number of ReadReq miss cycles
system.cpu5.l1c.ReadReq_miss_latency::total 587220514 # number of ReadReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::cpu5 653847941 # number of WriteReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::total 653847941 # number of WriteReq miss cycles
system.cpu5.l1c.demand_miss_latency::cpu5 1241068455 # number of demand (read+write) miss cycles
system.cpu5.l1c.demand_miss_latency::total 1241068455 # number of demand (read+write) miss cycles
system.cpu5.l1c.overall_miss_latency::cpu5 1241068455 # number of overall miss cycles
system.cpu5.l1c.overall_miss_latency::total 1241068455 # number of overall miss cycles
system.cpu5.l1c.ReadReq_accesses::cpu5 45073 # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.ReadReq_accesses::total 45073 # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::cpu5 24777 # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::total 24777 # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.demand_accesses::cpu5 69850 # number of demand (read+write) accesses
system.cpu5.l1c.demand_accesses::total 69850 # number of demand (read+write) accesses
system.cpu5.l1c.overall_accesses::cpu5 69850 # number of overall (read+write) accesses
system.cpu5.l1c.overall_accesses::total 69850 # number of overall (read+write) accesses
system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.807268 # miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_miss_rate::total 0.807268 # miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952052 # miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_miss_rate::total 0.952052 # miss rate for WriteReq accesses
system.cpu5.l1c.demand_miss_rate::cpu5 0.858626 # miss rate for demand accesses
system.cpu5.l1c.demand_miss_rate::total 0.858626 # miss rate for demand accesses
system.cpu5.l1c.overall_miss_rate::cpu5 0.858626 # miss rate for overall accesses
system.cpu5.l1c.overall_miss_rate::total 0.858626 # miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16138.638872 # average ReadReq miss latency
system.cpu5.l1c.ReadReq_avg_miss_latency::total 16138.638872 # average ReadReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 27718.340794 # average WriteReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::total 27718.340794 # average WriteReq miss latency
system.cpu5.l1c.demand_avg_miss_latency::cpu5 20693.096373 # average overall miss latency
system.cpu5.l1c.demand_avg_miss_latency::total 20693.096373 # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::cpu5 20693.096373 # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::total 20693.096373 # average overall miss latency
system.cpu5.l1c.blocked_cycles::no_mshrs 773798 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu5.l1c.blocked::no_mshrs 65921 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu5.l1c.avg_blocked_cycles::no_mshrs 11.738262 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu5.l1c.fast_writes 0 # number of fast writes performed
system.cpu5.l1c.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu5.l1c.writebacks::writebacks 9805 # number of writebacks
system.cpu5.l1c.writebacks::total 9805 # number of writebacks
system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36386 # number of ReadReq MSHR misses
system.cpu5.l1c.ReadReq_mshr_misses::total 36386 # number of ReadReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23589 # number of WriteReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::total 23589 # number of WriteReq MSHR misses
system.cpu5.l1c.demand_mshr_misses::cpu5 59975 # number of demand (read+write) MSHR misses
system.cpu5.l1c.demand_mshr_misses::total 59975 # number of demand (read+write) MSHR misses
system.cpu5.l1c.overall_mshr_misses::cpu5 59975 # number of overall MSHR misses
system.cpu5.l1c.overall_mshr_misses::total 59975 # number of overall MSHR misses
system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9927 # number of ReadReq MSHR uncacheable
system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9927 # number of ReadReq MSHR uncacheable
system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5497 # number of WriteReq MSHR uncacheable
system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5497 # number of WriteReq MSHR uncacheable
system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15424 # number of overall MSHR uncacheable misses
system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15424 # number of overall MSHR uncacheable misses
system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 530387712 # number of ReadReq MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_miss_latency::total 530387712 # number of ReadReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 617501507 # number of WriteReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::total 617501507 # number of WriteReq MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1147889219 # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::total 1147889219 # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1147889219 # number of overall MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::total 1147889219 # number of overall MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 644126924 # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 644126924 # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 971277615 # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 971277615 # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1615404539 # number of overall MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1615404539 # number of overall MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.807268 # mshr miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.807268 # mshr miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952052 # mshr miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952052 # mshr miss rate for WriteReq accesses
system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858626 # mshr miss rate for demand accesses
system.cpu5.l1c.demand_mshr_miss_rate::total 0.858626 # mshr miss rate for demand accesses
system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858626 # mshr miss rate for overall accesses
system.cpu5.l1c.overall_mshr_miss_rate::total 0.858626 # mshr miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 14576.697411 # average ReadReq mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 14576.697411 # average ReadReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 26177.519479 # average WriteReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 26177.519479 # average WriteReq mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 19139.461759 # average overall mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::total 19139.461759 # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 19139.461759 # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::total 19139.461759 # average overall mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 64886.362849 # average ReadReq mshr uncacheable latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64886.362849 # average ReadReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 176692.307622 # average WriteReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 176692.307622 # average WriteReq mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 104733.178099 # average overall mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 104733.178099 # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu6.num_reads 100000 # number of read accesses completed
system.cpu6.num_writes 55196 # number of write accesses completed
system.cpu6.l1c.tags.replacements 22166 # number of replacements
system.cpu6.l1c.tags.tagsinuse 390.500017 # Cycle average of tags in use
system.cpu6.l1c.tags.total_refs 13797 # Total number of references to valid blocks.
system.cpu6.l1c.tags.sampled_refs 22571 # Sample count of references to valid blocks.
system.cpu6.l1c.tags.avg_refs 0.611271 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu6.l1c.tags.occ_blocks::cpu6 390.500017 # Average occupied blocks per requestor
system.cpu6.l1c.tags.occ_percent::cpu6 0.762695 # Average percentage of cache occupancy
system.cpu6.l1c.tags.occ_percent::total 0.762695 # Average percentage of cache occupancy
system.cpu6.l1c.tags.occ_task_id_blocks::1024 405 # Occupied blocks per task id
system.cpu6.l1c.tags.age_task_id_blocks_1024::0 400 # Occupied blocks per task id
system.cpu6.l1c.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
system.cpu6.l1c.tags.occ_task_id_percent::1024 0.791016 # Percentage of cache occupancy per task id
system.cpu6.l1c.tags.tag_accesses 338189 # Number of tag accesses
system.cpu6.l1c.tags.data_accesses 338189 # Number of data accesses
system.cpu6.l1c.ReadReq_hits::cpu6 8999 # number of ReadReq hits
system.cpu6.l1c.ReadReq_hits::total 8999 # number of ReadReq hits
system.cpu6.l1c.WriteReq_hits::cpu6 1089 # number of WriteReq hits
system.cpu6.l1c.WriteReq_hits::total 1089 # number of WriteReq hits
system.cpu6.l1c.demand_hits::cpu6 10088 # number of demand (read+write) hits
system.cpu6.l1c.demand_hits::total 10088 # number of demand (read+write) hits
system.cpu6.l1c.overall_hits::cpu6 10088 # number of overall hits
system.cpu6.l1c.overall_hits::total 10088 # number of overall hits
system.cpu6.l1c.ReadReq_misses::cpu6 36489 # number of ReadReq misses
system.cpu6.l1c.ReadReq_misses::total 36489 # number of ReadReq misses
system.cpu6.l1c.WriteReq_misses::cpu6 23831 # number of WriteReq misses
system.cpu6.l1c.WriteReq_misses::total 23831 # number of WriteReq misses
system.cpu6.l1c.demand_misses::cpu6 60320 # number of demand (read+write) misses
system.cpu6.l1c.demand_misses::total 60320 # number of demand (read+write) misses
system.cpu6.l1c.overall_misses::cpu6 60320 # number of overall misses
system.cpu6.l1c.overall_misses::total 60320 # number of overall misses
system.cpu6.l1c.ReadReq_miss_latency::cpu6 591265797 # number of ReadReq miss cycles
system.cpu6.l1c.ReadReq_miss_latency::total 591265797 # number of ReadReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::cpu6 669884291 # number of WriteReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::total 669884291 # number of WriteReq miss cycles
system.cpu6.l1c.demand_miss_latency::cpu6 1261150088 # number of demand (read+write) miss cycles
system.cpu6.l1c.demand_miss_latency::total 1261150088 # number of demand (read+write) miss cycles
system.cpu6.l1c.overall_miss_latency::cpu6 1261150088 # number of overall miss cycles
system.cpu6.l1c.overall_miss_latency::total 1261150088 # number of overall miss cycles
system.cpu6.l1c.ReadReq_accesses::cpu6 45488 # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.ReadReq_accesses::total 45488 # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::cpu6 24920 # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::total 24920 # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.demand_accesses::cpu6 70408 # number of demand (read+write) accesses
system.cpu6.l1c.demand_accesses::total 70408 # number of demand (read+write) accesses
system.cpu6.l1c.overall_accesses::cpu6 70408 # number of overall (read+write) accesses
system.cpu6.l1c.overall_accesses::total 70408 # number of overall (read+write) accesses
system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.802168 # miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_miss_rate::total 0.802168 # miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.956300 # miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_miss_rate::total 0.956300 # miss rate for WriteReq accesses
system.cpu6.l1c.demand_miss_rate::cpu6 0.856721 # miss rate for demand accesses
system.cpu6.l1c.demand_miss_rate::total 0.856721 # miss rate for demand accesses
system.cpu6.l1c.overall_miss_rate::cpu6 0.856721 # miss rate for overall accesses
system.cpu6.l1c.overall_miss_rate::total 0.856721 # miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16203.946313 # average ReadReq miss latency
system.cpu6.l1c.ReadReq_avg_miss_latency::total 16203.946313 # average ReadReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 28109.785196 # average WriteReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::total 28109.785196 # average WriteReq miss latency
system.cpu6.l1c.demand_avg_miss_latency::cpu6 20907.660610 # average overall miss latency
system.cpu6.l1c.demand_avg_miss_latency::total 20907.660610 # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::cpu6 20907.660610 # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::total 20907.660610 # average overall miss latency
system.cpu6.l1c.blocked_cycles::no_mshrs 779089 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu6.l1c.blocked::no_mshrs 66360 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu6.l1c.avg_blocked_cycles::no_mshrs 11.740341 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu6.l1c.fast_writes 0 # number of fast writes performed
system.cpu6.l1c.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu6.l1c.writebacks::writebacks 9642 # number of writebacks
system.cpu6.l1c.writebacks::total 9642 # number of writebacks
system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36489 # number of ReadReq MSHR misses
system.cpu6.l1c.ReadReq_mshr_misses::total 36489 # number of ReadReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23831 # number of WriteReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::total 23831 # number of WriteReq MSHR misses
system.cpu6.l1c.demand_mshr_misses::cpu6 60320 # number of demand (read+write) MSHR misses
system.cpu6.l1c.demand_mshr_misses::total 60320 # number of demand (read+write) MSHR misses
system.cpu6.l1c.overall_mshr_misses::cpu6 60320 # number of overall MSHR misses
system.cpu6.l1c.overall_mshr_misses::total 60320 # number of overall MSHR misses
system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9769 # number of ReadReq MSHR uncacheable
system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9769 # number of ReadReq MSHR uncacheable
system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5428 # number of WriteReq MSHR uncacheable
system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5428 # number of WriteReq MSHR uncacheable
system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15197 # number of overall MSHR uncacheable misses
system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15197 # number of overall MSHR uncacheable misses
system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 534211155 # number of ReadReq MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_miss_latency::total 534211155 # number of ReadReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 633170857 # number of WriteReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::total 633170857 # number of WriteReq MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1167382012 # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::total 1167382012 # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1167382012 # number of overall MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::total 1167382012 # number of overall MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 633249047 # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 633249047 # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 972097686 # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 972097686 # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1605346733 # number of overall MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1605346733 # number of overall MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.802168 # mshr miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.802168 # mshr miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.956300 # mshr miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.956300 # mshr miss rate for WriteReq accesses
system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.856721 # mshr miss rate for demand accesses
system.cpu6.l1c.demand_mshr_miss_rate::total 0.856721 # mshr miss rate for demand accesses
system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.856721 # mshr miss rate for overall accesses
system.cpu6.l1c.overall_mshr_miss_rate::total 0.856721 # mshr miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 14640.334210 # average ReadReq mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 14640.334210 # average ReadReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 26569.210566 # average WriteReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 26569.210566 # average WriteReq mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 19353.150066 # average overall mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::total 19353.150066 # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 19353.150066 # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::total 19353.150066 # average overall mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 64822.299826 # average ReadReq mshr uncacheable latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64822.299826 # average ReadReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 179089.477892 # average WriteReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 179089.477892 # average WriteReq mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 105635.765809 # average overall mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 105635.765809 # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu7.num_reads 99558 # number of read accesses completed
system.cpu7.num_writes 55171 # number of write accesses completed
system.cpu7.l1c.tags.replacements 22301 # number of replacements
system.cpu7.l1c.tags.tagsinuse 392.314330 # Cycle average of tags in use
system.cpu7.l1c.tags.total_refs 13511 # Total number of references to valid blocks.
system.cpu7.l1c.tags.sampled_refs 22696 # Sample count of references to valid blocks.
system.cpu7.l1c.tags.avg_refs 0.595303 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu7.l1c.tags.occ_blocks::cpu7 392.314330 # Average occupied blocks per requestor
system.cpu7.l1c.tags.occ_percent::cpu7 0.766239 # Average percentage of cache occupancy
system.cpu7.l1c.tags.occ_percent::total 0.766239 # Average percentage of cache occupancy
system.cpu7.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id
system.cpu7.l1c.tags.age_task_id_blocks_1024::0 389 # Occupied blocks per task id
system.cpu7.l1c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id
system.cpu7.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id
system.cpu7.l1c.tags.tag_accesses 337937 # Number of tag accesses
system.cpu7.l1c.tags.data_accesses 337937 # Number of data accesses
system.cpu7.l1c.ReadReq_hits::cpu7 8724 # number of ReadReq hits
system.cpu7.l1c.ReadReq_hits::total 8724 # number of ReadReq hits
system.cpu7.l1c.WriteReq_hits::cpu7 1105 # number of WriteReq hits
system.cpu7.l1c.WriteReq_hits::total 1105 # number of WriteReq hits
system.cpu7.l1c.demand_hits::cpu7 9829 # number of demand (read+write) hits
system.cpu7.l1c.demand_hits::total 9829 # number of demand (read+write) hits
system.cpu7.l1c.overall_hits::cpu7 9829 # number of overall hits
system.cpu7.l1c.overall_hits::total 9829 # number of overall hits
system.cpu7.l1c.ReadReq_misses::cpu7 36568 # number of ReadReq misses
system.cpu7.l1c.ReadReq_misses::total 36568 # number of ReadReq misses
system.cpu7.l1c.WriteReq_misses::cpu7 23906 # number of WriteReq misses
system.cpu7.l1c.WriteReq_misses::total 23906 # number of WriteReq misses
system.cpu7.l1c.demand_misses::cpu7 60474 # number of demand (read+write) misses
system.cpu7.l1c.demand_misses::total 60474 # number of demand (read+write) misses
system.cpu7.l1c.overall_misses::cpu7 60474 # number of overall misses
system.cpu7.l1c.overall_misses::total 60474 # number of overall misses
system.cpu7.l1c.ReadReq_miss_latency::cpu7 596090233 # number of ReadReq miss cycles
system.cpu7.l1c.ReadReq_miss_latency::total 596090233 # number of ReadReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::cpu7 664580608 # number of WriteReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::total 664580608 # number of WriteReq miss cycles
system.cpu7.l1c.demand_miss_latency::cpu7 1260670841 # number of demand (read+write) miss cycles
system.cpu7.l1c.demand_miss_latency::total 1260670841 # number of demand (read+write) miss cycles
system.cpu7.l1c.overall_miss_latency::cpu7 1260670841 # number of overall miss cycles
system.cpu7.l1c.overall_miss_latency::total 1260670841 # number of overall miss cycles
system.cpu7.l1c.ReadReq_accesses::cpu7 45292 # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.ReadReq_accesses::total 45292 # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::cpu7 25011 # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::total 25011 # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.demand_accesses::cpu7 70303 # number of demand (read+write) accesses
system.cpu7.l1c.demand_accesses::total 70303 # number of demand (read+write) accesses
system.cpu7.l1c.overall_accesses::cpu7 70303 # number of overall (read+write) accesses
system.cpu7.l1c.overall_accesses::total 70303 # number of overall (read+write) accesses
system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807383 # miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_miss_rate::total 0.807383 # miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955819 # miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_miss_rate::total 0.955819 # miss rate for WriteReq accesses
system.cpu7.l1c.demand_miss_rate::cpu7 0.860191 # miss rate for demand accesses
system.cpu7.l1c.demand_miss_rate::total 0.860191 # miss rate for demand accesses
system.cpu7.l1c.overall_miss_rate::cpu7 0.860191 # miss rate for overall accesses
system.cpu7.l1c.overall_miss_rate::total 0.860191 # miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16300.870515 # average ReadReq miss latency
system.cpu7.l1c.ReadReq_avg_miss_latency::total 16300.870515 # average ReadReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 27799.740986 # average WriteReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::total 27799.740986 # average WriteReq miss latency
system.cpu7.l1c.demand_avg_miss_latency::cpu7 20846.493386 # average overall miss latency
system.cpu7.l1c.demand_avg_miss_latency::total 20846.493386 # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::cpu7 20846.493386 # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::total 20846.493386 # average overall miss latency
system.cpu7.l1c.blocked_cycles::no_mshrs 776345 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu7.l1c.blocked::no_mshrs 66228 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu7.l1c.avg_blocked_cycles::no_mshrs 11.722308 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu7.l1c.fast_writes 0 # number of fast writes performed
system.cpu7.l1c.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu7.l1c.writebacks::writebacks 9814 # number of writebacks
system.cpu7.l1c.writebacks::total 9814 # number of writebacks
system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36568 # number of ReadReq MSHR misses
system.cpu7.l1c.ReadReq_mshr_misses::total 36568 # number of ReadReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23906 # number of WriteReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::total 23906 # number of WriteReq MSHR misses
system.cpu7.l1c.demand_mshr_misses::cpu7 60474 # number of demand (read+write) MSHR misses
system.cpu7.l1c.demand_mshr_misses::total 60474 # number of demand (read+write) MSHR misses
system.cpu7.l1c.overall_mshr_misses::cpu7 60474 # number of overall MSHR misses
system.cpu7.l1c.overall_mshr_misses::total 60474 # number of overall MSHR misses
system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9700 # number of ReadReq MSHR uncacheable
system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9700 # number of ReadReq MSHR uncacheable
system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5336 # number of WriteReq MSHR uncacheable
system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5336 # number of WriteReq MSHR uncacheable
system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15036 # number of overall MSHR uncacheable misses
system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15036 # number of overall MSHR uncacheable misses
system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 538984883 # number of ReadReq MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_miss_latency::total 538984883 # number of ReadReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 627714786 # number of WriteReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::total 627714786 # number of WriteReq MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1166699669 # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::total 1166699669 # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1166699669 # number of overall MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::total 1166699669 # number of overall MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 629180127 # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 629180127 # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 945700289 # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 945700289 # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1574880416 # number of overall MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1574880416 # number of overall MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807383 # mshr miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807383 # mshr miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.955819 # mshr miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.955819 # mshr miss rate for WriteReq accesses
system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.860191 # mshr miss rate for demand accesses
system.cpu7.l1c.demand_mshr_miss_rate::total 0.860191 # mshr miss rate for demand accesses
system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.860191 # mshr miss rate for overall accesses
system.cpu7.l1c.overall_mshr_miss_rate::total 0.860191 # mshr miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 14739.249699 # average ReadReq mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 14739.249699 # average ReadReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 26257.625115 # average WriteReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 26257.625115 # average WriteReq mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 19292.583077 # average overall mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::total 19292.583077 # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 19292.583077 # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::total 19292.583077 # average overall mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 64863.930619 # average ReadReq mshr uncacheable latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 64863.930619 # average ReadReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 177230.189093 # average WriteReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 177230.189093 # average WriteReq mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 104740.650173 # average overall mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 104740.650173 # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.l2c.tags.replacements 14031 # number of replacements
system.l2c.tags.tagsinuse 784.967814 # Cycle average of tags in use
system.l2c.tags.total_refs 150152 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 14812 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 10.137186 # Average number of references to valid blocks.
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.l2c.tags.occ_blocks::writebacks 723.923615 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0 7.649200 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1 8.016952 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2 7.636701 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3 7.493514 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu4 7.626072 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu5 7.131481 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu6 7.354188 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu7 8.136089 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.706957 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0 0.007470 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1 0.007829 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2 0.007458 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3 0.007318 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu4 0.007447 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu5 0.006964 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu6 0.007182 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu7 0.007945 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.766570 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024 781 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 686 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.762695 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 1978435 # Number of tag accesses
system.l2c.tags.data_accesses 1978435 # Number of data accesses
system.l2c.ReadReq_hits::cpu0 10713 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1 10607 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2 10697 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3 10702 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu4 11123 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu5 10597 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu6 10776 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu7 10709 # number of ReadReq hits
system.l2c.ReadReq_hits::total 85924 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 76544 # number of Writeback hits
system.l2c.Writeback_hits::total 76544 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0 272 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1 268 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2 299 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3 302 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu4 259 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu5 274 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu6 287 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu7 307 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 2268 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0 1803 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1 1734 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2 1772 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu3 1671 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu4 1762 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu5 1808 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu6 1767 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu7 1864 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 14181 # number of ReadExReq hits
system.l2c.demand_hits::cpu0 12516 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1 12341 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2 12469 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3 12373 # number of demand (read+write) hits
system.l2c.demand_hits::cpu4 12885 # number of demand (read+write) hits
system.l2c.demand_hits::cpu5 12405 # number of demand (read+write) hits
system.l2c.demand_hits::cpu6 12543 # number of demand (read+write) hits
system.l2c.demand_hits::cpu7 12573 # number of demand (read+write) hits
system.l2c.demand_hits::total 100105 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0 12516 # number of overall hits
system.l2c.overall_hits::cpu1 12341 # number of overall hits
system.l2c.overall_hits::cpu2 12469 # number of overall hits
system.l2c.overall_hits::cpu3 12373 # number of overall hits
system.l2c.overall_hits::cpu4 12885 # number of overall hits
system.l2c.overall_hits::cpu5 12405 # number of overall hits
system.l2c.overall_hits::cpu6 12543 # number of overall hits
system.l2c.overall_hits::cpu7 12573 # number of overall hits
system.l2c.overall_hits::total 100105 # number of overall hits
system.l2c.ReadReq_misses::cpu0 745 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1 785 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2 742 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3 727 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu4 760 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu5 712 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu6 735 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu7 780 # number of ReadReq misses
system.l2c.ReadReq_misses::total 5986 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0 1959 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1 2034 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2 2073 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3 2095 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu4 2075 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu5 1984 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu6 2104 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu7 2050 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 16374 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0 4569 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1 4626 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2 4511 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3 4582 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu4 4471 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu5 4493 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu6 4628 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu7 4552 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 36432 # number of ReadExReq misses
system.l2c.demand_misses::cpu0 5314 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1 5411 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2 5253 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3 5309 # number of demand (read+write) misses
system.l2c.demand_misses::cpu4 5231 # number of demand (read+write) misses
system.l2c.demand_misses::cpu5 5205 # number of demand (read+write) misses
system.l2c.demand_misses::cpu6 5363 # number of demand (read+write) misses
system.l2c.demand_misses::cpu7 5332 # number of demand (read+write) misses
system.l2c.demand_misses::total 42418 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0 5314 # number of overall misses
system.l2c.overall_misses::cpu1 5411 # number of overall misses
system.l2c.overall_misses::cpu2 5253 # number of overall misses
system.l2c.overall_misses::cpu3 5309 # number of overall misses
system.l2c.overall_misses::cpu4 5231 # number of overall misses
system.l2c.overall_misses::cpu5 5205 # number of overall misses
system.l2c.overall_misses::cpu6 5363 # number of overall misses
system.l2c.overall_misses::cpu7 5332 # number of overall misses
system.l2c.overall_misses::total 42418 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0 46187916 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1 48036419 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2 45900428 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3 44726930 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu4 46758924 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu5 44218925 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu6 45379928 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu7 48529420 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 369738890 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0 57866497 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1 60355991 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2 61207994 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu3 63805822 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu4 62183492 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu5 61767496 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu6 63498496 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu7 63160496 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 493846284 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0 251689442 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1 254959951 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2 248273936 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3 252714443 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu4 246321934 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu5 247674443 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu6 255400930 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu7 250363448 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 2007398527 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0 297877358 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1 302996370 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2 294174364 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3 297441373 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu4 293080858 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu5 291893368 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu6 300780858 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu7 298892868 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 2377137417 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0 297877358 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1 302996370 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2 294174364 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3 297441373 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu4 293080858 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu5 291893368 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu6 300780858 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu7 298892868 # number of overall miss cycles
system.l2c.overall_miss_latency::total 2377137417 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0 11458 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1 11392 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2 11439 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3 11429 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu4 11883 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu5 11309 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu6 11511 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu7 11489 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 91910 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 76544 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 76544 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0 2231 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1 2302 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2 2372 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3 2397 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu4 2334 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu5 2258 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu6 2391 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu7 2357 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 18642 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0 6372 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1 6360 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2 6283 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3 6253 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu4 6233 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu5 6301 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu6 6395 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu7 6416 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 50613 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0 17830 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1 17752 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2 17722 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3 17682 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu4 18116 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu5 17610 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu6 17906 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu7 17905 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 142523 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0 17830 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1 17752 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2 17722 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3 17682 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu4 18116 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu5 17610 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu6 17906 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu7 17905 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 142523 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0 0.065020 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1 0.068908 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2 0.064866 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3 0.063610 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu4 0.063957 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu5 0.062959 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu6 0.063852 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu7 0.067891 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.065129 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0 0.878082 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1 0.883579 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2 0.873946 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3 0.874009 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu4 0.889032 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu5 0.878654 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu6 0.879967 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu7 0.869750 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.878339 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0 0.717043 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1 0.727358 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2 0.717969 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3 0.732768 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu4 0.717311 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu5 0.713061 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu6 0.723690 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu7 0.709476 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.719815 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0 0.298037 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1 0.304811 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2 0.296411 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3 0.300249 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu4 0.288750 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu5 0.295571 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu6 0.299509 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu7 0.297794 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.297622 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0 0.298037 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1 0.304811 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2 0.296411 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3 0.300249 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu4 0.288750 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu5 0.295571 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu6 0.299509 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu7 0.297794 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.297622 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0 61997.202685 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1 61192.890446 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2 61860.415094 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3 61522.599725 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu4 61524.900000 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu5 62105.231742 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu6 61741.398639 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu7 62217.205128 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 61767.271968 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0 29538.793772 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1 29673.545231 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2 29526.287506 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu3 30456.239618 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu4 29967.947952 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu5 31132.810484 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu6 30179.893536 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu7 30809.998049 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 30160.393551 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0 55086.330050 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1 55114.559230 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2 55037.449789 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3 55153.741379 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu4 55093.252964 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu5 55124.514356 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu6 55186.026361 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu7 55000.757469 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 55099.871734 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0 56055.204742 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1 55996.372205 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2 56001.211498 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3 56025.875494 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu4 56027.692219 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu5 56079.417483 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu6 56084.441171 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu7 56056.426857 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 56040.770828 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0 56055.204742 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1 55996.372205 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2 56001.211498 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3 56025.875494 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu4 56027.692219 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu5 56079.417483 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu6 56084.441171 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu7 56056.426857 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 56040.770828 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 18299 # number of cycles access was blocked
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.l2c.blocked::no_mshrs 3476 # number of cycles access was blocked
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.l2c.avg_blocked_cycles::no_mshrs 5.264384 # average number of cycles each access was blocked
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.l2c.writebacks::writebacks 6720 # number of writebacks
system.l2c.writebacks::total 6720 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0 7 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1 9 # number of ReadReq MSHR hits
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.l2c.ReadReq_mshr_hits::cpu2 8 # number of ReadReq MSHR hits
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.l2c.ReadReq_mshr_hits::cpu3 3 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu4 15 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu5 6 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu6 4 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu7 6 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.l2c.UpgradeReq_mshr_hits::cpu4 1 # number of UpgradeReq MSHR hits
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.l2c.UpgradeReq_mshr_hits::cpu6 3 # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::total 4 # number of UpgradeReq MSHR hits
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.l2c.ReadExReq_mshr_hits::cpu0 4 # number of ReadExReq MSHR hits
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.l2c.ReadExReq_mshr_hits::cpu1 4 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu2 8 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu3 2 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu4 4 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu5 5 # number of ReadExReq MSHR hits
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.l2c.ReadExReq_mshr_hits::cpu6 4 # number of ReadExReq MSHR hits
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.l2c.ReadExReq_mshr_hits::cpu7 4 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::total 35 # number of ReadExReq MSHR hits
system.l2c.demand_mshr_hits::cpu0 11 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1 13 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2 16 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3 5 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu4 19 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu5 11 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu6 8 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu7 10 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 93 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0 11 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1 13 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2 16 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3 5 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu4 19 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu5 11 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu6 8 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu7 10 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 93 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0 738 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1 776 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2 734 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3 724 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu4 745 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu5 706 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu6 731 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu7 774 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 5928 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0 1959 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1 2034 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2 2073 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3 2095 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu4 2074 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu5 1984 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu6 2101 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu7 2050 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 16370 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0 4565 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1 4622 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2 4503 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3 4580 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu4 4467 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu5 4488 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu6 4624 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu7 4548 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 36397 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0 5303 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1 5398 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2 5237 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3 5304 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu4 5212 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu5 5194 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu6 5355 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu7 5322 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 42325 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0 5303 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1 5398 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2 5237 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3 5304 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu4 5212 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu5 5194 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu6 5355 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu7 5322 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 42325 # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0 9834 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1 9869 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu2 9727 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu3 9854 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu4 9778 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu5 9927 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu6 9769 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu7 9700 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total 78458 # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0 5517 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1 5460 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu2 5550 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu3 5367 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu4 5370 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu5 5497 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu6 5427 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu7 5336 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total 43524 # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0 15351 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1 15329 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu2 15277 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu3 15221 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu4 15148 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu5 15424 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu6 15196 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu7 15036 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total 121982 # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0 37081908 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1 38421892 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2 36752422 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3 35943926 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu4 37213921 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu5 35460411 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu6 36445418 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu7 38946899 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 296266797 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0 82978964 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1 86239947 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2 87750966 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3 88854787 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu4 87819107 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu5 83999460 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu6 88854959 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu7 87064968 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 693563158 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0 196462368 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1 199050885 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2 193595340 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3 197409379 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu4 192312836 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu5 193341369 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu6 199367330 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu7 195358866 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 1566898373 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0 233544276 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1 237472777 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2 230347762 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3 233353305 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu4 229526757 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu5 228801780 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu6 235812748 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu7 234305765 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 1863165170 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0 233544276 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1 237472777 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2 230347762 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3 233353305 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu4 229526757 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu5 228801780 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu6 235812748 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu7 234305765 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 1863165170 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 419590422 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 420411799 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 414525738 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 420114597 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 417359247 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 423042782 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 416304244 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 412865244 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 3344214073 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 244799897 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 243732417 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 247505386 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 237594430 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 238425396 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 244815873 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 242422406 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 237975886 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 1937271691 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0 664390319 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1 664144216 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2 662031124 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu3 657709027 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu4 655784643 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu5 667858655 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu6 658726650 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu7 650841130 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 5281485764 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0 0.064409 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1 0.068118 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2 0.064166 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3 0.063348 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu4 0.062695 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu5 0.062428 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu6 0.063504 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu7 0.067369 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.064498 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.878082 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.883579 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.873946 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.874009 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.888603 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.878654 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.878712 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.869750 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.878125 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.716416 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.726730 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.716696 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.732448 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.716669 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.712268 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.723065 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.708853 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.719124 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0 0.297420 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1 0.304078 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2 0.295508 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3 0.299966 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu4 0.287701 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu5 0.294946 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu6 0.299062 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu7 0.297235 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.296970 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0 0.297420 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1 0.304078 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2 0.295508 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3 0.299966 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu4 0.287701 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu5 0.294946 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu6 0.299062 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu7 0.297235 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.296970 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 50246.487805 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 49512.747423 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 50071.419619 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49646.306630 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 49951.571812 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 50227.211048 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49856.932969 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 50318.990956 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 49977.529858 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 42357.817254 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 42399.187316 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 42330.422576 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 42412.786158 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 42342.867406 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 42338.437500 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 42291.746311 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 42470.716098 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42367.938790 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 43036.663308 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 43065.963868 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 42992.524983 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 43102.484498 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 43051.899709 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 43079.627674 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 43115.772059 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 42954.895778 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 43050.206693 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0 44040.029417 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1 43992.733790 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2 43984.678633 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3 43995.721154 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu4 44038.134497 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu5 44051.170581 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu6 44035.994024 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu7 44025.885945 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 44020.441110 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0 44040.029417 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1 43992.733790 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2 43984.678633 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3 43995.721154 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu4 44038.134497 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu5 44051.170581 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu6 44035.994024 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu7 44025.885945 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 44020.441110 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 42667.319707 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 42599.229811 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 42615.990336 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 42633.914857 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 42683.498364 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 42615.370404 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 42614.826901 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 42563.427216 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 42624.258495 # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 44371.922603 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 44639.636813 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 44595.565045 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 44269.504379 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 44399.515084 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 44536.269420 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 44669.689700 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 44598.179535 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 44510.423927 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 43279.937398 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 43325.997521 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 43335.152451 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 43210.631824 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 43291.830143 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 43299.964665 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 43348.687155 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 43285.523410 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 43297.255038 # average overall mshr uncacheable latency
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.membus.trans_dist::ReadReq 84372 # Transaction distribution
system.membus.trans_dist::ReadResp 84365 # Transaction distribution
system.membus.trans_dist::WriteReq 43521 # Transaction distribution
system.membus.trans_dist::WriteResp 43519 # Transaction distribution
system.membus.trans_dist::Writeback 6720 # Transaction distribution
system.membus.trans_dist::UpgradeReq 60428 # Transaction distribution
system.membus.trans_dist::UpgradeResp 49463 # Transaction distribution
system.membus.trans_dist::ReadExReq 49409 # Transaction distribution
system.membus.trans_dist::ReadExResp 3325 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 425122 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 425122 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1143411 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 1143411 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 57048 # Total snoops (count)
system.membus.snoop_fanout::samples 253034 # Request fanout histogram
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.membus.snoop_fanout::0 253034 100.00% 100.00% # Request fanout histogram
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.membus.snoop_fanout::total 253034 # Request fanout histogram
system.membus.reqLayer0.occupancy 288296633 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 60.9 # Layer utilization (%)
system.membus.respLayer0.occupancy 308136269 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 65.1 # Layer utilization (%)
system.toL2Bus.trans_dist::ReadReq 369990 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 369967 # Transaction distribution
system.toL2Bus.trans_dist::ReadRespWithInvalidate 6 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 43524 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 43518 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 76544 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 29606 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 29605 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 161002 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 160999 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120638 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120231 # Packet count per connected master and slave (bytes)
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120590 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120464 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120699 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120288 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120457 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120419 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 963786 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1770551 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1757664 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1763883 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1765044 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1785450 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1756799 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1766043 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1776312 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 14141746 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 320975 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 687560 # Request fanout histogram
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.toL2Bus.snoop_fanout::7 687560 100.00% 100.00% # Request fanout histogram
stats: Bump the MemTest regression stats Reflect changes in the tester behaviour.
2015-02-11 16:23:31 +01:00
system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.toL2Bus.snoop_fanout::total 687560 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 445191055 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 94.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 101323906 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer0.utilization 21.4 # Layer utilization (%)
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.toL2Bus.respLayer1.occupancy 101013875 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 21.3 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 101243878 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer2.utilization 21.4 # Layer utilization (%)
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.toL2Bus.respLayer3.occupancy 101066643 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 21.3 # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy 101367492 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer4.utilization 21.4 # Layer utilization (%)
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.toL2Bus.respLayer5.occupancy 100955896 # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization 21.3 # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy 101182766 # Layer occupancy (ticks)
tests: Update stats for cache block alignment
2015-03-27 09:55:57 +01:00
system.toL2Bus.respLayer6.utilization 21.4 # Layer utilization (%)
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.toL2Bus.respLayer7.occupancy 101290842 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer7.utilization 21.4 # Layer utilization (%)
Add short memtest run to quick regressions. Caveats: - Even though memtest is ISA-independent, it will only run for the Alpha builds, since there's no way to specify ISA-independent reference files and I didn't want to commit 3 copies since I'm not sure we want to run it for all the different ISAs anyway. - Reference outputs were generated on my laptop, so performance numbers will be low compared to zizzer. --HG-- extra : convert_revision : 210fe4abecc19fbab0b15402c6cb4863650bab66
2007-02-07 06:16:33 +01:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink