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gem5/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt

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cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
---------- Begin Simulation Statistics ----------
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
sim_seconds 0.413311 # Number of seconds simulated
sim_ticks 413311471500 # Number of ticks simulated
final_tick 413311471500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
host_inst_rate 320750 # Simulator instruction rate (inst/s)
host_op_rate 320750 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 216651718 # Simulator tick rate (ticks/s)
host_mem_usage 298932 # Number of bytes of host memory used
host_seconds 1907.72 # Real time elapsed on the host
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
sim_insts 611901617 # Number of instructions simulated
sim_ops 611901617 # Number of ops (including micro ops) simulated
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.voltage_domain.voltage 1 # Voltage in Volts
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
system.clk_domain.clock 1000 # Clock period in ticks
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.physmem.bytes_read::cpu.inst 170944 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24150272 # Number of bytes read from this memory
system.physmem.bytes_read::total 24321216 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 170944 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 170944 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 18724096 # Number of bytes written to this memory
system.physmem.bytes_written::total 18724096 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 2671 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 377348 # Number of read requests responded to by this memory
system.physmem.num_reads::total 380019 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 292564 # Number of write requests responded to by this memory
system.physmem.num_writes::total 292564 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 413596 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 58431168 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 58844764 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 413596 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 413596 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 45302628 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 45302628 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 45302628 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 413596 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 58431168 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 104147392 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 380019 # Number of read requests accepted
system.physmem.writeReqs 292564 # Number of write requests accepted
system.physmem.readBursts 380019 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 292564 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 24298816 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 22400 # Total number of bytes read from write queue
system.physmem.bytesWritten 18722432 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 24321216 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 18724096 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 350 # Number of DRAM read bursts serviced by the write queue
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.physmem.perBankRdBursts::0 23743 # Per bank write bursts
system.physmem.perBankRdBursts::1 23222 # Per bank write bursts
system.physmem.perBankRdBursts::2 23516 # Per bank write bursts
system.physmem.perBankRdBursts::3 24520 # Per bank write bursts
system.physmem.perBankRdBursts::4 25462 # Per bank write bursts
system.physmem.perBankRdBursts::5 23584 # Per bank write bursts
system.physmem.perBankRdBursts::6 23675 # Per bank write bursts
system.physmem.perBankRdBursts::7 23980 # Per bank write bursts
system.physmem.perBankRdBursts::8 23177 # Per bank write bursts
system.physmem.perBankRdBursts::9 23949 # Per bank write bursts
system.physmem.perBankRdBursts::10 24669 # Per bank write bursts
system.physmem.perBankRdBursts::11 22747 # Per bank write bursts
system.physmem.perBankRdBursts::12 23729 # Per bank write bursts
system.physmem.perBankRdBursts::13 24425 # Per bank write bursts
system.physmem.perBankRdBursts::14 22797 # Per bank write bursts
system.physmem.perBankRdBursts::15 22474 # Per bank write bursts
system.physmem.perBankWrBursts::0 17756 # Per bank write bursts
system.physmem.perBankWrBursts::1 17433 # Per bank write bursts
system.physmem.perBankWrBursts::2 17901 # Per bank write bursts
system.physmem.perBankWrBursts::3 18770 # Per bank write bursts
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.perBankWrBursts::4 19442 # Per bank write bursts
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.physmem.perBankWrBursts::5 18538 # Per bank write bursts
system.physmem.perBankWrBursts::6 18680 # Per bank write bursts
system.physmem.perBankWrBursts::7 18573 # Per bank write bursts
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.perBankWrBursts::8 18350 # Per bank write bursts
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.physmem.perBankWrBursts::9 18834 # Per bank write bursts
system.physmem.perBankWrBursts::10 19126 # Per bank write bursts
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.perBankWrBursts::11 17963 # Per bank write bursts
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.physmem.perBankWrBursts::12 18227 # Per bank write bursts
system.physmem.perBankWrBursts::13 18693 # Per bank write bursts
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.perBankWrBursts::14 17147 # Per bank write bursts
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.physmem.perBankWrBursts::15 17105 # Per bank write bursts
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.physmem.totGap 413311383000 # Total gap between requests
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.physmem.readPktSize::6 380019 # Read request sizes (log2)
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.physmem.writePktSize::6 292564 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 378271 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1381 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.physmem.wrQLenPdf::15 6908 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 7455 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 16940 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 17341 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 17386 # What write queue length does an incoming req see
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.wrQLenPdf::20 17435 # What write queue length does an incoming req see
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.physmem.wrQLenPdf::21 17416 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 17404 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 17387 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 17416 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 17424 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 17379 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 17497 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 17426 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 17431 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 17582 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 17331 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 17277 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 36 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 17 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 1 # What write queue length does an incoming req see
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.physmem.bytesPerActivate::samples 142426 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 302.052266 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 179.083619 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 324.600685 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 51194 35.94% 35.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 38668 27.15% 63.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 13205 9.27% 72.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 8199 5.76% 78.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 5653 3.97% 82.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 3753 2.64% 84.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 3030 2.13% 86.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 2604 1.83% 88.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 16120 11.32% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 142426 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 17258 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 21.998378 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 228.944233 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 17248 99.94% 99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071 4 0.02% 99.99% # Reads before turning the bus around for writes
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.physmem.rdPerTurnAround::total 17258 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 17258 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.950863 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.879940 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 2.817078 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 17053 98.81% 98.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 148 0.86% 99.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 32 0.19% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 8 0.05% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 6 0.03% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 1 0.01% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 1 0.01% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 2 0.01% 99.96% # Writes before turning the bus around for reads
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.wrPerTurnAround::60-63 1 0.01% 99.97% # Writes before turning the bus around for reads
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.physmem.wrPerTurnAround::64-67 1 0.01% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 1 0.01% 99.98% # Writes before turning the bus around for reads
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.wrPerTurnAround::88-91 1 0.01% 99.98% # Writes before turning the bus around for reads
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.physmem.wrPerTurnAround::100-103 1 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::212-215 1 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-243 1 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 17258 # Writes before turning the bus around for reads
system.physmem.totQLat 4042656250 # Total ticks spent queuing
system.physmem.totMemAccLat 11161450000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 1898345000 # Total ticks spent in databus transfers
system.physmem.avgQLat 10647.84 # Average queueing delay per DRAM burst
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.physmem.avgMemAccLat 29397.84 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 58.79 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 45.30 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 58.84 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 45.30 # Average system write bandwidth in MiByte/s
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.busUtil 0.81 # Data bus utilization in percentage
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.busUtilWrite 0.35 # Data bus utilization in percentage for writes
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.physmem.avgWrQLen 20.55 # Average write queue length when enqueuing
system.physmem.readRowHits 314442 # Number of row buffer hits during reads
system.physmem.writeRowHits 215335 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.82 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 73.60 # Row buffer hit rate for writes
system.physmem.avgGap 614513.57 # Average gap between requests
system.physmem.pageHitRate 78.81 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 549347400 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 299743125 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1495252200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 953162640 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 26995381920 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 62649847125 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 193029983250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 285972717660 # Total energy per rank (pJ)
system.physmem_0.averagePower 691.908567 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 320566103500 # Time in different power states
system.physmem_0.memoryStateTime::REF 13801320000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.physmem_0.memoryStateTime::ACT 78943046000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.physmem_1.actEnergy 527378040 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 287755875 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1466010000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 942483600 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 26995381920 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 59502215925 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 195791063250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 285512288610 # Total energy per rank (pJ)
system.physmem_1.averagePower 690.794563 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 325183887500 # Time in different power states
system.physmem_1.memoryStateTime::REF 13801320000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.physmem_1.memoryStateTime::ACT 74324788750 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.branchPred.lookups 124207419 # Number of BP lookups
system.cpu.branchPred.condPredicted 87899229 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 6403012 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 71682632 # Number of BTB lookups
system.cpu.branchPred.BTBHits 67406446 # Number of BTB hits
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.branchPred.BTBHitPct 94.034558 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 15055625 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 1126618 # Number of incorrect RAS predictions.
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.dtb.read_hits 149439695 # DTB read hits
system.cpu.dtb.read_misses 564071 # DTB read misses
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.dtb.read_acv 0 # DTB read access violations
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.dtb.read_accesses 150003766 # DTB read accesses
system.cpu.dtb.write_hits 57327469 # DTB write hits
system.cpu.dtb.write_misses 66798 # DTB write misses
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.dtb.write_acv 0 # DTB write access violations
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.dtb.write_accesses 57394267 # DTB write accesses
system.cpu.dtb.data_hits 206767164 # DTB hits
system.cpu.dtb.data_misses 630869 # DTB misses
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.dtb.data_acv 0 # DTB access violations
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.dtb.data_accesses 207398033 # DTB accesses
system.cpu.itb.fetch_hits 226566802 # ITB hits
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.itb.fetch_misses 48 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.itb.fetch_accesses 226566850 # ITB accesses
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 485 # Number of system calls
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.numCycles 826622943 # number of cpu cycles simulated
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 611901617 # Number of instructions committed
system.cpu.committedOps 611901617 # Number of ops (including micro ops) committed
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.discardedOps 13262321 # Number of ops (including micro ops) which were discarded before commit
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.cpi 1.350908 # CPI: cycles per instruction
system.cpu.ipc 0.740243 # IPC: instructions per cycle
system.cpu.tickCycles 740977624 # Number of cycles that the object actually ticked
system.cpu.idleCycles 85645319 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 2535493 # number of replacements
system.cpu.dcache.tags.tagsinuse 4087.640549 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 202664153 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2539589 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 79.801949 # Average number of references to valid blocks.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.warmup_cycle 1642835250 # Cycle when the warmup percentage was hit.
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.dcache.tags.occ_blocks::cpu.data 4087.640549 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.997959 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.997959 # Average percentage of cache occupancy
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::2 828 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 3146 # Occupied blocks per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.dcache.tags.tag_accesses 414772189 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 414772189 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 146997943 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 146997943 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 55666210 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 55666210 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 202664153 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 202664153 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 202664153 # number of overall hits
system.cpu.dcache.overall_hits::total 202664153 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1908323 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1908323 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1543824 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1543824 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 3452147 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3452147 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3452147 # number of overall misses
system.cpu.dcache.overall_misses::total 3452147 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 37798959500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 37798959500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 48016494500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 48016494500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 85815454000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 85815454000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 85815454000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 85815454000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 148906266 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 148906266 # number of ReadReq accesses(hits+misses)
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 57210034 # number of WriteReq accesses(hits+misses)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.WriteReq_accesses::total 57210034 # number of WriteReq accesses(hits+misses)
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.dcache.demand_accesses::cpu.data 206116300 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 206116300 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 206116300 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 206116300 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012816 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.012816 # miss rate for ReadReq accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026985 # miss rate for WriteReq accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.WriteReq_miss_rate::total 0.026985 # miss rate for WriteReq accesses
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.016749 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.016749 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.016749 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.016749 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19807.422276 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 19807.422276 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31102.311209 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 31102.311209 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 24858.574678 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 24858.574678 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 24858.574678 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 24858.574678 # average overall miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.dcache.writebacks::writebacks 2340079 # number of writebacks
system.cpu.dcache.writebacks::total 2340079 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 143534 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 143534 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769024 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 769024 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 912558 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 912558 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 912558 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 912558 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764789 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1764789 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 774800 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 774800 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2539589 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2539589 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2539589 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2539589 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32332751000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 32332751000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23008045000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 23008045000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 55340796000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 55340796000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 55340796000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 55340796000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.011852 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.011852 # mshr miss rate for ReadReq accesses
stats: changes due to recent changesets.
2015-01-04 20:02:12 +01:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.013543 # mshr miss rate for WriteReq accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.013543 # mshr miss rate for WriteReq accesses
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012321 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.012321 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012321 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.012321 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18321.029313 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18321.029313 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29695.463345 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29695.463345 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21791.241024 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 21791.241024 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21791.241024 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 21791.241024 # average overall mshr miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.icache.tags.replacements 3154 # number of replacements
system.cpu.icache.tags.tagsinuse 1117.871500 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 226561819 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 4983 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 45466.951435 # Average number of references to valid blocks.
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.icache.tags.occ_blocks::cpu.inst 1117.871500 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.545836 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.545836 # Average percentage of cache occupancy
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::3 77 # Occupied blocks per task id
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::4 1588 # Occupied blocks per task id
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.icache.tags.tag_accesses 453138587 # Number of tag accesses
system.cpu.icache.tags.data_accesses 453138587 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 226561819 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 226561819 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 226561819 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 226561819 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 226561819 # number of overall hits
system.cpu.icache.overall_hits::total 226561819 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 4983 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 4983 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 4983 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 4983 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 4983 # number of overall misses
system.cpu.icache.overall_misses::total 4983 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 247079500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 247079500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 247079500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 247079500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 247079500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 247079500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 226566802 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 226566802 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 226566802 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 226566802 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 226566802 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 226566802 # number of overall (read+write) accesses
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49584.487257 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 49584.487257 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 49584.487257 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 49584.487257 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 49584.487257 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 49584.487257 # average overall miss latency
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4983 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 4983 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 4983 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 4983 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 4983 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 4983 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 238501000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 238501000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 238501000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 238501000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 238501000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 238501000 # number of overall MSHR miss cycles
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47862.933976 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47862.933976 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47862.933976 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 47862.933976 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47862.933976 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 47862.933976 # average overall mshr miss latency
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.l2cache.tags.replacements 347308 # number of replacements
system.cpu.l2cache.tags.tagsinuse 29502.914302 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3711163 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 379732 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 9.773111 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 189708414000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 21415.422329 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 178.366863 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 7909.125111 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.653547 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005443 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.241367 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.900357 # Average percentage of cache occupancy
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32424 # Occupied blocks per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 76 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13173 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18829 # Occupied blocks per task id
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.989502 # Percentage of cache occupancy per task id
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.l2cache.tags.tag_accesses 40235078 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 40235078 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 2312 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1590725 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1593037 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 2340079 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 2340079 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 571516 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 571516 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2312 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 2162241 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2164553 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 2312 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 2162241 # number of overall hits
system.cpu.l2cache.overall_hits::total 2164553 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 2671 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 170726 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 173397 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 206622 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 206622 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 2671 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 377348 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 380019 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 2671 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 377348 # number of overall misses
system.cpu.l2cache.overall_misses::total 380019 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 209227500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 13799563750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 14008791250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16275084500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 16275084500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 209227500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 30074648250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 30283875750 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 209227500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 30074648250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 30283875750 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 4983 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1761451 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1766434 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 2340079 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 2340079 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 778138 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 778138 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 4983 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2539589 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2544572 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 4983 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2539589 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2544572 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.536022 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.096924 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.098162 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.265534 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.265534 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.536022 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.148586 # miss rate for demand accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.demand_miss_rate::total 0.149345 # miss rate for demand accesses
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.536022 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.148586 # miss rate for overall accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.overall_miss_rate::total 0.149345 # miss rate for overall accesses
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78333.021340 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80828.718239 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 80790.274630 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78767.432800 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78767.432800 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78333.021340 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79700.033523 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 79690.425347 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78333.021340 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79700.033523 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 79690.425347 # average overall miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.l2cache.writebacks::writebacks 292564 # number of writebacks
system.cpu.l2cache.writebacks::total 292564 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2671 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 170726 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 173397 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206622 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 206622 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2671 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 377348 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 380019 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2671 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 377348 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 380019 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 175804500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 11663055250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11838859750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13690980000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13690980000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 175804500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25354035250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 25529839750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 175804500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25354035250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 25529839750 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.536022 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.096924 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.098162 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265534 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265534 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.536022 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148586 # mshr miss rate for demand accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::total 0.149345 # mshr miss rate for demand accesses
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.536022 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148586 # mshr miss rate for overall accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::total 0.149345 # mshr miss rate for overall accesses
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65819.730438 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68314.464405 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68276.035629 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66260.998345 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66260.998345 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65819.730438 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67190.061296 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67180.429794 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65819.730438 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67190.061296 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67180.429794 # average overall mshr miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.toL2Bus.trans_dist::ReadReq 1766434 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 1766434 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 2340079 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 778138 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 778138 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9966 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7419257 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 7429223 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 318912 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312298752 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 312617664 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.toL2Bus.snoop_fanout::samples 4884651 # Request fanout histogram
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.toL2Bus.snoop_fanout::1 4884651 100.00% 100.00% # Request fanout histogram
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.toL2Bus.snoop_fanout::total 4884651 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 4782404500 # Layer occupancy (ticks)
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 8026500 # Layer occupancy (ticks)
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 3891673000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.membus.trans_dist::ReadReq 173397 # Transaction distribution
system.membus.trans_dist::ReadResp 173397 # Transaction distribution
system.membus.trans_dist::Writeback 292564 # Transaction distribution
system.membus.trans_dist::ReadExReq 206622 # Transaction distribution
system.membus.trans_dist::ReadExResp 206622 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1052602 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1052602 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43045312 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 43045312 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoops 0 # Total snoops (count)
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.membus.snoop_fanout::samples 672583 # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.membus.snoop_fanout::0 672583 100.00% 100.00% # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.membus.snoop_fanout::total 672583 # Request fanout histogram
system.membus.reqLayer0.occupancy 1984973000 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
stats: Update MinorCPU regressions after accounting fix
2015-05-26 09:21:39 +02:00
system.membus.respLayer1.occupancy 2011061250 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
---------- End Simulation Statistics ----------
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