2014-07-23 23:09:05 +02:00
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---------- Begin Simulation Statistics ----------
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2014-09-20 23:18:53 +02:00
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sim_seconds 0.409380 # Number of seconds simulated
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sim_ticks 409379703500 # Number of ticks simulated
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final_tick 409379703500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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2014-07-23 23:09:05 +02:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2014-10-09 23:52:13 +02:00
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host_inst_rate 295886 # Simulator instruction rate (inst/s)
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host_op_rate 295886 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 197956312 # Simulator tick rate (ticks/s)
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host_mem_usage 239696 # Number of bytes of host memory used
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host_seconds 2068.03 # Real time elapsed on the host
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2014-07-23 23:09:05 +02:00
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sim_insts 611901617 # Number of instructions simulated
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sim_ops 611901617 # Number of ops (including micro ops) simulated
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2014-07-28 07:48:21 +02:00
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system.voltage_domain.voltage 1 # Voltage in Volts
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2014-07-23 23:09:05 +02:00
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system.clk_domain.clock 1000 # Clock period in ticks
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2014-09-20 23:18:53 +02:00
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system.physmem.bytes_read::cpu.inst 24321024 # Number of bytes read from this memory
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system.physmem.bytes_read::total 24321024 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 170880 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 170880 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 18723904 # Number of bytes written to this memory
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system.physmem.bytes_written::total 18723904 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 380016 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 380016 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 292561 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 292561 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 59409452 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 59409452 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 417412 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 417412 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 45737255 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 45737255 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 45737255 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 59409452 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 105146708 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 380016 # Number of read requests accepted
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system.physmem.writeReqs 292561 # Number of write requests accepted
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system.physmem.readBursts 380016 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 292561 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 24297984 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 23040 # Total number of bytes read from write queue
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system.physmem.bytesWritten 18722304 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 24321024 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 18723904 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 360 # Number of DRAM read bursts serviced by the write queue
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2014-07-23 23:09:05 +02:00
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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2014-09-20 23:18:53 +02:00
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system.physmem.perBankRdBursts::0 23733 # Per bank write bursts
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system.physmem.perBankRdBursts::1 23212 # Per bank write bursts
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system.physmem.perBankRdBursts::2 23513 # Per bank write bursts
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system.physmem.perBankRdBursts::3 24527 # Per bank write bursts
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system.physmem.perBankRdBursts::4 25463 # Per bank write bursts
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system.physmem.perBankRdBursts::5 23584 # Per bank write bursts
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system.physmem.perBankRdBursts::6 23682 # Per bank write bursts
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system.physmem.perBankRdBursts::7 23974 # Per bank write bursts
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system.physmem.perBankRdBursts::8 23187 # Per bank write bursts
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2014-07-28 07:48:21 +02:00
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system.physmem.perBankRdBursts::9 23951 # Per bank write bursts
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2014-09-20 23:18:53 +02:00
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system.physmem.perBankRdBursts::10 24675 # Per bank write bursts
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system.physmem.perBankRdBursts::11 22741 # Per bank write bursts
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system.physmem.perBankRdBursts::12 23717 # Per bank write bursts
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system.physmem.perBankRdBursts::13 24415 # Per bank write bursts
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system.physmem.perBankRdBursts::14 22809 # Per bank write bursts
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system.physmem.perBankRdBursts::15 22473 # Per bank write bursts
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system.physmem.perBankWrBursts::0 17752 # Per bank write bursts
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2014-09-03 13:42:59 +02:00
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system.physmem.perBankWrBursts::1 17434 # Per bank write bursts
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2014-07-28 07:48:21 +02:00
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system.physmem.perBankWrBursts::2 17902 # Per bank write bursts
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2014-09-20 23:18:53 +02:00
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system.physmem.perBankWrBursts::3 18771 # Per bank write bursts
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2014-07-28 07:48:21 +02:00
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system.physmem.perBankWrBursts::4 19442 # Per bank write bursts
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system.physmem.perBankWrBursts::5 18539 # Per bank write bursts
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2014-09-20 23:18:53 +02:00
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system.physmem.perBankWrBursts::6 18683 # Per bank write bursts
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system.physmem.perBankWrBursts::7 18574 # Per bank write bursts
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2014-09-03 13:42:59 +02:00
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system.physmem.perBankWrBursts::8 18353 # Per bank write bursts
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2014-07-23 23:09:05 +02:00
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system.physmem.perBankWrBursts::9 18833 # Per bank write bursts
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2014-09-20 23:18:53 +02:00
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system.physmem.perBankWrBursts::10 19130 # Per bank write bursts
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system.physmem.perBankWrBursts::11 17961 # Per bank write bursts
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system.physmem.perBankWrBursts::12 18219 # Per bank write bursts
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system.physmem.perBankWrBursts::13 18693 # Per bank write bursts
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2014-09-03 13:42:59 +02:00
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system.physmem.perBankWrBursts::14 17148 # Per bank write bursts
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2014-09-20 23:18:53 +02:00
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system.physmem.perBankWrBursts::15 17102 # Per bank write bursts
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2014-07-28 07:48:21 +02:00
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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2014-09-20 23:18:53 +02:00
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system.physmem.totGap 409379622500 # Total gap between requests
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2014-07-28 07:48:21 +02:00
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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2014-09-20 23:18:53 +02:00
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system.physmem.readPktSize::6 380016 # Read request sizes (log2)
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2014-07-28 07:48:21 +02:00
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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2014-09-20 23:18:53 +02:00
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system.physmem.writePktSize::6 292561 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 378259 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 1382 # What read queue length does an incoming req see
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2014-07-23 23:09:05 +02:00
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system.physmem.rdQLenPdf::2 15 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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2014-09-20 23:18:53 +02:00
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system.physmem.wrQLenPdf::15 6764 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 7315 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 16914 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 17326 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 17416 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 17418 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 17396 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 17393 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 17401 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 17400 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 17401 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 17389 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 17535 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 17502 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 17406 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 17637 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 17404 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 17309 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 44 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 33 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 25 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 23 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 17 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 15 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 13 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 10 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 12 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 9 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 4 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 3 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 3 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 2 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 2 # What write queue length does an incoming req see
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2014-07-28 07:48:21 +02:00
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
2014-07-23 23:09:05 +02:00
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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2014-09-20 23:18:53 +02:00
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system.physmem.bytesPerActivate::samples 141528 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 303.959754 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 180.049332 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 326.018132 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 50528 35.70% 35.70% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 38641 27.30% 63.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 12939 9.14% 72.15% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 7964 5.63% 77.77% # Bytes accessed per row activation
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|
|
system.physmem.bytesPerActivate::512-639 5792 4.09% 81.87% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::640-767 3807 2.69% 84.56% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::768-895 3019 2.13% 86.69% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::896-1023 2550 1.80% 88.49% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::1024-1151 16288 11.51% 100.00% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::total 141528 # Bytes accessed per row activation
|
|
|
|
|
system.physmem.rdPerTurnAround::samples 17267 # Reads before turning the bus around for writes
|
|
|
|
|
system.physmem.rdPerTurnAround::mean 21.986332 # Reads before turning the bus around for writes
|
|
|
|
|
system.physmem.rdPerTurnAround::stdev 228.214102 # Reads before turning the bus around for writes
|
|
|
|
|
system.physmem.rdPerTurnAround::0-1023 17257 99.94% 99.94% # Reads before turning the bus around for writes
|
2014-07-28 07:48:21 +02:00
|
|
|
system.physmem.rdPerTurnAround::1024-2047 7 0.04% 99.98% # Reads before turning the bus around for writes
|
2014-09-20 23:18:53 +02:00
|
|
|
system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.99% # Reads before turning the bus around for writes
|
2014-07-28 07:48:21 +02:00
|
|
|
system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes
|
2014-09-20 23:18:53 +02:00
|
|
|
system.physmem.rdPerTurnAround::total 17267 # Reads before turning the bus around for writes
|
|
|
|
|
system.physmem.wrPerTurnAround::samples 17267 # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::mean 16.941912 # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::gmean 16.866733 # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::stdev 2.774183 # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::16-19 17056 98.78% 98.78% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::20-23 152 0.88% 99.66% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::24-27 31 0.18% 99.84% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::28-31 11 0.06% 99.90% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::32-35 2 0.01% 99.91% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::36-39 1 0.01% 99.92% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::40-43 1 0.01% 99.92% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::44-47 1 0.01% 99.93% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::52-55 1 0.01% 99.94% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::56-59 2 0.01% 99.95% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::60-63 1 0.01% 99.96% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::72-75 2 0.01% 99.97% # Writes before turning the bus around for reads
|
2014-07-28 07:48:21 +02:00
|
|
|
system.physmem.wrPerTurnAround::80-83 1 0.01% 99.98% # Writes before turning the bus around for reads
|
2014-09-20 23:18:53 +02:00
|
|
|
system.physmem.wrPerTurnAround::84-87 1 0.01% 99.98% # Writes before turning the bus around for reads
|
2014-07-28 07:48:21 +02:00
|
|
|
system.physmem.wrPerTurnAround::120-123 1 0.01% 99.99% # Writes before turning the bus around for reads
|
2014-09-20 23:18:53 +02:00
|
|
|
system.physmem.wrPerTurnAround::168-171 1 0.01% 99.99% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::236-239 1 0.01% 100.00% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::total 17267 # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.totQLat 4096707750 # Total ticks spent queuing
|
|
|
|
|
system.physmem.totMemAccLat 11215257750 # Total ticks spent from burst creation until serviced by the DRAM
|
|
|
|
|
system.physmem.totBusLat 1898280000 # Total ticks spent in databus transfers
|
|
|
|
|
system.physmem.avgQLat 10790.58 # Average queueing delay per DRAM burst
|
2014-07-28 07:48:21 +02:00
|
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
2014-09-20 23:18:53 +02:00
|
|
|
system.physmem.avgMemAccLat 29540.58 # Average memory access latency per DRAM burst
|
|
|
|
|
system.physmem.avgRdBW 59.35 # Average DRAM read bandwidth in MiByte/s
|
|
|
|
|
system.physmem.avgWrBW 45.73 # Average achieved write bandwidth in MiByte/s
|
|
|
|
|
system.physmem.avgRdBWSys 59.41 # Average system read bandwidth in MiByte/s
|
|
|
|
|
system.physmem.avgWrBWSys 45.74 # Average system write bandwidth in MiByte/s
|
2014-07-28 07:48:21 +02:00
|
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
|
|
|
system.physmem.busUtil 0.82 # Data bus utilization in percentage
|
|
|
|
|
system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads
|
|
|
|
|
system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes
|
|
|
|
|
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
2014-09-20 23:18:53 +02:00
|
|
|
system.physmem.avgWrQLen 21.14 # Average write queue length when enqueuing
|
|
|
|
|
system.physmem.readRowHits 314853 # Number of row buffer hits during reads
|
|
|
|
|
system.physmem.writeRowHits 215803 # Number of row buffer hits during writes
|
|
|
|
|
system.physmem.readRowHitRate 82.93 # Row buffer hit rate for reads
|
|
|
|
|
system.physmem.writeRowHitRate 73.76 # Row buffer hit rate for writes
|
|
|
|
|
system.physmem.avgGap 608673.24 # Average gap between requests
|
|
|
|
|
system.physmem.pageHitRate 78.94 # Row buffer hit rate, read and write combined
|
|
|
|
|
system.physmem.memoryStateTime::IDLE 275372649250 # Time in different power states
|
|
|
|
|
system.physmem.memoryStateTime::REF 13670020000 # Time in different power states
|
2014-07-28 07:48:21 +02:00
|
|
|
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
2014-09-20 23:18:53 +02:00
|
|
|
system.physmem.memoryStateTime::ACT 120335301000 # Time in different power states
|
2014-07-28 07:48:21 +02:00
|
|
|
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
2014-10-09 23:52:13 +02:00
|
|
|
system.physmem.actEnergy::0 544939920 # Energy for activate commands per rank (pJ)
|
|
|
|
|
system.physmem.actEnergy::1 524943720 # Energy for activate commands per rank (pJ)
|
|
|
|
|
system.physmem.preEnergy::0 297338250 # Energy for precharge commands per rank (pJ)
|
|
|
|
|
system.physmem.preEnergy::1 286427625 # Energy for precharge commands per rank (pJ)
|
|
|
|
|
system.physmem.readEnergy::0 1495143000 # Energy for read commands per rank (pJ)
|
|
|
|
|
system.physmem.readEnergy::1 1465986600 # Energy for read commands per rank (pJ)
|
|
|
|
|
system.physmem.writeEnergy::0 953104320 # Energy for write commands per rank (pJ)
|
|
|
|
|
system.physmem.writeEnergy::1 942425280 # Energy for write commands per rank (pJ)
|
|
|
|
|
system.physmem.refreshEnergy::0 26738559120 # Energy for refresh commands per rank (pJ)
|
|
|
|
|
system.physmem.refreshEnergy::1 26738559120 # Energy for refresh commands per rank (pJ)
|
|
|
|
|
system.physmem.actBackEnergy::0 61488174015 # Energy for active background per rank (pJ)
|
|
|
|
|
system.physmem.actBackEnergy::1 58208465835 # Energy for active background per rank (pJ)
|
|
|
|
|
system.physmem.preBackEnergy::0 191689779750 # Energy for precharge background per rank (pJ)
|
|
|
|
|
system.physmem.preBackEnergy::1 194566716750 # Energy for precharge background per rank (pJ)
|
|
|
|
|
system.physmem.totalEnergy::0 283207038375 # Total energy per rank (pJ)
|
|
|
|
|
system.physmem.totalEnergy::1 282733524930 # Total energy per rank (pJ)
|
|
|
|
|
system.physmem.averagePower::0 691.798455 # Core power per rank (mW)
|
|
|
|
|
system.physmem.averagePower::1 690.641789 # Core power per rank (mW)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.membus.trans_dist::ReadReq 173391 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::ReadResp 173391 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::Writeback 292561 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::ReadExReq 206625 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::ReadExResp 206625 # Transaction distribution
|
|
|
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1052593 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_count::total 1052593 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43044928 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size::total 43044928 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
|
|
|
system.membus.snoop_fanout::samples 672577 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::0 672577 100.00% 100.00% # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::total 672577 # Request fanout histogram
|
|
|
|
|
system.membus.reqLayer0.occupancy 3204370000 # Layer occupancy (ticks)
|
2014-07-28 07:48:21 +02:00
|
|
|
system.membus.reqLayer0.utilization 0.8 # Layer utilization (%)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.membus.respLayer1.occupancy 3607409500 # Layer occupancy (ticks)
|
2014-07-28 07:48:21 +02:00
|
|
|
system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
|
|
|
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.branchPred.lookups 123709339 # Number of BP lookups
|
|
|
|
|
system.cpu.branchPred.condPredicted 87626566 # Number of conditional branches predicted
|
|
|
|
|
system.cpu.branchPred.condIncorrect 6391113 # Number of conditional branches incorrect
|
|
|
|
|
system.cpu.branchPred.BTBLookups 71478402 # Number of BTB lookups
|
|
|
|
|
system.cpu.branchPred.BTBHits 67228425 # Number of BTB hits
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.branchPred.BTBHitPct 94.054180 # BTB Hit Percentage
|
|
|
|
|
system.cpu.branchPred.usedRAS 14930713 # Number of times the RAS was used to get a target.
|
|
|
|
|
system.cpu.branchPred.RASInCorrect 1120398 # Number of incorrect RAS predictions.
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
|
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
|
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
|
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dtb.read_hits 149300115 # DTB read hits
|
|
|
|
|
system.cpu.dtb.read_misses 537223 # DTB read misses
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dtb.read_accesses 149837338 # DTB read accesses
|
|
|
|
|
system.cpu.dtb.write_hits 57314034 # DTB write hits
|
|
|
|
|
system.cpu.dtb.write_misses 66532 # DTB write misses
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dtb.write_accesses 57380566 # DTB write accesses
|
|
|
|
|
system.cpu.dtb.data_hits 206614149 # DTB hits
|
|
|
|
|
system.cpu.dtb.data_misses 603755 # DTB misses
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dtb.data_accesses 207217904 # DTB accesses
|
|
|
|
|
system.cpu.itb.fetch_hits 225746689 # ITB hits
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.itb.fetch_misses 48 # ITB misses
|
|
|
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.itb.fetch_accesses 225746737 # ITB accesses
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
|
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
|
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
|
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
|
|
|
system.cpu.workload.num_syscalls 485 # Number of system calls
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.numCycles 818759407 # number of cpu cycles simulated
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
|
|
|
system.cpu.committedInsts 611901617 # Number of instructions committed
|
|
|
|
|
system.cpu.committedOps 611901617 # Number of ops (including micro ops) committed
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.discardedOps 13148655 # Number of ops (including micro ops) which were discarded before commit
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.cpi 1.338057 # CPI: cycles per instruction
|
|
|
|
|
system.cpu.ipc 0.747352 # IPC: instructions per cycle
|
|
|
|
|
system.cpu.tickCycles 736857348 # Number of cycles that the object actually ticked
|
|
|
|
|
system.cpu.idleCycles 81902059 # Total number of cycles that the object has spent stopped
|
|
|
|
|
system.cpu.icache.tags.replacements 3155 # number of replacements
|
|
|
|
|
system.cpu.icache.tags.tagsinuse 1116.246910 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.tags.total_refs 225741705 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.tags.sampled_refs 4984 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.tags.avg_refs 45293.279494 # Average number of references to valid blocks.
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1116.246910 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.545042 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.tags.occ_percent::total 0.545042 # Average percentage of cache occupancy
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 77 # Occupied blocks per task id
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 1590 # Occupied blocks per task id
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.icache.tags.tag_accesses 451498362 # Number of tag accesses
|
|
|
|
|
system.cpu.icache.tags.data_accesses 451498362 # Number of data accesses
|
|
|
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 225741705 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_hits::total 225741705 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits::cpu.inst 225741705 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_hits::total 225741705 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits::cpu.inst 225741705 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_hits::total 225741705 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 4984 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::total 4984 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses::cpu.inst 4984 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_misses::total 4984 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses::cpu.inst 4984 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_misses::total 4984 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 227159500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::total 227159500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 227159500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::total 227159500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 227159500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::total 227159500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 225746689 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::total 225746689 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses::cpu.inst 225746689 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_accesses::total 225746689 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::cpu.inst 225746689 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::total 225746689 # number of overall (read+write) accesses
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45577.748796 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 45577.748796 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 45577.748796 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::total 45577.748796 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 45577.748796 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::total 45577.748796 # average overall miss latency
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4984 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::total 4984 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 4984 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::total 4984 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 4984 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::total 4984 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 216090500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 216090500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 216090500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::total 216090500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 216090500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::total 216090500 # number of overall MSHR miss cycles
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43356.841894 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43356.841894 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43356.841894 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 43356.841894 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43356.841894 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 43356.841894 # average overall mshr miss latency
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 1766375 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 1766375 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::Writeback 2340053 # Transaction distribution
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 778163 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 778163 # Transaction distribution
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9968 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7419161 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count::total 7429129 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 318976 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312294848 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size::total 312613824 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::samples 4884591 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::1 4884591 100.00% 100.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::total 4884591 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 4782348500 # Layer occupancy (ticks)
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.toL2Bus.respLayer0.occupancy 8026500 # Layer occupancy (ticks)
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.toL2Bus.respLayer1.occupancy 3891677000 # Layer occupancy (ticks)
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.tags.replacements 347305 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tags.tagsinuse 29490.835705 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.tags.total_refs 3711078 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.tags.sampled_refs 379729 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.tags.avg_refs 9.772964 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.tags.warmup_cycle 188662245000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 21414.068024 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 8076.767680 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.653505 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.246483 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::total 0.899989 # Average percentage of cache occupancy
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32424 # Occupied blocks per task id
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 224 # Occupied blocks per task id
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13174 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18828 # Occupied blocks per task id
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.989502 # Percentage of cache occupancy per task id
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.tags.tag_accesses 40234620 # Number of tag accesses
|
|
|
|
|
system.cpu.l2cache.tags.data_accesses 40234620 # Number of data accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 1592984 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::total 1592984 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::writebacks 2340053 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::total 2340053 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.inst 571538 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::total 571538 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.inst 2164522 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::total 2164522 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.inst 2164522 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::total 2164522 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 173391 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::total 173391 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.inst 206625 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::total 206625 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.inst 380016 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::total 380016 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.inst 380016 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::total 380016 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12672589500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 12672589500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 14785830500 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 14785830500 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 27458420000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::total 27458420000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 27458420000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::total 27458420000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1766375 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::total 1766375 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 2340053 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::total 2340053 # number of Writeback accesses(hits+misses)
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.inst 778163 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::total 778163 # number of ReadExReq accesses(hits+misses)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 2544538 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::total 2544538 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 2544538 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::total 2544538 # number of overall (read+write) accesses
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.098162 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.098162 # miss rate for ReadReq accesses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.265529 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.265529 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.149346 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::total 0.149346 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.149346 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::total 0.149346 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73086.777860 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 73086.777860 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71558.768300 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71558.768300 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72255.957644 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 72255.957644 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72255.957644 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 72255.957644 # average overall miss latency
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.writebacks::writebacks 292561 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.writebacks::total 292561 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 173391 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 173391 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 206625 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 206625 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 380016 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::total 380016 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 380016 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::total 380016 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10460652500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10460652500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 12167413500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12167413500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22628066000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 22628066000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22628066000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 22628066000 # number of overall MSHR miss cycles
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.098162 # mshr miss rate for ReadReq accesses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.265529 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265529 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.149346 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.149346 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.149346 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.149346 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60329.846993 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60329.846993 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58886.453721 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58886.453721 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59545.034946 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59545.034946 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59545.034946 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59545.034946 # average overall mshr miss latency
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dcache.tags.replacements 2535458 # number of replacements
|
|
|
|
|
system.cpu.dcache.tags.tagsinuse 4087.758418 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.tags.total_refs 202542728 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.tags.sampled_refs 2539554 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.tags.avg_refs 79.755236 # Average number of references to valid blocks.
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.dcache.tags.warmup_cycle 1608245250 # Cycle when the warmup percentage was hit.
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dcache.tags.occ_blocks::cpu.inst 4087.758418 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.dcache.tags.occ_percent::cpu.inst 0.997988 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.tags.occ_percent::total 0.997988 # Average percentage of cache occupancy
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 828 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 3146 # Occupied blocks per task id
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dcache.tags.tag_accesses 414529138 # Number of tag accesses
|
|
|
|
|
system.cpu.dcache.tags.data_accesses 414529138 # Number of data accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::cpu.inst 146876552 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::total 146876552 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::cpu.inst 55666176 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::total 55666176 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits::cpu.inst 202542728 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_hits::total 202542728 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits::cpu.inst 202542728 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_hits::total 202542728 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::cpu.inst 1908206 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::total 1908206 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::cpu.inst 1543858 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::total 1543858 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses::cpu.inst 3452064 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_misses::total 3452064 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses::cpu.inst 3452064 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_misses::total 3452064 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 36392982500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::total 36392982500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 45181402750 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::total 45181402750 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::cpu.inst 81574385250 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::total 81574385250 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::cpu.inst 81574385250 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::total 81574385250 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::cpu.inst 148784758 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::total 148784758 # number of ReadReq accesses(hits+misses)
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.dcache.WriteReq_accesses::cpu.inst 57210034 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::total 57210034 # number of WriteReq accesses(hits+misses)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dcache.demand_accesses::cpu.inst 205994792 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 205994792 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.inst 205994792 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 205994792 # number of overall (read+write) accesses
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.012825 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.012825 # miss rate for ReadReq accesses
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.026986 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.026986 # miss rate for WriteReq accesses
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.inst 0.016758 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::total 0.016758 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.inst 0.016758 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::total 0.016758 # miss rate for overall accesses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 19071.831081 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 19071.831081 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29265.258042 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 29265.258042 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 23630.612077 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::total 23630.612077 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 23630.612077 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::total 23630.612077 # average overall miss latency
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dcache.writebacks::writebacks 2340053 # number of writebacks
|
|
|
|
|
system.cpu.dcache.writebacks::total 2340053 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 143482 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 143482 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 769028 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 769028 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::cpu.inst 912510 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::total 912510 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::cpu.inst 912510 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::total 912510 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1764724 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 1764724 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 774830 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 774830 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::cpu.inst 2539554 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::total 2539554 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::cpu.inst 2539554 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::total 2539554 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 30222763750 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 30222763750 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 21236491750 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 21236491750 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 51459255500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 51459255500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 51459255500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 51459255500 # number of overall MSHR miss cycles
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.011861 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.011861 # mshr miss rate for ReadReq accesses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.013544 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.013544 # mshr miss rate for WriteReq accesses
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.012328 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.012328 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.012328 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.012328 # mshr miss rate for overall accesses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 17126.056964 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17126.056964 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 27407.936902 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27407.936902 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 20263.107420 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20263.107420 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 20263.107420 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20263.107420 # average overall mshr miss latency
|
2014-07-28 07:48:21 +02:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2014-07-23 23:09:05 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
