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gem5/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt

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cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
---------- Begin Simulation Statistics ----------
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
sim_seconds 0.410940 # Number of seconds simulated
sim_ticks 410940483000 # Number of ticks simulated
final_tick 410940483000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
host_inst_rate 339016 # Simulator instruction rate (inst/s)
host_op_rate 339016 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 227676015 # Simulator tick rate (ticks/s)
host_mem_usage 297088 # Number of bytes of host memory used
host_seconds 1804.94 # Real time elapsed on the host
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
sim_insts 611901617 # Number of instructions simulated
sim_ops 611901617 # Number of ops (including micro ops) simulated
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.voltage_domain.voltage 1 # Voltage in Volts
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
system.clk_domain.clock 1000 # Clock period in ticks
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.bytes_read::cpu.inst 24320576 # Number of bytes read from this memory
system.physmem.bytes_read::total 24320576 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 171008 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 171008 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 18724416 # Number of bytes written to this memory
system.physmem.bytes_written::total 18724416 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 380009 # Number of read requests responded to by this memory
system.physmem.num_reads::total 380009 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 292569 # Number of write requests responded to by this memory
system.physmem.num_writes::total 292569 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 59182721 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 59182721 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 416138 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 416138 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 45564788 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 45564788 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 45564788 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 59182721 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 104747509 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 380009 # Number of read requests accepted
system.physmem.writeReqs 292569 # Number of write requests accepted
system.physmem.readBursts 380009 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 292569 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 24297024 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 23552 # Total number of bytes read from write queue
system.physmem.bytesWritten 18722752 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 24320576 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 18724416 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 368 # Number of DRAM read bursts serviced by the write queue
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankRdBursts::0 23736 # Per bank write bursts
system.physmem.perBankRdBursts::1 23216 # Per bank write bursts
system.physmem.perBankRdBursts::2 23510 # Per bank write bursts
system.physmem.perBankRdBursts::3 24529 # Per bank write bursts
system.physmem.perBankRdBursts::4 25457 # Per bank write bursts
system.physmem.perBankRdBursts::5 23594 # Per bank write bursts
system.physmem.perBankRdBursts::6 23677 # Per bank write bursts
system.physmem.perBankRdBursts::7 23981 # Per bank write bursts
system.physmem.perBankRdBursts::8 23173 # Per bank write bursts
system.physmem.perBankRdBursts::9 23945 # Per bank write bursts
system.physmem.perBankRdBursts::10 24675 # Per bank write bursts
system.physmem.perBankRdBursts::11 22741 # Per bank write bursts
system.physmem.perBankRdBursts::12 23723 # Per bank write bursts
system.physmem.perBankRdBursts::13 24409 # Per bank write bursts
system.physmem.perBankRdBursts::14 22807 # Per bank write bursts
system.physmem.perBankRdBursts::15 22468 # Per bank write bursts
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.perBankWrBursts::0 17754 # Per bank write bursts
system.physmem.perBankWrBursts::1 17431 # Per bank write bursts
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankWrBursts::2 17901 # Per bank write bursts
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.perBankWrBursts::3 18773 # Per bank write bursts
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.perBankWrBursts::4 19442 # Per bank write bursts
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.perBankWrBursts::5 18543 # Per bank write bursts
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankWrBursts::6 18677 # Per bank write bursts
system.physmem.perBankWrBursts::7 18574 # Per bank write bursts
system.physmem.perBankWrBursts::8 18352 # Per bank write bursts
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
system.physmem.perBankWrBursts::9 18833 # Per bank write bursts
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.perBankWrBursts::10 19127 # Per bank write bursts
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankWrBursts::11 17966 # Per bank write bursts
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.perBankWrBursts::12 18224 # Per bank write bursts
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankWrBursts::13 18695 # Per bank write bursts
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.perBankWrBursts::14 17148 # Per bank write bursts
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.perBankWrBursts::15 17103 # Per bank write bursts
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.totGap 410940401000 # Total gap between requests
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.readPktSize::6 380009 # Read request sizes (log2)
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.writePktSize::6 292569 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 378252 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1375 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.wrQLenPdf::15 6958 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 7441 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 16889 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 17304 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 17388 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 17416 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 17420 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 17393 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 17392 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 17410 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 17400 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 17408 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 17492 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 17470 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 17454 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 17578 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 17334 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 17286 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 20 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.bytesPerActivate::samples 142331 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 302.240383 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 178.797095 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 325.472154 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 51326 36.06% 36.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 38738 27.22% 63.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 13057 9.17% 72.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 7891 5.54% 78.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 5698 4.00% 82.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 3672 2.58% 84.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 3107 2.18% 86.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 2648 1.86% 88.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 16194 11.38% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 142331 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 17261 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 21.992932 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 228.052387 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 17249 99.93% 99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.99% # Reads before turning the bus around for writes
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.rdPerTurnAround::total 17261 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 17261 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.948207 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.879580 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 2.601828 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 17058 98.82% 98.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 154 0.89% 99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 25 0.14% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 10 0.06% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 4 0.02% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 2 0.01% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 1 0.01% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 1 0.01% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 1 0.01% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 1 0.01% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 2 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151 1 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::220-223 1 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 17261 # Writes before turning the bus around for reads
system.physmem.totQLat 4019056000 # Total ticks spent queuing
system.physmem.totMemAccLat 11137324750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 1898205000 # Total ticks spent in databus transfers
system.physmem.avgQLat 10586.46 # Average queueing delay per DRAM burst
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.avgMemAccLat 29336.46 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 59.13 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 45.56 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 59.18 # Average system read bandwidth in MiByte/s
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.avgWrBWSys 45.56 # Average system write bandwidth in MiByte/s
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.82 # Data bus utilization in percentage
system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.avgWrQLen 20.74 # Average write queue length when enqueuing
system.physmem.readRowHits 314673 # Number of row buffer hits during reads
system.physmem.writeRowHits 215171 # Number of row buffer hits during writes
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.readRowHitRate 82.89 # Row buffer hit rate for reads
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.writeRowHitRate 73.55 # Row buffer hit rate for writes
system.physmem.avgGap 610992.93 # Average gap between requests
system.physmem.pageHitRate 78.82 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 547495200 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 298732500 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1495119600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 953078400 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 26840271120 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 61546767165 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 192572713500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 284254177485 # Total energy per rank (pJ)
system.physmem_0.averagePower 691.725104 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 319820574750 # Time in different power states
system.physmem_0.memoryStateTime::REF 13722020000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 77392866750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 528262560 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 288238500 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1465495200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 942392880 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 26840271120 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 58539586815 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 195210595500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 283814842575 # Total energy per rank (pJ)
system.physmem_1.averagePower 690.655981 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 324225356250 # Time in different power states
system.physmem_1.memoryStateTime::REF 13722020000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 72987820500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 124267347 # Number of BP lookups
system.cpu.branchPred.condPredicted 87926966 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 6405633 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 71910290 # Number of BTB lookups
system.cpu.branchPred.BTBHits 67438494 # Number of BTB hits
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.branchPred.BTBHitPct 93.781424 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 15062581 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 1126311 # Number of incorrect RAS predictions.
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dtb.read_hits 149395037 # DTB read hits
system.cpu.dtb.read_misses 569044 # DTB read misses
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.dtb.read_acv 0 # DTB read access violations
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dtb.read_accesses 149964081 # DTB read accesses
system.cpu.dtb.write_hits 57322306 # DTB write hits
system.cpu.dtb.write_misses 67257 # DTB write misses
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.dtb.write_acv 0 # DTB write access violations
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dtb.write_accesses 57389563 # DTB write accesses
system.cpu.dtb.data_hits 206717343 # DTB hits
system.cpu.dtb.data_misses 636301 # DTB misses
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.dtb.data_acv 0 # DTB access violations
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dtb.data_accesses 207353644 # DTB accesses
system.cpu.itb.fetch_hits 226796884 # ITB hits
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.itb.fetch_misses 48 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.itb.fetch_accesses 226796932 # ITB accesses
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 485 # Number of system calls
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.numCycles 821880966 # number of cpu cycles simulated
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 611901617 # Number of instructions committed
system.cpu.committedOps 611901617 # Number of ops (including micro ops) committed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.discardedOps 12979255 # Number of ops (including micro ops) which were discarded before commit
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.cpi 1.343159 # CPI: cycles per instruction
system.cpu.ipc 0.744514 # IPC: instructions per cycle
system.cpu.tickCycles 741712966 # Number of cycles that the object actually ticked
system.cpu.idleCycles 80168000 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 2535450 # number of replacements
system.cpu.dcache.tags.tagsinuse 4087.778260 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 202631199 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2539546 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 79.790324 # Average number of references to valid blocks.
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.tags.warmup_cycle 1608227250 # Cycle when the warmup percentage was hit.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.occ_blocks::cpu.inst 4087.778260 # Average occupied blocks per requestor
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.tags.occ_percent::cpu.inst 0.997993 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.997993 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 829 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 3145 # Occupied blocks per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.tag_accesses 414706244 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 414706244 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.inst 146964985 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 146964985 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.inst 55666214 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 55666214 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.inst 202631199 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 202631199 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.inst 202631199 # number of overall hits
system.cpu.dcache.overall_hits::total 202631199 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.inst 1908330 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1908330 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.inst 1543820 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1543820 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.inst 3452150 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3452150 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.inst 3452150 # number of overall misses
system.cpu.dcache.overall_misses::total 3452150 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 36414832750 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 36414832750 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 44905898000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 44905898000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.inst 81320730750 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 81320730750 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.inst 81320730750 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 81320730750 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.inst 148873315 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 148873315 # number of ReadReq accesses(hits+misses)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.inst 57210034 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 57210034 # number of WriteReq accesses(hits+misses)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.demand_accesses::cpu.inst 206083349 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 206083349 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.inst 206083349 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 206083349 # number of overall (read+write) accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.012818 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.012818 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.026985 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.026985 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.inst 0.016751 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.016751 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.inst 0.016751 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.016751 # miss rate for overall accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 19082.041759 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 19082.041759 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29087.521861 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 29087.521861 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 23556.546138 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 23556.546138 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 23556.546138 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 23556.546138 # average overall miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.writebacks::writebacks 2340060 # number of writebacks
system.cpu.dcache.writebacks::total 2340060 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 143560 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 143560 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 769044 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 769044 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.inst 912604 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 912604 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.inst 912604 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 912604 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1764770 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1764770 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 774776 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 774776 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.inst 2539546 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2539546 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.inst 2539546 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2539546 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 30222614500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 30222614500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 21167535500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 21167535500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 51390150000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 51390150000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 51390150000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 51390150000 # number of overall MSHR miss cycles
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.011854 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.011854 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.013543 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.013543 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.012323 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.012323 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.012323 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.012323 # mshr miss rate for overall accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 17125.525989 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17125.525989 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 27320.845638 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27320.845638 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 20235.959498 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20235.959498 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 20235.959498 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20235.959498 # average overall mshr miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.tags.replacements 3192 # number of replacements
system.cpu.icache.tags.tagsinuse 1117.017357 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 226791863 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 5021 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 45168.664210 # Average number of references to valid blocks.
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.tags.occ_blocks::cpu.inst 1117.017357 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.545419 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.545419 # Average percentage of cache occupancy
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 75 # Occupied blocks per task id
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::4 1590 # Occupied blocks per task id
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.tags.tag_accesses 453598789 # Number of tag accesses
system.cpu.icache.tags.data_accesses 453598789 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 226791863 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 226791863 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 226791863 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 226791863 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 226791863 # number of overall hits
system.cpu.icache.overall_hits::total 226791863 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 5021 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 5021 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 5021 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 5021 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 5021 # number of overall misses
system.cpu.icache.overall_misses::total 5021 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 229227250 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 229227250 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 229227250 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 229227250 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 229227250 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 229227250 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 226796884 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 226796884 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 226796884 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 226796884 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 226796884 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 226796884 # number of overall (read+write) accesses
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45653.704441 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 45653.704441 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 45653.704441 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 45653.704441 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 45653.704441 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 45653.704441 # average overall miss latency
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5021 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 5021 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 5021 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 5021 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 5021 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 5021 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 218087750 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 218087750 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 218087750 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 218087750 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 218087750 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 218087750 # number of overall MSHR miss cycles
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43435.122486 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43435.122486 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43435.122486 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 43435.122486 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43435.122486 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 43435.122486 # average overall mshr miss latency
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.replacements 347298 # number of replacements
system.cpu.l2cache.tags.tagsinuse 29498.877271 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3711146 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 379722 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 9.773324 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 188676425000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 21419.098483 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 8079.778788 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.653659 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.246575 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.900234 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32424 # Occupied blocks per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 224 # Occupied blocks per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13171 # Occupied blocks per task id
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18831 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.989502 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 40234870 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 40234870 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 1593052 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1593052 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 2340060 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 2340060 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.inst 571506 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 571506 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2164558 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2164558 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 2164558 # number of overall hits
system.cpu.l2cache.overall_hits::total 2164558 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 173383 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 173383 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.inst 206626 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 206626 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 380009 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 380009 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 380009 # number of overall misses
system.cpu.l2cache.overall_misses::total 380009 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12672404250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 12672404250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 14718134000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 14718134000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 27390538250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 27390538250 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 27390538250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 27390538250 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1766435 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1766435 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 2340060 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 2340060 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.inst 778132 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 778132 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 2544567 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2544567 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 2544567 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2544567 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.098154 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.098154 # miss rate for ReadReq accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.265541 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.265541 # miss rate for ReadExReq accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.149341 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.149341 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.149341 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.149341 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73089.081686 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 73089.081686 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71230.793801 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71230.793801 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72078.656690 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 72078.656690 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72078.656690 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 72078.656690 # average overall miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.writebacks::writebacks 292569 # number of writebacks
system.cpu.l2cache.writebacks::total 292569 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 173383 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 173383 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 206626 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 206626 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 380009 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 380009 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 380009 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 380009 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10460839250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10460839250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 12089060000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12089060000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22549899250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 22549899250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22549899250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 22549899250 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.098154 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.098154 # mshr miss rate for ReadReq accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.265541 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265541 # mshr miss rate for ReadExReq accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.149341 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.149341 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.149341 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.149341 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60333.707745 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60333.707745 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58506.964274 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58506.964274 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59340.434700 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59340.434700 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59340.434700 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59340.434700 # average overall mshr miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.trans_dist::ReadReq 1766435 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 1766435 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 2340060 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 778132 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 778132 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10042 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7419152 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 7429194 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 321344 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312294784 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 312616128 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::samples 4884627 # Request fanout histogram
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::1 4884627 100.00% 100.00% # Request fanout histogram
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::total 4884627 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 4782373500 # Layer occupancy (ticks)
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.respLayer0.occupancy 8080250 # Layer occupancy (ticks)
stats: Bump stats for the regressions using the minor CPU Updating the stats to match the current behaviour.
2014-07-28 07:48:21 +02:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 3891629500 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.trans_dist::ReadReq 173383 # Transaction distribution
system.membus.trans_dist::ReadResp 173383 # Transaction distribution
system.membus.trans_dist::Writeback 292569 # Transaction distribution
system.membus.trans_dist::ReadExReq 206626 # Transaction distribution
system.membus.trans_dist::ReadExResp 206626 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1052587 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1052587 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43044992 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 43044992 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoops 0 # Total snoops (count)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::samples 672578 # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::0 672578 100.00% 100.00% # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::total 672578 # Request fanout histogram
system.membus.reqLayer0.occupancy 3222626500 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer0.utilization 0.8 # Layer utilization (%)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.respLayer1.occupancy 3617752750 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
cpu: Minor CPU add regression tests for ARM and ALPHA This patch adds regression tests results and test harnesses for the Minor CPU on ARM and ALPHA.
2014-07-23 23:09:05 +02:00
---------- End Simulation Statistics ----------
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