2007-02-07 06:16:33 +01:00
---------- Begin Simulation Statistics ----------
2015-09-25 13:27:03 +02:00
sim_seconds 0.000518 # Number of seconds simulated
sim_ticks 517786000 # Number of ticks simulated
final_tick 517786000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2012-01-25 18:19:50 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2015-09-25 13:27:03 +02:00
host_tick_rate 99723528 # Simulator tick rate (ticks/s)
host_mem_usage 280036 # Number of bytes of host memory used
host_seconds 5.19 # Real time elapsed on the host
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2015-09-25 13:27:03 +02:00
system.physmem.bytes_read::cpu0 82733 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1 82298 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2 83808 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3 81707 # Number of bytes read from this memory
system.physmem.bytes_read::cpu4 79210 # Number of bytes read from this memory
system.physmem.bytes_read::cpu5 80419 # Number of bytes read from this memory
system.physmem.bytes_read::cpu6 83957 # Number of bytes read from this memory
system.physmem.bytes_read::cpu7 82578 # Number of bytes read from this memory
system.physmem.bytes_read::total 656710 # Number of bytes read from this memory
system.physmem.bytes_written::writebacks 415488 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0 5449 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1 5329 # Number of bytes written to this memory
system.physmem.bytes_written::cpu2 5533 # Number of bytes written to this memory
system.physmem.bytes_written::cpu3 5454 # Number of bytes written to this memory
system.physmem.bytes_written::cpu4 5382 # Number of bytes written to this memory
system.physmem.bytes_written::cpu5 5483 # Number of bytes written to this memory
system.physmem.bytes_written::cpu6 5508 # Number of bytes written to this memory
system.physmem.bytes_written::cpu7 5404 # Number of bytes written to this memory
system.physmem.bytes_written::total 459030 # Number of bytes written to this memory
system.physmem.num_reads::cpu0 10913 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1 10856 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2 10917 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3 10895 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu4 10981 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu5 10993 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu6 11003 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu7 10884 # Number of read requests responded to by this memory
system.physmem.num_reads::total 87442 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 6492 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0 5449 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1 5329 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu2 5533 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu3 5454 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu4 5382 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu5 5483 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu6 5508 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu7 5404 # Number of write requests responded to by this memory
system.physmem.num_writes::total 50034 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0 159782227 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1 158942111 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2 161858374 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3 157800713 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu4 152978257 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu5 155313199 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu6 162146138 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu7 159482875 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1268303894 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 802431893 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0 10523653 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1 10291897 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu2 10685882 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu3 10533309 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu4 10394256 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu5 10589317 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu6 10637599 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu7 10436744 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 886524549 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 802431893 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0 170305879 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1 169234008 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2 172544256 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3 168334022 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu4 163372513 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu5 165902516 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu6 172783737 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu7 169919619 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2154828443 # Total bandwidth to/from this memory (bytes/s)
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2015-09-25 13:27:03 +02:00
system.cpu0.num_reads 99592 # number of read accesses completed
system.cpu0.num_writes 55369 # number of write accesses completed
system.cpu0.l1c.tags.replacements 22465 # number of replacements
system.cpu0.l1c.tags.tagsinuse 392.038302 # Cycle average of tags in use
system.cpu0.l1c.tags.total_refs 13410 # Total number of references to valid blocks.
system.cpu0.l1c.tags.sampled_refs 22854 # Sample count of references to valid blocks.
system.cpu0.l1c.tags.avg_refs 0.586768 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-09-25 13:27:03 +02:00
system.cpu0.l1c.tags.occ_blocks::cpu0 392.038302 # Average occupied blocks per requestor
system.cpu0.l1c.tags.occ_percent::cpu0 0.765700 # Average percentage of cache occupancy
system.cpu0.l1c.tags.occ_percent::total 0.765700 # Average percentage of cache occupancy
system.cpu0.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id
system.cpu0.l1c.tags.age_task_id_blocks_1024::0 379 # Occupied blocks per task id
system.cpu0.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id
system.cpu0.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id
system.cpu0.l1c.tags.tag_accesses 338870 # Number of tag accesses
system.cpu0.l1c.tags.data_accesses 338870 # Number of data accesses
system.cpu0.l1c.ReadReq_hits::cpu0 8751 # number of ReadReq hits
system.cpu0.l1c.ReadReq_hits::total 8751 # number of ReadReq hits
system.cpu0.l1c.WriteReq_hits::cpu0 1148 # number of WriteReq hits
system.cpu0.l1c.WriteReq_hits::total 1148 # number of WriteReq hits
system.cpu0.l1c.demand_hits::cpu0 9899 # number of demand (read+write) hits
system.cpu0.l1c.demand_hits::total 9899 # number of demand (read+write) hits
system.cpu0.l1c.overall_hits::cpu0 9899 # number of overall hits
system.cpu0.l1c.overall_hits::total 9899 # number of overall hits
system.cpu0.l1c.ReadReq_misses::cpu0 36676 # number of ReadReq misses
system.cpu0.l1c.ReadReq_misses::total 36676 # number of ReadReq misses
system.cpu0.l1c.WriteReq_misses::cpu0 23894 # number of WriteReq misses
system.cpu0.l1c.WriteReq_misses::total 23894 # number of WriteReq misses
system.cpu0.l1c.demand_misses::cpu0 60570 # number of demand (read+write) misses
system.cpu0.l1c.demand_misses::total 60570 # number of demand (read+write) misses
system.cpu0.l1c.overall_misses::cpu0 60570 # number of overall misses
system.cpu0.l1c.overall_misses::total 60570 # number of overall misses
system.cpu0.l1c.ReadReq_miss_latency::cpu0 605837577 # number of ReadReq miss cycles
system.cpu0.l1c.ReadReq_miss_latency::total 605837577 # number of ReadReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::cpu0 675142476 # number of WriteReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::total 675142476 # number of WriteReq miss cycles
system.cpu0.l1c.demand_miss_latency::cpu0 1280980053 # number of demand (read+write) miss cycles
system.cpu0.l1c.demand_miss_latency::total 1280980053 # number of demand (read+write) miss cycles
system.cpu0.l1c.overall_miss_latency::cpu0 1280980053 # number of overall miss cycles
system.cpu0.l1c.overall_miss_latency::total 1280980053 # number of overall miss cycles
system.cpu0.l1c.ReadReq_accesses::cpu0 45427 # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.ReadReq_accesses::total 45427 # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::cpu0 25042 # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::total 25042 # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.demand_accesses::cpu0 70469 # number of demand (read+write) accesses
system.cpu0.l1c.demand_accesses::total 70469 # number of demand (read+write) accesses
system.cpu0.l1c.overall_accesses::cpu0 70469 # number of overall (read+write) accesses
system.cpu0.l1c.overall_accesses::total 70469 # number of overall (read+write) accesses
system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807361 # miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_miss_rate::total 0.807361 # miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954157 # miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_miss_rate::total 0.954157 # miss rate for WriteReq accesses
system.cpu0.l1c.demand_miss_rate::cpu0 0.859527 # miss rate for demand accesses
system.cpu0.l1c.demand_miss_rate::total 0.859527 # miss rate for demand accesses
system.cpu0.l1c.overall_miss_rate::cpu0 0.859527 # miss rate for overall accesses
system.cpu0.l1c.overall_miss_rate::total 0.859527 # miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16518.638265 # average ReadReq miss latency
system.cpu0.l1c.ReadReq_avg_miss_latency::total 16518.638265 # average ReadReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 28255.732653 # average WriteReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::total 28255.732653 # average WriteReq miss latency
system.cpu0.l1c.demand_avg_miss_latency::cpu0 21148.754383 # average overall miss latency
system.cpu0.l1c.demand_avg_miss_latency::total 21148.754383 # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::cpu0 21148.754383 # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::total 21148.754383 # average overall miss latency
system.cpu0.l1c.blocked_cycles::no_mshrs 743435 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-09-25 13:27:03 +02:00
system.cpu0.l1c.blocked::no_mshrs 61083 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked
2015-09-25 13:27:03 +02:00
system.cpu0.l1c.avg_blocked_cycles::no_mshrs 12.170899 # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2012-01-25 18:19:50 +01:00
system.cpu0.l1c.fast_writes 0 # number of fast writes performed
system.cpu0.l1c.cache_copies 0 # number of cache copies performed
2015-09-25 13:27:03 +02:00
system.cpu0.l1c.writebacks::writebacks 9922 # number of writebacks
system.cpu0.l1c.writebacks::total 9922 # number of writebacks
system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36676 # number of ReadReq MSHR misses
system.cpu0.l1c.ReadReq_mshr_misses::total 36676 # number of ReadReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23894 # number of WriteReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::total 23894 # number of WriteReq MSHR misses
system.cpu0.l1c.demand_mshr_misses::cpu0 60570 # number of demand (read+write) MSHR misses
system.cpu0.l1c.demand_mshr_misses::total 60570 # number of demand (read+write) MSHR misses
system.cpu0.l1c.overall_mshr_misses::cpu0 60570 # number of overall MSHR misses
system.cpu0.l1c.overall_mshr_misses::total 60570 # number of overall MSHR misses
system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9773 # number of ReadReq MSHR uncacheable
system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9773 # number of ReadReq MSHR uncacheable
system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5450 # number of WriteReq MSHR uncacheable
system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5450 # number of WriteReq MSHR uncacheable
system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15223 # number of overall MSHR uncacheable misses
system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15223 # number of overall MSHR uncacheable misses
system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 569161577 # number of ReadReq MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_miss_latency::total 569161577 # number of ReadReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 651248476 # number of WriteReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::total 651248476 # number of WriteReq MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1220410053 # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::total 1220410053 # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1220410053 # number of overall MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::total 1220410053 # number of overall MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 638102868 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 638102868 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 843396249 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 843396249 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1481499117 # number of overall MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1481499117 # number of overall MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807361 # mshr miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807361 # mshr miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954157 # mshr miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954157 # mshr miss rate for WriteReq accesses
system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.859527 # mshr miss rate for demand accesses
system.cpu0.l1c.demand_mshr_miss_rate::total 0.859527 # mshr miss rate for demand accesses
system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.859527 # mshr miss rate for overall accesses
system.cpu0.l1c.overall_mshr_miss_rate::total 0.859527 # mshr miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 15518.638265 # average ReadReq mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 15518.638265 # average ReadReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 27255.732653 # average WriteReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 27255.732653 # average WriteReq mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 20148.754383 # average overall mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20148.754383 # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20148.754383 # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20148.754383 # average overall mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 65292.424844 # average ReadReq mshr uncacheable latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65292.424844 # average ReadReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 154751.605321 # average WriteReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154751.605321 # average WriteReq mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 97319.786967 # average overall mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 97319.786967 # average overall mshr uncacheable latency
2012-01-25 18:19:50 +01:00
system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
2015-09-25 13:27:03 +02:00
system.cpu1.num_reads 99505 # number of read accesses completed
system.cpu1.num_writes 55135 # number of write accesses completed
system.cpu1.l1c.tags.replacements 22526 # number of replacements
system.cpu1.l1c.tags.tagsinuse 393.510444 # Cycle average of tags in use
system.cpu1.l1c.tags.total_refs 13408 # Total number of references to valid blocks.
system.cpu1.l1c.tags.sampled_refs 22912 # Sample count of references to valid blocks.
system.cpu1.l1c.tags.avg_refs 0.585196 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-09-25 13:27:03 +02:00
system.cpu1.l1c.tags.occ_blocks::cpu1 393.510444 # Average occupied blocks per requestor
system.cpu1.l1c.tags.occ_percent::cpu1 0.768575 # Average percentage of cache occupancy
system.cpu1.l1c.tags.occ_percent::total 0.768575 # Average percentage of cache occupancy
2015-07-03 16:15:03 +02:00
system.cpu1.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id
2015-09-25 13:27:03 +02:00
system.cpu1.l1c.tags.age_task_id_blocks_1024::0 374 # Occupied blocks per task id
system.cpu1.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id
2015-07-03 16:15:03 +02:00
system.cpu1.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id
2015-09-25 13:27:03 +02:00
system.cpu1.l1c.tags.tag_accesses 339206 # Number of tag accesses
system.cpu1.l1c.tags.data_accesses 339206 # Number of data accesses
system.cpu1.l1c.ReadReq_hits::cpu1 8687 # number of ReadReq hits
system.cpu1.l1c.ReadReq_hits::total 8687 # number of ReadReq hits
system.cpu1.l1c.WriteReq_hits::cpu1 1167 # number of WriteReq hits
system.cpu1.l1c.WriteReq_hits::total 1167 # number of WriteReq hits
system.cpu1.l1c.demand_hits::cpu1 9854 # number of demand (read+write) hits
system.cpu1.l1c.demand_hits::total 9854 # number of demand (read+write) hits
system.cpu1.l1c.overall_hits::cpu1 9854 # number of overall hits
system.cpu1.l1c.overall_hits::total 9854 # number of overall hits
system.cpu1.l1c.ReadReq_misses::cpu1 36759 # number of ReadReq misses
system.cpu1.l1c.ReadReq_misses::total 36759 # number of ReadReq misses
system.cpu1.l1c.WriteReq_misses::cpu1 23925 # number of WriteReq misses
system.cpu1.l1c.WriteReq_misses::total 23925 # number of WriteReq misses
system.cpu1.l1c.demand_misses::cpu1 60684 # number of demand (read+write) misses
system.cpu1.l1c.demand_misses::total 60684 # number of demand (read+write) misses
system.cpu1.l1c.overall_misses::cpu1 60684 # number of overall misses
system.cpu1.l1c.overall_misses::total 60684 # number of overall misses
system.cpu1.l1c.ReadReq_miss_latency::cpu1 611192958 # number of ReadReq miss cycles
system.cpu1.l1c.ReadReq_miss_latency::total 611192958 # number of ReadReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::cpu1 677073428 # number of WriteReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::total 677073428 # number of WriteReq miss cycles
system.cpu1.l1c.demand_miss_latency::cpu1 1288266386 # number of demand (read+write) miss cycles
system.cpu1.l1c.demand_miss_latency::total 1288266386 # number of demand (read+write) miss cycles
system.cpu1.l1c.overall_miss_latency::cpu1 1288266386 # number of overall miss cycles
system.cpu1.l1c.overall_miss_latency::total 1288266386 # number of overall miss cycles
system.cpu1.l1c.ReadReq_accesses::cpu1 45446 # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.ReadReq_accesses::total 45446 # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::cpu1 25092 # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::total 25092 # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.demand_accesses::cpu1 70538 # number of demand (read+write) accesses
system.cpu1.l1c.demand_accesses::total 70538 # number of demand (read+write) accesses
system.cpu1.l1c.overall_accesses::cpu1 70538 # number of overall (read+write) accesses
system.cpu1.l1c.overall_accesses::total 70538 # number of overall (read+write) accesses
system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.808850 # miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_miss_rate::total 0.808850 # miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.953491 # miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_miss_rate::total 0.953491 # miss rate for WriteReq accesses
system.cpu1.l1c.demand_miss_rate::cpu1 0.860302 # miss rate for demand accesses
system.cpu1.l1c.demand_miss_rate::total 0.860302 # miss rate for demand accesses
system.cpu1.l1c.overall_miss_rate::cpu1 0.860302 # miss rate for overall accesses
system.cpu1.l1c.overall_miss_rate::total 0.860302 # miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16627.028972 # average ReadReq miss latency
system.cpu1.l1c.ReadReq_avg_miss_latency::total 16627.028972 # average ReadReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 28299.829801 # average WriteReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::total 28299.829801 # average WriteReq miss latency
system.cpu1.l1c.demand_avg_miss_latency::cpu1 21229.094753 # average overall miss latency
system.cpu1.l1c.demand_avg_miss_latency::total 21229.094753 # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::cpu1 21229.094753 # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::total 21229.094753 # average overall miss latency
system.cpu1.l1c.blocked_cycles::no_mshrs 746931 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-09-25 13:27:03 +02:00
system.cpu1.l1c.blocked::no_mshrs 61259 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked
2015-09-25 13:27:03 +02:00
system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.193000 # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2012-01-25 18:19:50 +01:00
system.cpu1.l1c.fast_writes 0 # number of fast writes performed
system.cpu1.l1c.cache_copies 0 # number of cache copies performed
2015-09-25 13:27:03 +02:00
system.cpu1.l1c.writebacks::writebacks 9855 # number of writebacks
system.cpu1.l1c.writebacks::total 9855 # number of writebacks
system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36759 # number of ReadReq MSHR misses
system.cpu1.l1c.ReadReq_mshr_misses::total 36759 # number of ReadReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23925 # number of WriteReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::total 23925 # number of WriteReq MSHR misses
system.cpu1.l1c.demand_mshr_misses::cpu1 60684 # number of demand (read+write) MSHR misses
system.cpu1.l1c.demand_mshr_misses::total 60684 # number of demand (read+write) MSHR misses
system.cpu1.l1c.overall_mshr_misses::cpu1 60684 # number of overall MSHR misses
system.cpu1.l1c.overall_mshr_misses::total 60684 # number of overall MSHR misses
system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9724 # number of ReadReq MSHR uncacheable
system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9724 # number of ReadReq MSHR uncacheable
system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5329 # number of WriteReq MSHR uncacheable
system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5329 # number of WriteReq MSHR uncacheable
system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15053 # number of overall MSHR uncacheable misses
system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15053 # number of overall MSHR uncacheable misses
system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 574433958 # number of ReadReq MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_miss_latency::total 574433958 # number of ReadReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 653148428 # number of WriteReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::total 653148428 # number of WriteReq MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1227582386 # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::total 1227582386 # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1227582386 # number of overall MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::total 1227582386 # number of overall MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 636306689 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 636306689 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 841464320 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 841464320 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1477771009 # number of overall MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1477771009 # number of overall MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.808850 # mshr miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.808850 # mshr miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.953491 # mshr miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.953491 # mshr miss rate for WriteReq accesses
system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.860302 # mshr miss rate for demand accesses
system.cpu1.l1c.demand_mshr_miss_rate::total 0.860302 # mshr miss rate for demand accesses
system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.860302 # mshr miss rate for overall accesses
system.cpu1.l1c.overall_mshr_miss_rate::total 0.860302 # mshr miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 15627.028972 # average ReadReq mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 15627.028972 # average ReadReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 27299.829801 # average WriteReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 27299.829801 # average WriteReq mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 20229.094753 # average overall mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::total 20229.094753 # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 20229.094753 # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::total 20229.094753 # average overall mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 65436.722439 # average ReadReq mshr uncacheable latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65436.722439 # average ReadReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 157902.856071 # average WriteReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157902.856071 # average WriteReq mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 98171.195708 # average overall mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 98171.195708 # average overall mshr uncacheable latency
2012-01-25 18:19:50 +01:00
system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
2015-09-25 13:27:03 +02:00
system.cpu2.num_reads 99747 # number of read accesses completed
system.cpu2.num_writes 54917 # number of write accesses completed
system.cpu2.l1c.tags.replacements 22440 # number of replacements
system.cpu2.l1c.tags.tagsinuse 392.958774 # Cycle average of tags in use
system.cpu2.l1c.tags.total_refs 13419 # Total number of references to valid blocks.
system.cpu2.l1c.tags.sampled_refs 22848 # Sample count of references to valid blocks.
system.cpu2.l1c.tags.avg_refs 0.587316 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-09-25 13:27:03 +02:00
system.cpu2.l1c.tags.occ_blocks::cpu2 392.958774 # Average occupied blocks per requestor
system.cpu2.l1c.tags.occ_percent::cpu2 0.767498 # Average percentage of cache occupancy
system.cpu2.l1c.tags.occ_percent::total 0.767498 # Average percentage of cache occupancy
system.cpu2.l1c.tags.occ_task_id_blocks::1024 408 # Occupied blocks per task id
system.cpu2.l1c.tags.age_task_id_blocks_1024::0 391 # Occupied blocks per task id
system.cpu2.l1c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id
system.cpu2.l1c.tags.occ_task_id_percent::1024 0.796875 # Percentage of cache occupancy per task id
system.cpu2.l1c.tags.tag_accesses 337058 # Number of tag accesses
system.cpu2.l1c.tags.data_accesses 337058 # Number of data accesses
system.cpu2.l1c.ReadReq_hits::cpu2 8566 # number of ReadReq hits
system.cpu2.l1c.ReadReq_hits::total 8566 # number of ReadReq hits
system.cpu2.l1c.WriteReq_hits::cpu2 1197 # number of WriteReq hits
system.cpu2.l1c.WriteReq_hits::total 1197 # number of WriteReq hits
system.cpu2.l1c.demand_hits::cpu2 9763 # number of demand (read+write) hits
system.cpu2.l1c.demand_hits::total 9763 # number of demand (read+write) hits
system.cpu2.l1c.overall_hits::cpu2 9763 # number of overall hits
system.cpu2.l1c.overall_hits::total 9763 # number of overall hits
system.cpu2.l1c.ReadReq_misses::cpu2 36656 # number of ReadReq misses
system.cpu2.l1c.ReadReq_misses::total 36656 # number of ReadReq misses
system.cpu2.l1c.WriteReq_misses::cpu2 23689 # number of WriteReq misses
system.cpu2.l1c.WriteReq_misses::total 23689 # number of WriteReq misses
system.cpu2.l1c.demand_misses::cpu2 60345 # number of demand (read+write) misses
system.cpu2.l1c.demand_misses::total 60345 # number of demand (read+write) misses
system.cpu2.l1c.overall_misses::cpu2 60345 # number of overall misses
system.cpu2.l1c.overall_misses::total 60345 # number of overall misses
system.cpu2.l1c.ReadReq_miss_latency::cpu2 609273651 # number of ReadReq miss cycles
system.cpu2.l1c.ReadReq_miss_latency::total 609273651 # number of ReadReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::cpu2 671190571 # number of WriteReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::total 671190571 # number of WriteReq miss cycles
system.cpu2.l1c.demand_miss_latency::cpu2 1280464222 # number of demand (read+write) miss cycles
system.cpu2.l1c.demand_miss_latency::total 1280464222 # number of demand (read+write) miss cycles
system.cpu2.l1c.overall_miss_latency::cpu2 1280464222 # number of overall miss cycles
system.cpu2.l1c.overall_miss_latency::total 1280464222 # number of overall miss cycles
system.cpu2.l1c.ReadReq_accesses::cpu2 45222 # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.ReadReq_accesses::total 45222 # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::cpu2 24886 # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::total 24886 # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.demand_accesses::cpu2 70108 # number of demand (read+write) accesses
system.cpu2.l1c.demand_accesses::total 70108 # number of demand (read+write) accesses
system.cpu2.l1c.overall_accesses::cpu2 70108 # number of overall (read+write) accesses
system.cpu2.l1c.overall_accesses::total 70108 # number of overall (read+write) accesses
system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.810579 # miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_miss_rate::total 0.810579 # miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.951901 # miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_miss_rate::total 0.951901 # miss rate for WriteReq accesses
system.cpu2.l1c.demand_miss_rate::cpu2 0.860743 # miss rate for demand accesses
system.cpu2.l1c.demand_miss_rate::total 0.860743 # miss rate for demand accesses
system.cpu2.l1c.overall_miss_rate::cpu2 0.860743 # miss rate for overall accesses
system.cpu2.l1c.overall_miss_rate::total 0.860743 # miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16621.389431 # average ReadReq miss latency
system.cpu2.l1c.ReadReq_avg_miss_latency::total 16621.389431 # average ReadReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 28333.427793 # average WriteReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::total 28333.427793 # average WriteReq miss latency
system.cpu2.l1c.demand_avg_miss_latency::cpu2 21219.060767 # average overall miss latency
system.cpu2.l1c.demand_avg_miss_latency::total 21219.060767 # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::cpu2 21219.060767 # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::total 21219.060767 # average overall miss latency
system.cpu2.l1c.blocked_cycles::no_mshrs 742867 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-09-25 13:27:03 +02:00
system.cpu2.l1c.blocked::no_mshrs 60931 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked
2015-09-25 13:27:03 +02:00
system.cpu2.l1c.avg_blocked_cycles::no_mshrs 12.191938 # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2012-01-25 18:19:50 +01:00
system.cpu2.l1c.fast_writes 0 # number of fast writes performed
system.cpu2.l1c.cache_copies 0 # number of cache copies performed
2015-09-25 13:27:03 +02:00
system.cpu2.l1c.writebacks::writebacks 9836 # number of writebacks
system.cpu2.l1c.writebacks::total 9836 # number of writebacks
system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36656 # number of ReadReq MSHR misses
system.cpu2.l1c.ReadReq_mshr_misses::total 36656 # number of ReadReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23689 # number of WriteReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::total 23689 # number of WriteReq MSHR misses
system.cpu2.l1c.demand_mshr_misses::cpu2 60345 # number of demand (read+write) MSHR misses
system.cpu2.l1c.demand_mshr_misses::total 60345 # number of demand (read+write) MSHR misses
system.cpu2.l1c.overall_mshr_misses::cpu2 60345 # number of overall MSHR misses
system.cpu2.l1c.overall_mshr_misses::total 60345 # number of overall MSHR misses
system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9760 # number of ReadReq MSHR uncacheable
system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9760 # number of ReadReq MSHR uncacheable
system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5535 # number of WriteReq MSHR uncacheable
system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5535 # number of WriteReq MSHR uncacheable
system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15295 # number of overall MSHR uncacheable misses
system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15295 # number of overall MSHR uncacheable misses
system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 572617651 # number of ReadReq MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_miss_latency::total 572617651 # number of ReadReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 647503571 # number of WriteReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::total 647503571 # number of WriteReq MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1220121222 # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::total 1220121222 # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1220121222 # number of overall MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::total 1220121222 # number of overall MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 638440786 # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 638440786 # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 853548639 # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 853548639 # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1491989425 # number of overall MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1491989425 # number of overall MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.810579 # mshr miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.810579 # mshr miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.951901 # mshr miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.951901 # mshr miss rate for WriteReq accesses
system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.860743 # mshr miss rate for demand accesses
system.cpu2.l1c.demand_mshr_miss_rate::total 0.860743 # mshr miss rate for demand accesses
system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.860743 # mshr miss rate for overall accesses
system.cpu2.l1c.overall_mshr_miss_rate::total 0.860743 # mshr miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 15621.389431 # average ReadReq mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 15621.389431 # average ReadReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 27333.512221 # average WriteReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 27333.512221 # average WriteReq mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 20219.093910 # average overall mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::total 20219.093910 # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 20219.093910 # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::total 20219.093910 # average overall mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 65414.014959 # average ReadReq mshr uncacheable latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65414.014959 # average ReadReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 154209.329539 # average WriteReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154209.329539 # average WriteReq mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 97547.526970 # average overall mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 97547.526970 # average overall mshr uncacheable latency
2012-01-25 18:19:50 +01:00
system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
2015-09-25 13:27:03 +02:00
system.cpu3.num_reads 98987 # number of read accesses completed
system.cpu3.num_writes 55311 # number of write accesses completed
system.cpu3.l1c.tags.replacements 22430 # number of replacements
system.cpu3.l1c.tags.tagsinuse 392.656254 # Cycle average of tags in use
system.cpu3.l1c.tags.total_refs 13364 # Total number of references to valid blocks.
system.cpu3.l1c.tags.sampled_refs 22840 # Sample count of references to valid blocks.
system.cpu3.l1c.tags.avg_refs 0.585114 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-09-25 13:27:03 +02:00
system.cpu3.l1c.tags.occ_blocks::cpu3 392.656254 # Average occupied blocks per requestor
system.cpu3.l1c.tags.occ_percent::cpu3 0.766907 # Average percentage of cache occupancy
system.cpu3.l1c.tags.occ_percent::total 0.766907 # Average percentage of cache occupancy
system.cpu3.l1c.tags.occ_task_id_blocks::1024 410 # Occupied blocks per task id
system.cpu3.l1c.tags.age_task_id_blocks_1024::0 401 # Occupied blocks per task id
system.cpu3.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id
system.cpu3.l1c.tags.occ_task_id_percent::1024 0.800781 # Percentage of cache occupancy per task id
system.cpu3.l1c.tags.tag_accesses 337200 # Number of tag accesses
system.cpu3.l1c.tags.data_accesses 337200 # Number of data accesses
system.cpu3.l1c.ReadReq_hits::cpu3 8601 # number of ReadReq hits
system.cpu3.l1c.ReadReq_hits::total 8601 # number of ReadReq hits
system.cpu3.l1c.WriteReq_hits::cpu3 1133 # number of WriteReq hits
system.cpu3.l1c.WriteReq_hits::total 1133 # number of WriteReq hits
system.cpu3.l1c.demand_hits::cpu3 9734 # number of demand (read+write) hits
system.cpu3.l1c.demand_hits::total 9734 # number of demand (read+write) hits
system.cpu3.l1c.overall_hits::cpu3 9734 # number of overall hits
system.cpu3.l1c.overall_hits::total 9734 # number of overall hits
system.cpu3.l1c.ReadReq_misses::cpu3 36299 # number of ReadReq misses
system.cpu3.l1c.ReadReq_misses::total 36299 # number of ReadReq misses
system.cpu3.l1c.WriteReq_misses::cpu3 24092 # number of WriteReq misses
system.cpu3.l1c.WriteReq_misses::total 24092 # number of WriteReq misses
system.cpu3.l1c.demand_misses::cpu3 60391 # number of demand (read+write) misses
system.cpu3.l1c.demand_misses::total 60391 # number of demand (read+write) misses
system.cpu3.l1c.overall_misses::cpu3 60391 # number of overall misses
system.cpu3.l1c.overall_misses::total 60391 # number of overall misses
system.cpu3.l1c.ReadReq_miss_latency::cpu3 601442350 # number of ReadReq miss cycles
system.cpu3.l1c.ReadReq_miss_latency::total 601442350 # number of ReadReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::cpu3 682370713 # number of WriteReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::total 682370713 # number of WriteReq miss cycles
system.cpu3.l1c.demand_miss_latency::cpu3 1283813063 # number of demand (read+write) miss cycles
system.cpu3.l1c.demand_miss_latency::total 1283813063 # number of demand (read+write) miss cycles
system.cpu3.l1c.overall_miss_latency::cpu3 1283813063 # number of overall miss cycles
system.cpu3.l1c.overall_miss_latency::total 1283813063 # number of overall miss cycles
system.cpu3.l1c.ReadReq_accesses::cpu3 44900 # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.ReadReq_accesses::total 44900 # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::cpu3 25225 # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::total 25225 # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.demand_accesses::cpu3 70125 # number of demand (read+write) accesses
system.cpu3.l1c.demand_accesses::total 70125 # number of demand (read+write) accesses
system.cpu3.l1c.overall_accesses::cpu3 70125 # number of overall (read+write) accesses
system.cpu3.l1c.overall_accesses::total 70125 # number of overall (read+write) accesses
system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.808441 # miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_miss_rate::total 0.808441 # miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955084 # miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_miss_rate::total 0.955084 # miss rate for WriteReq accesses
system.cpu3.l1c.demand_miss_rate::cpu3 0.861191 # miss rate for demand accesses
system.cpu3.l1c.demand_miss_rate::total 0.861191 # miss rate for demand accesses
system.cpu3.l1c.overall_miss_rate::cpu3 0.861191 # miss rate for overall accesses
system.cpu3.l1c.overall_miss_rate::total 0.861191 # miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16569.116229 # average ReadReq miss latency
system.cpu3.l1c.ReadReq_avg_miss_latency::total 16569.116229 # average ReadReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 28323.539474 # average WriteReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::total 28323.539474 # average WriteReq miss latency
system.cpu3.l1c.demand_avg_miss_latency::cpu3 21258.350797 # average overall miss latency
system.cpu3.l1c.demand_avg_miss_latency::total 21258.350797 # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::cpu3 21258.350797 # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::total 21258.350797 # average overall miss latency
system.cpu3.l1c.blocked_cycles::no_mshrs 746578 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-09-25 13:27:03 +02:00
system.cpu3.l1c.blocked::no_mshrs 60969 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked
2015-09-25 13:27:03 +02:00
system.cpu3.l1c.avg_blocked_cycles::no_mshrs 12.245207 # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2012-01-25 18:19:50 +01:00
system.cpu3.l1c.fast_writes 0 # number of fast writes performed
system.cpu3.l1c.cache_copies 0 # number of cache copies performed
2015-09-25 13:27:03 +02:00
system.cpu3.l1c.writebacks::writebacks 9891 # number of writebacks
system.cpu3.l1c.writebacks::total 9891 # number of writebacks
system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36299 # number of ReadReq MSHR misses
system.cpu3.l1c.ReadReq_mshr_misses::total 36299 # number of ReadReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::cpu3 24092 # number of WriteReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::total 24092 # number of WriteReq MSHR misses
system.cpu3.l1c.demand_mshr_misses::cpu3 60391 # number of demand (read+write) MSHR misses
system.cpu3.l1c.demand_mshr_misses::total 60391 # number of demand (read+write) MSHR misses
system.cpu3.l1c.overall_mshr_misses::cpu3 60391 # number of overall MSHR misses
system.cpu3.l1c.overall_mshr_misses::total 60391 # number of overall MSHR misses
system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9771 # number of ReadReq MSHR uncacheable
system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9771 # number of ReadReq MSHR uncacheable
2015-07-03 16:15:03 +02:00
system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5455 # number of WriteReq MSHR uncacheable
system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5455 # number of WriteReq MSHR uncacheable
2015-09-25 13:27:03 +02:00
system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15226 # number of overall MSHR uncacheable misses
system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15226 # number of overall MSHR uncacheable misses
system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 565143350 # number of ReadReq MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_miss_latency::total 565143350 # number of ReadReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 658281713 # number of WriteReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::total 658281713 # number of WriteReq MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1223425063 # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::total 1223425063 # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1223425063 # number of overall MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::total 1223425063 # number of overall MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 638944774 # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 638944774 # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 852450723 # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 852450723 # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1491395497 # number of overall MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1491395497 # number of overall MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.808441 # mshr miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.808441 # mshr miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955084 # mshr miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955084 # mshr miss rate for WriteReq accesses
system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.861191 # mshr miss rate for demand accesses
system.cpu3.l1c.demand_mshr_miss_rate::total 0.861191 # mshr miss rate for demand accesses
system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.861191 # mshr miss rate for overall accesses
system.cpu3.l1c.overall_mshr_miss_rate::total 0.861191 # mshr miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 15569.116229 # average ReadReq mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 15569.116229 # average ReadReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 27323.663996 # average WriteReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 27323.663996 # average WriteReq mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 20258.400474 # average overall mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::total 20258.400474 # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 20258.400474 # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::total 20258.400474 # average overall mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 65391.953127 # average ReadReq mshr uncacheable latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65391.953127 # average ReadReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 156269.610082 # average WriteReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156269.610082 # average WriteReq mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 97950.577762 # average overall mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 97950.577762 # average overall mshr uncacheable latency
2012-01-25 18:19:50 +01:00
system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
2015-07-03 16:15:03 +02:00
system.cpu4.num_reads 100000 # number of read accesses completed
2015-09-25 13:27:03 +02:00
system.cpu4.num_writes 54901 # number of write accesses completed
system.cpu4.l1c.tags.replacements 22108 # number of replacements
system.cpu4.l1c.tags.tagsinuse 392.325245 # Cycle average of tags in use
system.cpu4.l1c.tags.total_refs 13548 # Total number of references to valid blocks.
system.cpu4.l1c.tags.sampled_refs 22499 # Sample count of references to valid blocks.
system.cpu4.l1c.tags.avg_refs 0.602160 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-09-25 13:27:03 +02:00
system.cpu4.l1c.tags.occ_blocks::cpu4 392.325245 # Average occupied blocks per requestor
system.cpu4.l1c.tags.occ_percent::cpu4 0.766260 # Average percentage of cache occupancy
system.cpu4.l1c.tags.occ_percent::total 0.766260 # Average percentage of cache occupancy
system.cpu4.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id
system.cpu4.l1c.tags.age_task_id_blocks_1024::0 384 # Occupied blocks per task id
system.cpu4.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id
system.cpu4.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id
system.cpu4.l1c.tags.tag_accesses 338175 # Number of tag accesses
system.cpu4.l1c.tags.data_accesses 338175 # Number of data accesses
system.cpu4.l1c.ReadReq_hits::cpu4 8785 # number of ReadReq hits
system.cpu4.l1c.ReadReq_hits::total 8785 # number of ReadReq hits
system.cpu4.l1c.WriteReq_hits::cpu4 1156 # number of WriteReq hits
system.cpu4.l1c.WriteReq_hits::total 1156 # number of WriteReq hits
system.cpu4.l1c.demand_hits::cpu4 9941 # number of demand (read+write) hits
system.cpu4.l1c.demand_hits::total 9941 # number of demand (read+write) hits
system.cpu4.l1c.overall_hits::cpu4 9941 # number of overall hits
system.cpu4.l1c.overall_hits::total 9941 # number of overall hits
system.cpu4.l1c.ReadReq_misses::cpu4 36616 # number of ReadReq misses
system.cpu4.l1c.ReadReq_misses::total 36616 # number of ReadReq misses
system.cpu4.l1c.WriteReq_misses::cpu4 23803 # number of WriteReq misses
system.cpu4.l1c.WriteReq_misses::total 23803 # number of WriteReq misses
system.cpu4.l1c.demand_misses::cpu4 60419 # number of demand (read+write) misses
system.cpu4.l1c.demand_misses::total 60419 # number of demand (read+write) misses
system.cpu4.l1c.overall_misses::cpu4 60419 # number of overall misses
system.cpu4.l1c.overall_misses::total 60419 # number of overall misses
system.cpu4.l1c.ReadReq_miss_latency::cpu4 606172682 # number of ReadReq miss cycles
system.cpu4.l1c.ReadReq_miss_latency::total 606172682 # number of ReadReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::cpu4 676089465 # number of WriteReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::total 676089465 # number of WriteReq miss cycles
system.cpu4.l1c.demand_miss_latency::cpu4 1282262147 # number of demand (read+write) miss cycles
system.cpu4.l1c.demand_miss_latency::total 1282262147 # number of demand (read+write) miss cycles
system.cpu4.l1c.overall_miss_latency::cpu4 1282262147 # number of overall miss cycles
system.cpu4.l1c.overall_miss_latency::total 1282262147 # number of overall miss cycles
system.cpu4.l1c.ReadReq_accesses::cpu4 45401 # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.ReadReq_accesses::total 45401 # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::cpu4 24959 # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::total 24959 # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.demand_accesses::cpu4 70360 # number of demand (read+write) accesses
system.cpu4.l1c.demand_accesses::total 70360 # number of demand (read+write) accesses
system.cpu4.l1c.overall_accesses::cpu4 70360 # number of overall (read+write) accesses
system.cpu4.l1c.overall_accesses::total 70360 # number of overall (read+write) accesses
system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.806502 # miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_miss_rate::total 0.806502 # miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953684 # miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_miss_rate::total 0.953684 # miss rate for WriteReq accesses
system.cpu4.l1c.demand_miss_rate::cpu4 0.858712 # miss rate for demand accesses
system.cpu4.l1c.demand_miss_rate::total 0.858712 # miss rate for demand accesses
system.cpu4.l1c.overall_miss_rate::cpu4 0.858712 # miss rate for overall accesses
system.cpu4.l1c.overall_miss_rate::total 0.858712 # miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16554.858040 # average ReadReq miss latency
system.cpu4.l1c.ReadReq_avg_miss_latency::total 16554.858040 # average ReadReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 28403.540100 # average WriteReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::total 28403.540100 # average WriteReq miss latency
system.cpu4.l1c.demand_avg_miss_latency::cpu4 21222.829689 # average overall miss latency
system.cpu4.l1c.demand_avg_miss_latency::total 21222.829689 # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::cpu4 21222.829689 # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::total 21222.829689 # average overall miss latency
system.cpu4.l1c.blocked_cycles::no_mshrs 752786 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-09-25 13:27:03 +02:00
system.cpu4.l1c.blocked::no_mshrs 61311 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked
2015-09-25 13:27:03 +02:00
system.cpu4.l1c.avg_blocked_cycles::no_mshrs 12.278156 # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2012-01-25 18:19:50 +01:00
system.cpu4.l1c.fast_writes 0 # number of fast writes performed
system.cpu4.l1c.cache_copies 0 # number of cache copies performed
2015-09-25 13:27:03 +02:00
system.cpu4.l1c.writebacks::writebacks 9736 # number of writebacks
system.cpu4.l1c.writebacks::total 9736 # number of writebacks
system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36616 # number of ReadReq MSHR misses
system.cpu4.l1c.ReadReq_mshr_misses::total 36616 # number of ReadReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23803 # number of WriteReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::total 23803 # number of WriteReq MSHR misses
system.cpu4.l1c.demand_mshr_misses::cpu4 60419 # number of demand (read+write) MSHR misses
system.cpu4.l1c.demand_mshr_misses::total 60419 # number of demand (read+write) MSHR misses
system.cpu4.l1c.overall_mshr_misses::cpu4 60419 # number of overall MSHR misses
system.cpu4.l1c.overall_mshr_misses::total 60419 # number of overall MSHR misses
system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9898 # number of ReadReq MSHR uncacheable
system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9898 # number of ReadReq MSHR uncacheable
system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5382 # number of WriteReq MSHR uncacheable
system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5382 # number of WriteReq MSHR uncacheable
system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15280 # number of overall MSHR uncacheable misses
system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15280 # number of overall MSHR uncacheable misses
system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 569559682 # number of ReadReq MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_miss_latency::total 569559682 # number of ReadReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 652287465 # number of WriteReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::total 652287465 # number of WriteReq MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1221847147 # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::total 1221847147 # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1221847147 # number of overall MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::total 1221847147 # number of overall MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 646717625 # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 646717625 # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 846861232 # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 846861232 # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1493578857 # number of overall MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1493578857 # number of overall MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.806502 # mshr miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.806502 # mshr miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953684 # mshr miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953684 # mshr miss rate for WriteReq accesses
system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.858712 # mshr miss rate for demand accesses
system.cpu4.l1c.demand_mshr_miss_rate::total 0.858712 # mshr miss rate for demand accesses
system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.858712 # mshr miss rate for overall accesses
system.cpu4.l1c.overall_mshr_miss_rate::total 0.858712 # mshr miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 15554.939972 # average ReadReq mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 15554.939972 # average ReadReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 27403.582111 # average WriteReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 27403.582111 # average WriteReq mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 20222.895894 # average overall mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::total 20222.895894 # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 20222.895894 # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::total 20222.895894 # average overall mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 65338.212265 # average ReadReq mshr uncacheable latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65338.212265 # average ReadReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 157350.656262 # average WriteReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157350.656262 # average WriteReq mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 97747.307395 # average overall mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 97747.307395 # average overall mshr uncacheable latency
2012-01-25 18:19:50 +01:00
system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
2015-09-25 13:27:03 +02:00
system.cpu5.num_reads 99420 # number of read accesses completed
system.cpu5.num_writes 55050 # number of write accesses completed
system.cpu5.l1c.tags.replacements 22127 # number of replacements
system.cpu5.l1c.tags.tagsinuse 390.223258 # Cycle average of tags in use
system.cpu5.l1c.tags.total_refs 13616 # Total number of references to valid blocks.
system.cpu5.l1c.tags.sampled_refs 22515 # Sample count of references to valid blocks.
system.cpu5.l1c.tags.avg_refs 0.604752 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-09-25 13:27:03 +02:00
system.cpu5.l1c.tags.occ_blocks::cpu5 390.223258 # Average occupied blocks per requestor
system.cpu5.l1c.tags.occ_percent::cpu5 0.762155 # Average percentage of cache occupancy
system.cpu5.l1c.tags.occ_percent::total 0.762155 # Average percentage of cache occupancy
system.cpu5.l1c.tags.occ_task_id_blocks::1024 388 # Occupied blocks per task id
system.cpu5.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id
2015-07-03 16:15:03 +02:00
system.cpu5.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id
2015-09-25 13:27:03 +02:00
system.cpu5.l1c.tags.occ_task_id_percent::1024 0.757812 # Percentage of cache occupancy per task id
system.cpu5.l1c.tags.tag_accesses 338569 # Number of tag accesses
system.cpu5.l1c.tags.data_accesses 338569 # Number of data accesses
system.cpu5.l1c.ReadReq_hits::cpu5 8830 # number of ReadReq hits
system.cpu5.l1c.ReadReq_hits::total 8830 # number of ReadReq hits
system.cpu5.l1c.WriteReq_hits::cpu5 1218 # number of WriteReq hits
system.cpu5.l1c.WriteReq_hits::total 1218 # number of WriteReq hits
system.cpu5.l1c.demand_hits::cpu5 10048 # number of demand (read+write) hits
system.cpu5.l1c.demand_hits::total 10048 # number of demand (read+write) hits
system.cpu5.l1c.overall_hits::cpu5 10048 # number of overall hits
system.cpu5.l1c.overall_hits::total 10048 # number of overall hits
system.cpu5.l1c.ReadReq_misses::cpu5 36409 # number of ReadReq misses
system.cpu5.l1c.ReadReq_misses::total 36409 # number of ReadReq misses
system.cpu5.l1c.WriteReq_misses::cpu5 23995 # number of WriteReq misses
system.cpu5.l1c.WriteReq_misses::total 23995 # number of WriteReq misses
system.cpu5.l1c.demand_misses::cpu5 60404 # number of demand (read+write) misses
system.cpu5.l1c.demand_misses::total 60404 # number of demand (read+write) misses
system.cpu5.l1c.overall_misses::cpu5 60404 # number of overall misses
system.cpu5.l1c.overall_misses::total 60404 # number of overall misses
system.cpu5.l1c.ReadReq_miss_latency::cpu5 603629256 # number of ReadReq miss cycles
system.cpu5.l1c.ReadReq_miss_latency::total 603629256 # number of ReadReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::cpu5 675904407 # number of WriteReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::total 675904407 # number of WriteReq miss cycles
system.cpu5.l1c.demand_miss_latency::cpu5 1279533663 # number of demand (read+write) miss cycles
system.cpu5.l1c.demand_miss_latency::total 1279533663 # number of demand (read+write) miss cycles
system.cpu5.l1c.overall_miss_latency::cpu5 1279533663 # number of overall miss cycles
system.cpu5.l1c.overall_miss_latency::total 1279533663 # number of overall miss cycles
system.cpu5.l1c.ReadReq_accesses::cpu5 45239 # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.ReadReq_accesses::total 45239 # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::cpu5 25213 # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::total 25213 # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.demand_accesses::cpu5 70452 # number of demand (read+write) accesses
system.cpu5.l1c.demand_accesses::total 70452 # number of demand (read+write) accesses
system.cpu5.l1c.overall_accesses::cpu5 70452 # number of overall (read+write) accesses
system.cpu5.l1c.overall_accesses::total 70452 # number of overall (read+write) accesses
system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.804814 # miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_miss_rate::total 0.804814 # miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.951692 # miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_miss_rate::total 0.951692 # miss rate for WriteReq accesses
system.cpu5.l1c.demand_miss_rate::cpu5 0.857378 # miss rate for demand accesses
system.cpu5.l1c.demand_miss_rate::total 0.857378 # miss rate for demand accesses
system.cpu5.l1c.overall_miss_rate::cpu5 0.857378 # miss rate for overall accesses
system.cpu5.l1c.overall_miss_rate::total 0.857378 # miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16579.122085 # average ReadReq miss latency
system.cpu5.l1c.ReadReq_avg_miss_latency::total 16579.122085 # average ReadReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 28168.552073 # average WriteReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::total 28168.552073 # average WriteReq miss latency
system.cpu5.l1c.demand_avg_miss_latency::cpu5 21182.929326 # average overall miss latency
system.cpu5.l1c.demand_avg_miss_latency::total 21182.929326 # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::cpu5 21182.929326 # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::total 21182.929326 # average overall miss latency
system.cpu5.l1c.blocked_cycles::no_mshrs 750665 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-09-25 13:27:03 +02:00
system.cpu5.l1c.blocked::no_mshrs 61291 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked
2015-09-25 13:27:03 +02:00
system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.247557 # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2012-01-25 18:19:50 +01:00
system.cpu5.l1c.fast_writes 0 # number of fast writes performed
system.cpu5.l1c.cache_copies 0 # number of cache copies performed
2015-09-25 13:27:03 +02:00
system.cpu5.l1c.writebacks::writebacks 9761 # number of writebacks
system.cpu5.l1c.writebacks::total 9761 # number of writebacks
system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36409 # number of ReadReq MSHR misses
system.cpu5.l1c.ReadReq_mshr_misses::total 36409 # number of ReadReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23995 # number of WriteReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::total 23995 # number of WriteReq MSHR misses
system.cpu5.l1c.demand_mshr_misses::cpu5 60404 # number of demand (read+write) MSHR misses
system.cpu5.l1c.demand_mshr_misses::total 60404 # number of demand (read+write) MSHR misses
system.cpu5.l1c.overall_mshr_misses::cpu5 60404 # number of overall MSHR misses
system.cpu5.l1c.overall_mshr_misses::total 60404 # number of overall MSHR misses
system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9891 # number of ReadReq MSHR uncacheable
system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9891 # number of ReadReq MSHR uncacheable
system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5483 # number of WriteReq MSHR uncacheable
system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5483 # number of WriteReq MSHR uncacheable
system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15374 # number of overall MSHR uncacheable misses
system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15374 # number of overall MSHR uncacheable misses
system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 567222256 # number of ReadReq MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_miss_latency::total 567222256 # number of ReadReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 651909407 # number of WriteReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::total 651909407 # number of WriteReq MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1219131663 # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::total 1219131663 # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1219131663 # number of overall MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::total 1219131663 # number of overall MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 648234678 # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 648234678 # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 860459231 # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 860459231 # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1508693909 # number of overall MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1508693909 # number of overall MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.804814 # mshr miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.804814 # mshr miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.951692 # mshr miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.951692 # mshr miss rate for WriteReq accesses
system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.857378 # mshr miss rate for demand accesses
system.cpu5.l1c.demand_mshr_miss_rate::total 0.857378 # mshr miss rate for demand accesses
system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.857378 # mshr miss rate for overall accesses
system.cpu5.l1c.overall_mshr_miss_rate::total 0.857378 # mshr miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 15579.177017 # average ReadReq mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 15579.177017 # average ReadReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 27168.552073 # average WriteReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 27168.552073 # average WriteReq mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 20182.962436 # average overall mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::total 20182.962436 # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 20182.962436 # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::total 20182.962436 # average overall mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 65537.830149 # average ReadReq mshr uncacheable latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65537.830149 # average ReadReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 156932.196061 # average WriteReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156932.196061 # average WriteReq mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 98132.815728 # average overall mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 98132.815728 # average overall mshr uncacheable latency
2012-01-25 18:19:50 +01:00
system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
2015-09-25 13:27:03 +02:00
system.cpu6.num_reads 99130 # number of read accesses completed
system.cpu6.num_writes 55082 # number of write accesses completed
system.cpu6.l1c.tags.replacements 22211 # number of replacements
system.cpu6.l1c.tags.tagsinuse 391.729996 # Cycle average of tags in use
system.cpu6.l1c.tags.total_refs 13451 # Total number of references to valid blocks.
system.cpu6.l1c.tags.sampled_refs 22620 # Sample count of references to valid blocks.
system.cpu6.l1c.tags.avg_refs 0.594651 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-09-25 13:27:03 +02:00
system.cpu6.l1c.tags.occ_blocks::cpu6 391.729996 # Average occupied blocks per requestor
system.cpu6.l1c.tags.occ_percent::cpu6 0.765098 # Average percentage of cache occupancy
system.cpu6.l1c.tags.occ_percent::total 0.765098 # Average percentage of cache occupancy
system.cpu6.l1c.tags.occ_task_id_blocks::1024 409 # Occupied blocks per task id
system.cpu6.l1c.tags.age_task_id_blocks_1024::0 394 # Occupied blocks per task id
system.cpu6.l1c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id
system.cpu6.l1c.tags.occ_task_id_percent::1024 0.798828 # Percentage of cache occupancy per task id
system.cpu6.l1c.tags.tag_accesses 338357 # Number of tag accesses
system.cpu6.l1c.tags.data_accesses 338357 # Number of data accesses
system.cpu6.l1c.ReadReq_hits::cpu6 8673 # number of ReadReq hits
system.cpu6.l1c.ReadReq_hits::total 8673 # number of ReadReq hits
system.cpu6.l1c.WriteReq_hits::cpu6 1155 # number of WriteReq hits
system.cpu6.l1c.WriteReq_hits::total 1155 # number of WriteReq hits
system.cpu6.l1c.demand_hits::cpu6 9828 # number of demand (read+write) hits
system.cpu6.l1c.demand_hits::total 9828 # number of demand (read+write) hits
system.cpu6.l1c.overall_hits::cpu6 9828 # number of overall hits
system.cpu6.l1c.overall_hits::total 9828 # number of overall hits
system.cpu6.l1c.ReadReq_misses::cpu6 36524 # number of ReadReq misses
system.cpu6.l1c.ReadReq_misses::total 36524 # number of ReadReq misses
system.cpu6.l1c.WriteReq_misses::cpu6 24020 # number of WriteReq misses
system.cpu6.l1c.WriteReq_misses::total 24020 # number of WriteReq misses
system.cpu6.l1c.demand_misses::cpu6 60544 # number of demand (read+write) misses
system.cpu6.l1c.demand_misses::total 60544 # number of demand (read+write) misses
system.cpu6.l1c.overall_misses::cpu6 60544 # number of overall misses
system.cpu6.l1c.overall_misses::total 60544 # number of overall misses
system.cpu6.l1c.ReadReq_miss_latency::cpu6 604615121 # number of ReadReq miss cycles
system.cpu6.l1c.ReadReq_miss_latency::total 604615121 # number of ReadReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::cpu6 676363327 # number of WriteReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::total 676363327 # number of WriteReq miss cycles
system.cpu6.l1c.demand_miss_latency::cpu6 1280978448 # number of demand (read+write) miss cycles
system.cpu6.l1c.demand_miss_latency::total 1280978448 # number of demand (read+write) miss cycles
system.cpu6.l1c.overall_miss_latency::cpu6 1280978448 # number of overall miss cycles
system.cpu6.l1c.overall_miss_latency::total 1280978448 # number of overall miss cycles
system.cpu6.l1c.ReadReq_accesses::cpu6 45197 # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.ReadReq_accesses::total 45197 # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::cpu6 25175 # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::total 25175 # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.demand_accesses::cpu6 70372 # number of demand (read+write) accesses
system.cpu6.l1c.demand_accesses::total 70372 # number of demand (read+write) accesses
system.cpu6.l1c.overall_accesses::cpu6 70372 # number of overall (read+write) accesses
system.cpu6.l1c.overall_accesses::total 70372 # number of overall (read+write) accesses
system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.808107 # miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_miss_rate::total 0.808107 # miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954121 # miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_miss_rate::total 0.954121 # miss rate for WriteReq accesses
system.cpu6.l1c.demand_miss_rate::cpu6 0.860342 # miss rate for demand accesses
system.cpu6.l1c.demand_miss_rate::total 0.860342 # miss rate for demand accesses
system.cpu6.l1c.overall_miss_rate::cpu6 0.860342 # miss rate for overall accesses
system.cpu6.l1c.overall_miss_rate::total 0.860342 # miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16553.913071 # average ReadReq miss latency
system.cpu6.l1c.ReadReq_avg_miss_latency::total 16553.913071 # average ReadReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 28158.340008 # average WriteReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::total 28158.340008 # average WriteReq miss latency
system.cpu6.l1c.demand_avg_miss_latency::cpu6 21157.809989 # average overall miss latency
system.cpu6.l1c.demand_avg_miss_latency::total 21157.809989 # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::cpu6 21157.809989 # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::total 21157.809989 # average overall miss latency
system.cpu6.l1c.blocked_cycles::no_mshrs 747919 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-09-25 13:27:03 +02:00
system.cpu6.l1c.blocked::no_mshrs 61299 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked
2015-09-25 13:27:03 +02:00
system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.201162 # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2012-01-25 18:19:50 +01:00
system.cpu6.l1c.fast_writes 0 # number of fast writes performed
system.cpu6.l1c.cache_copies 0 # number of cache copies performed
2015-09-25 13:27:03 +02:00
system.cpu6.l1c.writebacks::writebacks 9790 # number of writebacks
system.cpu6.l1c.writebacks::total 9790 # number of writebacks
system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36524 # number of ReadReq MSHR misses
system.cpu6.l1c.ReadReq_mshr_misses::total 36524 # number of ReadReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::cpu6 24020 # number of WriteReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::total 24020 # number of WriteReq MSHR misses
system.cpu6.l1c.demand_mshr_misses::cpu6 60544 # number of demand (read+write) MSHR misses
system.cpu6.l1c.demand_mshr_misses::total 60544 # number of demand (read+write) MSHR misses
system.cpu6.l1c.overall_mshr_misses::cpu6 60544 # number of overall MSHR misses
system.cpu6.l1c.overall_mshr_misses::total 60544 # number of overall MSHR misses
system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9846 # number of ReadReq MSHR uncacheable
system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9846 # number of ReadReq MSHR uncacheable
system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5510 # number of WriteReq MSHR uncacheable
system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5510 # number of WriteReq MSHR uncacheable
system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15356 # number of overall MSHR uncacheable misses
system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15356 # number of overall MSHR uncacheable misses
system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 568091121 # number of ReadReq MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_miss_latency::total 568091121 # number of ReadReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 652345327 # number of WriteReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::total 652345327 # number of WriteReq MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1220436448 # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::total 1220436448 # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1220436448 # number of overall MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::total 1220436448 # number of overall MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 644948195 # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 644948195 # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 860679200 # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 860679200 # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1505627395 # number of overall MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1505627395 # number of overall MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.808107 # mshr miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.808107 # mshr miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954121 # mshr miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954121 # mshr miss rate for WriteReq accesses
system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.860342 # mshr miss rate for demand accesses
system.cpu6.l1c.demand_mshr_miss_rate::total 0.860342 # mshr miss rate for demand accesses
system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.860342 # mshr miss rate for overall accesses
system.cpu6.l1c.overall_mshr_miss_rate::total 0.860342 # mshr miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 15553.913071 # average ReadReq mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 15553.913071 # average ReadReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 27158.423272 # average WriteReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 27158.423272 # average WriteReq mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20157.843023 # average overall mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20157.843023 # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20157.843023 # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20157.843023 # average overall mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 65503.574548 # average ReadReq mshr uncacheable latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65503.574548 # average ReadReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 156203.121597 # average WriteReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156203.121597 # average WriteReq mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 98048.150234 # average overall mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 98048.150234 # average overall mshr uncacheable latency
2012-01-25 18:19:50 +01:00
system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
2015-09-25 13:27:03 +02:00
system.cpu7.num_reads 99282 # number of read accesses completed
system.cpu7.num_writes 55000 # number of write accesses completed
system.cpu7.l1c.tags.replacements 22412 # number of replacements
system.cpu7.l1c.tags.tagsinuse 392.240178 # Cycle average of tags in use
system.cpu7.l1c.tags.total_refs 13369 # Total number of references to valid blocks.
system.cpu7.l1c.tags.sampled_refs 22828 # Sample count of references to valid blocks.
system.cpu7.l1c.tags.avg_refs 0.585640 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-09-25 13:27:03 +02:00
system.cpu7.l1c.tags.occ_blocks::cpu7 392.240178 # Average occupied blocks per requestor
system.cpu7.l1c.tags.occ_percent::cpu7 0.766094 # Average percentage of cache occupancy
system.cpu7.l1c.tags.occ_percent::total 0.766094 # Average percentage of cache occupancy
system.cpu7.l1c.tags.occ_task_id_blocks::1024 416 # Occupied blocks per task id
system.cpu7.l1c.tags.age_task_id_blocks_1024::0 407 # Occupied blocks per task id
2015-07-03 16:15:03 +02:00
system.cpu7.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id
2015-09-25 13:27:03 +02:00
system.cpu7.l1c.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id
system.cpu7.l1c.tags.tag_accesses 337994 # Number of tag accesses
system.cpu7.l1c.tags.data_accesses 337994 # Number of data accesses
system.cpu7.l1c.ReadReq_hits::cpu7 8608 # number of ReadReq hits
system.cpu7.l1c.ReadReq_hits::total 8608 # number of ReadReq hits
system.cpu7.l1c.WriteReq_hits::cpu7 1119 # number of WriteReq hits
system.cpu7.l1c.WriteReq_hits::total 1119 # number of WriteReq hits
system.cpu7.l1c.demand_hits::cpu7 9727 # number of demand (read+write) hits
system.cpu7.l1c.demand_hits::total 9727 # number of demand (read+write) hits
system.cpu7.l1c.overall_hits::cpu7 9727 # number of overall hits
system.cpu7.l1c.overall_hits::total 9727 # number of overall hits
system.cpu7.l1c.ReadReq_misses::cpu7 36557 # number of ReadReq misses
system.cpu7.l1c.ReadReq_misses::total 36557 # number of ReadReq misses
system.cpu7.l1c.WriteReq_misses::cpu7 24000 # number of WriteReq misses
system.cpu7.l1c.WriteReq_misses::total 24000 # number of WriteReq misses
system.cpu7.l1c.demand_misses::cpu7 60557 # number of demand (read+write) misses
system.cpu7.l1c.demand_misses::total 60557 # number of demand (read+write) misses
system.cpu7.l1c.overall_misses::cpu7 60557 # number of overall misses
system.cpu7.l1c.overall_misses::total 60557 # number of overall misses
system.cpu7.l1c.ReadReq_miss_latency::cpu7 604992547 # number of ReadReq miss cycles
system.cpu7.l1c.ReadReq_miss_latency::total 604992547 # number of ReadReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::cpu7 682517760 # number of WriteReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::total 682517760 # number of WriteReq miss cycles
system.cpu7.l1c.demand_miss_latency::cpu7 1287510307 # number of demand (read+write) miss cycles
system.cpu7.l1c.demand_miss_latency::total 1287510307 # number of demand (read+write) miss cycles
system.cpu7.l1c.overall_miss_latency::cpu7 1287510307 # number of overall miss cycles
system.cpu7.l1c.overall_miss_latency::total 1287510307 # number of overall miss cycles
system.cpu7.l1c.ReadReq_accesses::cpu7 45165 # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.ReadReq_accesses::total 45165 # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::cpu7 25119 # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::total 25119 # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.demand_accesses::cpu7 70284 # number of demand (read+write) accesses
system.cpu7.l1c.demand_accesses::total 70284 # number of demand (read+write) accesses
system.cpu7.l1c.overall_accesses::cpu7 70284 # number of overall (read+write) accesses
system.cpu7.l1c.overall_accesses::total 70284 # number of overall (read+write) accesses
system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.809410 # miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_miss_rate::total 0.809410 # miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955452 # miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_miss_rate::total 0.955452 # miss rate for WriteReq accesses
system.cpu7.l1c.demand_miss_rate::cpu7 0.861604 # miss rate for demand accesses
system.cpu7.l1c.demand_miss_rate::total 0.861604 # miss rate for demand accesses
system.cpu7.l1c.overall_miss_rate::cpu7 0.861604 # miss rate for overall accesses
system.cpu7.l1c.overall_miss_rate::total 0.861604 # miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16549.294171 # average ReadReq miss latency
system.cpu7.l1c.ReadReq_avg_miss_latency::total 16549.294171 # average ReadReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 28438.240000 # average WriteReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::total 28438.240000 # average WriteReq miss latency
system.cpu7.l1c.demand_avg_miss_latency::cpu7 21261.130951 # average overall miss latency
system.cpu7.l1c.demand_avg_miss_latency::total 21261.130951 # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::cpu7 21261.130951 # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::total 21261.130951 # average overall miss latency
system.cpu7.l1c.blocked_cycles::no_mshrs 748003 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-09-25 13:27:03 +02:00
system.cpu7.l1c.blocked::no_mshrs 61301 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked
2015-09-25 13:27:03 +02:00
system.cpu7.l1c.avg_blocked_cycles::no_mshrs 12.202134 # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2012-01-25 18:19:50 +01:00
system.cpu7.l1c.fast_writes 0 # number of fast writes performed
system.cpu7.l1c.cache_copies 0 # number of cache copies performed
2015-09-25 13:27:03 +02:00
system.cpu7.l1c.writebacks::writebacks 9927 # number of writebacks
system.cpu7.l1c.writebacks::total 9927 # number of writebacks
system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36557 # number of ReadReq MSHR misses
system.cpu7.l1c.ReadReq_mshr_misses::total 36557 # number of ReadReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::cpu7 24000 # number of WriteReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::total 24000 # number of WriteReq MSHR misses
system.cpu7.l1c.demand_mshr_misses::cpu7 60557 # number of demand (read+write) MSHR misses
system.cpu7.l1c.demand_mshr_misses::total 60557 # number of demand (read+write) MSHR misses
system.cpu7.l1c.overall_mshr_misses::cpu7 60557 # number of overall MSHR misses
system.cpu7.l1c.overall_mshr_misses::total 60557 # number of overall MSHR misses
system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9747 # number of ReadReq MSHR uncacheable
system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9747 # number of ReadReq MSHR uncacheable
system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5404 # number of WriteReq MSHR uncacheable
system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5404 # number of WriteReq MSHR uncacheable
system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15151 # number of overall MSHR uncacheable misses
system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15151 # number of overall MSHR uncacheable misses
system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 568436547 # number of ReadReq MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_miss_latency::total 568436547 # number of ReadReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 658518760 # number of WriteReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::total 658518760 # number of WriteReq MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1226955307 # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::total 1226955307 # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1226955307 # number of overall MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::total 1226955307 # number of overall MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 638135236 # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 638135236 # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 851560751 # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 851560751 # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1489695987 # number of overall MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1489695987 # number of overall MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.809410 # mshr miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.809410 # mshr miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.955452 # mshr miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.955452 # mshr miss rate for WriteReq accesses
system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.861604 # mshr miss rate for demand accesses
system.cpu7.l1c.demand_mshr_miss_rate::total 0.861604 # mshr miss rate for demand accesses
system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.861604 # mshr miss rate for overall accesses
system.cpu7.l1c.overall_mshr_miss_rate::total 0.861604 # mshr miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 15549.321525 # average ReadReq mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 15549.321525 # average ReadReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 27438.281667 # average WriteReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 27438.281667 # average WriteReq mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20261.163978 # average overall mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20261.163978 # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20261.163978 # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20261.163978 # average overall mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 65469.912383 # average ReadReq mshr uncacheable latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65469.912383 # average ReadReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 157579.709660 # average WriteReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157579.709660 # average WriteReq mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 98323.278133 # average overall mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 98323.278133 # average overall mshr uncacheable latency
2012-01-25 18:19:50 +01:00
system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
2015-09-25 13:27:03 +02:00
system.l2c.tags.replacements 14184 # number of replacements
system.l2c.tags.tagsinuse 788.596931 # Cycle average of tags in use
system.l2c.tags.total_refs 165124 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 14990 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 11.015610 # Average number of references to valid blocks.
2015-02-11 16:23:31 +01:00
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-09-25 13:27:03 +02:00
system.l2c.tags.occ_blocks::writebacks 730.575268 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0 6.784178 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1 7.707727 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2 7.687216 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3 7.484376 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu4 6.524449 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu5 7.360121 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu6 7.299960 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu7 7.173635 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.713452 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0 0.006625 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1 0.007527 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2 0.007507 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3 0.007309 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu4 0.006372 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu5 0.007188 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu6 0.007129 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu7 0.007006 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.770114 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024 806 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 681 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.787109 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 2105340 # Number of tag accesses
system.l2c.tags.data_accesses 2105340 # Number of data accesses
system.l2c.Writeback_hits::writebacks 77391 # number of Writeback hits
system.l2c.Writeback_hits::total 77391 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0 263 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1 239 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2 258 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3 273 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu4 248 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu5 266 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu6 263 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu7 283 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 2093 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0 1731 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1 1747 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2 1743 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu3 1722 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu4 1763 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu5 1786 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu6 1787 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu7 1783 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 14062 # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0 10988 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1 10938 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2 10927 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu3 10853 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu4 11009 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu5 10877 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu6 10827 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu7 10964 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 87383 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0 12719 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1 12685 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2 12670 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3 12575 # number of demand (read+write) hits
system.l2c.demand_hits::cpu4 12772 # number of demand (read+write) hits
system.l2c.demand_hits::cpu5 12663 # number of demand (read+write) hits
system.l2c.demand_hits::cpu6 12614 # number of demand (read+write) hits
system.l2c.demand_hits::cpu7 12747 # number of demand (read+write) hits
system.l2c.demand_hits::total 101445 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0 12719 # number of overall hits
system.l2c.overall_hits::cpu1 12685 # number of overall hits
system.l2c.overall_hits::cpu2 12670 # number of overall hits
system.l2c.overall_hits::cpu3 12575 # number of overall hits
system.l2c.overall_hits::cpu4 12772 # number of overall hits
system.l2c.overall_hits::cpu5 12663 # number of overall hits
system.l2c.overall_hits::cpu6 12614 # number of overall hits
system.l2c.overall_hits::cpu7 12747 # number of overall hits
system.l2c.overall_hits::total 101445 # number of overall hits
system.l2c.UpgradeReq_misses::cpu0 1986 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1 2040 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2 2071 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3 2052 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu4 2099 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu5 2039 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu6 2050 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu7 2087 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 16424 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0 4684 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1 4646 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2 4587 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3 4709 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu4 4574 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu5 4603 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu6 4641 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu7 4708 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 37152 # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0 746 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1 738 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2 778 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu3 755 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu4 710 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu5 726 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu6 763 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu7 735 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 5951 # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0 5430 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1 5384 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2 5365 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3 5464 # number of demand (read+write) misses
system.l2c.demand_misses::cpu4 5284 # number of demand (read+write) misses
system.l2c.demand_misses::cpu5 5329 # number of demand (read+write) misses
system.l2c.demand_misses::cpu6 5404 # number of demand (read+write) misses
system.l2c.demand_misses::cpu7 5443 # number of demand (read+write) misses
system.l2c.demand_misses::total 43103 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0 5430 # number of overall misses
system.l2c.overall_misses::cpu1 5384 # number of overall misses
system.l2c.overall_misses::cpu2 5365 # number of overall misses
system.l2c.overall_misses::cpu3 5464 # number of overall misses
system.l2c.overall_misses::cpu4 5284 # number of overall misses
system.l2c.overall_misses::cpu5 5329 # number of overall misses
system.l2c.overall_misses::cpu6 5404 # number of overall misses
system.l2c.overall_misses::cpu7 5443 # number of overall misses
system.l2c.overall_misses::total 43103 # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0 59643812 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1 60697485 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2 64325987 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu3 61406491 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu4 65507992 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu5 63321487 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu6 63031988 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu7 64081491 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 502016733 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0 260655915 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1 258218912 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2 254645420 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3 260879417 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu4 253975429 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu5 255536909 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu6 257461916 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu7 261401431 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 2062775349 # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0 45984404 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1 45132427 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu2 48152413 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu3 46986917 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu4 43700923 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu5 45387411 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu6 47108917 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu7 45792412 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 368245824 # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0 306640319 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1 303351339 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2 302797833 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3 307866334 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu4 297676352 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu5 300924320 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu6 304570833 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu7 307193843 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 2431021173 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0 306640319 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1 303351339 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2 302797833 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3 307866334 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu4 297676352 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu5 300924320 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu6 304570833 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu7 307193843 # number of overall miss cycles
system.l2c.overall_miss_latency::total 2431021173 # number of overall miss cycles
system.l2c.Writeback_accesses::writebacks 77391 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 77391 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0 2249 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1 2279 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2 2329 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3 2325 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu4 2347 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu5 2305 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu6 2313 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu7 2370 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 18517 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0 6415 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1 6393 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2 6330 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3 6431 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu4 6337 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu5 6389 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu6 6428 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu7 6491 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 51214 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0 11734 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1 11676 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu2 11705 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu3 11608 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu4 11719 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu5 11603 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu6 11590 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu7 11699 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 93334 # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0 18149 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1 18069 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2 18035 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3 18039 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu4 18056 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu5 17992 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu6 18018 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu7 18190 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 144548 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0 18149 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1 18069 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2 18035 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3 18039 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu4 18056 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu5 17992 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu6 18018 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu7 18190 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 144548 # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0 0.883059 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1 0.895129 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2 0.889223 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3 0.882581 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu4 0.894333 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu5 0.884599 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu6 0.886295 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu7 0.880591 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.886969 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0 0.730164 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1 0.726732 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2 0.724645 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3 0.732234 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu4 0.721793 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu5 0.720457 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu6 0.721998 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu7 0.725312 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.725427 # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0 0.063576 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1 0.063207 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2 0.066467 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu3 0.065041 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu4 0.060585 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu5 0.062570 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu6 0.065833 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu7 0.062826 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.063760 # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0 0.299190 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1 0.297969 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2 0.297477 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3 0.302899 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu4 0.292645 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu5 0.296187 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu6 0.299922 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu7 0.299230 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.298192 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0 0.299190 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1 0.297969 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2 0.297477 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3 0.302899 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu4 0.292645 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu5 0.296187 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu6 0.299922 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu7 0.299230 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.298192 # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0 30032.130916 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1 29753.669118 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2 31060.351038 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu3 29925.190546 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu4 31209.143402 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu5 31055.167729 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu6 30747.311220 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu7 30705.074748 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 30566.045604 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0 55648.145816 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1 55578.758502 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2 55514.589056 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3 55400.173498 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu4 55525.891780 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu5 55515.296328 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu6 55475.525964 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu7 55522.818819 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 55522.592297 # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0 61641.292225 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1 61155.050136 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu2 61892.561697 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu3 62234.327152 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu4 61550.595775 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu5 62517.095041 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu6 61741.699869 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu7 62302.601361 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 61879.654512 # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0 56471.513628 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1 56343.116456 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2 56439.484250 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3 56344.497438 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu4 56335.418622 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu5 56469.191218 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu6 56360.257772 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu7 56438.332353 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 56400.277776 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0 56471.513628 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1 56343.116456 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2 56439.484250 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3 56344.497438 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu4 56335.418622 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu5 56469.191218 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu6 56360.257772 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu7 56438.332353 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 56400.277776 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 17704 # number of cycles access was blocked
2015-02-11 16:23:31 +01:00
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-09-25 13:27:03 +02:00
system.l2c.blocked::no_mshrs 3172 # number of cycles access was blocked
2015-02-11 16:23:31 +01:00
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2015-09-25 13:27:03 +02:00
system.l2c.avg_blocked_cycles::no_mshrs 5.581337 # average number of cycles each access was blocked
2015-02-11 16:23:31 +01:00
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
2015-09-25 13:27:03 +02:00
system.l2c.writebacks::writebacks 6492 # number of writebacks
system.l2c.writebacks::total 6492 # number of writebacks
system.l2c.UpgradeReq_mshr_hits::cpu1 1 # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu5 2 # number of UpgradeReq MSHR hits
2015-07-03 16:15:03 +02:00
system.l2c.UpgradeReq_mshr_hits::total 3 # number of UpgradeReq MSHR hits
2015-09-25 13:27:03 +02:00
system.l2c.ReadExReq_mshr_hits::cpu0 6 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu1 5 # number of ReadExReq MSHR hits
2015-07-03 16:15:03 +02:00
system.l2c.ReadExReq_mshr_hits::cpu2 3 # number of ReadExReq MSHR hits
2015-09-25 13:27:03 +02:00
system.l2c.ReadExReq_mshr_hits::cpu3 8 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu4 4 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu5 4 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu6 7 # number of ReadExReq MSHR hits
2015-07-03 16:15:03 +02:00
system.l2c.ReadExReq_mshr_hits::cpu7 3 # number of ReadExReq MSHR hits
2015-09-25 13:27:03 +02:00
system.l2c.ReadExReq_mshr_hits::total 40 # number of ReadExReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0 8 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1 11 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu2 15 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu3 8 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu4 8 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu5 5 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu6 11 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu7 4 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total 70 # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0 14 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1 16 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2 18 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3 16 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu4 12 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu5 9 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu6 18 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu7 7 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 110 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0 14 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1 16 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2 18 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3 16 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu4 12 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu5 9 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu6 18 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu7 7 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 110 # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks 1197 # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total 1197 # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0 1986 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1 2039 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2 2071 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3 2052 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu4 2099 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu5 2037 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu6 2050 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu7 2087 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 16421 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0 4678 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1 4641 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2 4584 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3 4701 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu4 4570 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu5 4599 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu6 4634 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu7 4705 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 37112 # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0 738 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1 727 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu2 763 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu3 747 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu4 702 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu5 721 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu6 752 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu7 731 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total 5881 # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0 5416 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1 5368 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2 5347 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3 5448 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu4 5272 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu5 5320 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu6 5386 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu7 5436 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 42993 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0 5416 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1 5368 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2 5347 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3 5448 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu4 5272 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu5 5320 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu6 5386 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu7 5436 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 42993 # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0 9773 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1 9723 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu2 9760 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu3 9771 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu4 9898 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu5 9891 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu6 9845 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu7 9747 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total 78408 # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0 5449 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1 5329 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu2 5533 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu3 5455 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu4 5382 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu5 5483 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu6 5508 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu7 5404 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total 43543 # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0 15222 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1 15052 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu2 15293 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu3 15226 # number of overall MSHR uncacheable misses
2015-07-03 16:15:03 +02:00
system.l2c.overall_mshr_uncacheable_misses::cpu4 15280 # number of overall MSHR uncacheable misses
2015-09-25 13:27:03 +02:00
system.l2c.overall_mshr_uncacheable_misses::cpu5 15374 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu6 15353 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu7 15151 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total 121951 # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0 89216305 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1 91661476 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2 93067979 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3 92238981 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu4 94104480 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu5 91562476 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu6 91964478 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu7 93840981 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 737657156 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0 213700915 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1 211685412 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2 208764420 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3 213671917 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu4 208164429 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu5 209421909 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu6 210919416 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu7 214243431 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 1690571849 # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0 38320904 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1 37446428 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2 40065914 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu3 39278917 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu4 36377424 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu5 38015411 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu6 39226917 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu7 38343914 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 307075829 # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0 252021819 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1 249131840 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2 248830334 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3 252950834 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu4 244541853 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu5 247437320 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu6 250146333 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu7 252587345 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 1997647678 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0 252021819 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1 249131840 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2 248830334 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3 252950834 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu4 244541853 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu5 247437320 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu6 250146333 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu7 252587345 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 1997647678 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 434119876 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 432203209 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 433941865 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 434763383 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 440636377 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 440018712 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 437840875 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 433521379 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 3487045676 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 249140431 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 246794950 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 253993435 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 250261774 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 246746570 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 252474432 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 253706432 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 248671425 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 2001789449 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0 683260307 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1 678998159 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2 687935300 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu3 685025157 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu4 687382947 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu5 692493144 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu6 691547307 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu7 682192804 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 5488835125 # number of overall MSHR uncacheable cycles
2015-07-03 16:15:03 +02:00
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2015-09-25 13:27:03 +02:00
system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.883059 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.894691 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.889223 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.882581 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.894333 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.883731 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.886295 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.880591 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.886807 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.729228 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.725950 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.724171 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.730991 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.721161 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.719831 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.720909 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.724850 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.724646 # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.062894 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.062264 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.065186 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.064352 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.059903 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.062139 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.064884 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.062484 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.063010 # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0 0.298419 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1 0.297083 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2 0.296479 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3 0.302012 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu4 0.291981 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu5 0.295687 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu6 0.298923 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu7 0.298846 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.297431 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0 0.298419 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1 0.297083 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2 0.296479 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3 0.302012 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu4 0.291981 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu5 0.295687 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu6 0.298923 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu7 0.298846 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.297431 # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 44922.610775 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 44954.132418 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 44938.666828 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 44950.770468 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 44833.006193 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 44949.669121 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 44860.720976 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 44964.533301 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44921.573351 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 45682.110945 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 45612.025856 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 45541.976440 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 45452.439268 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 45550.203282 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 45536.401174 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 45515.627104 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 45535.266950 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 45553.240165 # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 51925.344173 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 51508.154058 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 52511.027523 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 52582.218206 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 51819.692308 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 52725.951456 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 52163.453457 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 52454.054720 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 52214.900357 # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0 46532.832164 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1 46410.551416 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2 46536.438003 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3 46430.035609 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu4 46385.025228 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu5 46510.774436 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu6 46443.804864 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu7 46465.663171 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 46464.486730 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0 46532.832164 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1 46410.551416 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2 46536.438003 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3 46430.035609 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu4 46385.025228 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu5 46510.774436 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu6 46443.804864 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu7 46465.663171 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 46464.486730 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 44420.329070 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 44451.631081 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 44461.256660 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 44495.280217 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 44517.718428 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 44486.777070 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 44473.425597 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 44477.416538 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 44473.085348 # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 45722.229950 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 46311.681366 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 45905.193385 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 45877.502108 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 45846.631364 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 46046.768557 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 46061.443718 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 46016.177831 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 45972.703971 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 44886.368874 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 45110.162038 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 44983.672268 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 44990.487127 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 44985.794961 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 45043.134123 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 45043.138605 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 45026.255957 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 45008.529040 # average overall mshr uncacheable latency
2015-02-11 16:23:31 +01:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::ReadReq 78406 # Transaction distribution
system.membus.trans_dist::ReadResp 84270 # Transaction distribution
system.membus.trans_dist::WriteReq 43542 # Transaction distribution
system.membus.trans_dist::WriteResp 43539 # Transaction distribution
system.membus.trans_dist::Writeback 6492 # Transaction distribution
system.membus.trans_dist::CleanEvict 1226 # Transaction distribution
system.membus.trans_dist::UpgradeReq 61182 # Transaction distribution
system.membus.trans_dist::UpgradeResp 50391 # Transaction distribution
system.membus.trans_dist::ReadExReq 49587 # Transaction distribution
system.membus.trans_dist::ReadExResp 3167 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 5869 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 427671 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 427671 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1115735 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 1115735 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 57207 # Total snoops (count)
system.membus.snoop_fanout::samples 255615 # Request fanout histogram
2015-02-11 16:23:31 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.membus.snoop_fanout::0 255615 100.00% 100.00% # Request fanout histogram
2015-02-11 16:23:31 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.membus.snoop_fanout::total 255615 # Request fanout histogram
system.membus.reqLayer0.occupancy 293172648 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 56.6 # Layer utilization (%)
system.membus.respLayer0.occupancy 310812284 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 60.0 # Layer utilization (%)
system.toL2Bus.snoop_filter.tot_requests 663719 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 283046 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 335146 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 12757 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 5920 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 6837 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq 78408 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 370885 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.toL2Bus.trans_dist::WriteReq 43543 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 43537 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 83883 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 20723 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 29304 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 29302 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 162111 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 162107 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 292494 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 122788 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122467 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122636 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122530 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122578 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 122681 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122805 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122788 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 981273 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1801396 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1791690 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1789116 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1791289 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1784816 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1780428 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1784184 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1802670 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 14325589 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 335027 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 801595 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 1.188537 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 1.005333 # Request fanout histogram
2015-02-11 16:23:31 +01:00
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::0 216155 26.97% 26.97% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 322197 40.19% 67.16% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 179904 22.44% 89.60% # Request fanout histogram
system.toL2Bus.snoop_fanout::3 65286 8.14% 97.75% # Request fanout histogram
system.toL2Bus.snoop_fanout::4 15605 1.95% 99.69% # Request fanout histogram
system.toL2Bus.snoop_fanout::5 2259 0.28% 99.98% # Request fanout histogram
system.toL2Bus.snoop_fanout::6 176 0.02% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::7 13 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
2015-02-11 16:23:31 +01:00
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 801595 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 495500281 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 95.7 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 101557213 # Layer occupancy (ticks)
2015-07-03 16:15:03 +02:00
system.toL2Bus.respLayer0.utilization 19.6 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.toL2Bus.respLayer1.occupancy 101587169 # Layer occupancy (ticks)
2015-07-03 16:15:03 +02:00
system.toL2Bus.respLayer1.utilization 19.6 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.toL2Bus.respLayer2.occupancy 101172758 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 19.5 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 101251086 # Layer occupancy (ticks)
2015-07-03 16:15:03 +02:00
system.toL2Bus.respLayer3.utilization 19.6 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.toL2Bus.respLayer4.occupancy 101367103 # Layer occupancy (ticks)
2015-07-03 16:15:03 +02:00
system.toL2Bus.respLayer4.utilization 19.6 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.toL2Bus.respLayer5.occupancy 101469413 # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization 19.6 # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy 101588792 # Layer occupancy (ticks)
2015-07-03 16:15:03 +02:00
system.toL2Bus.respLayer6.utilization 19.6 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.toL2Bus.respLayer7.occupancy 101399821 # Layer occupancy (ticks)
2015-07-03 16:15:03 +02:00
system.toL2Bus.respLayer7.utilization 19.6 # Layer utilization (%)
2007-02-07 06:16:33 +01:00
---------- End Simulation Statistics ----------
