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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt

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arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
---------- Begin Simulation Statistics ----------
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
sim_seconds 51.799232 # Number of seconds simulated
sim_ticks 51799232151500 # Number of ticks simulated
final_tick 51799232151500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
host_inst_rate 1085172 # Simulator instruction rate (inst/s)
host_op_rate 1275227 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 67259328222 # Simulator tick rate (ticks/s)
host_mem_usage 678040 # Number of bytes of host memory used
host_seconds 770.14 # Real time elapsed on the host
sim_insts 835736802 # Number of instructions simulated
sim_ops 982105580 # Number of ops (including micro ops) simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.physmem.bytes_read::cpu0.dtb.walker 74880 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 80448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 2375384 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 17755184 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 76352 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 77888 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 2376540 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 17975768 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 395840 # Number of bytes read from this memory
system.physmem.bytes_read::total 41188284 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 2375384 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 2376540 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 4751924 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 62641792 # Number of bytes written to this memory
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.physmem.bytes_written::cpu0.data 15860 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 4720 # Number of bytes written to this memory
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.physmem.bytes_written::total 62662372 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 1170 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1257 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 57776 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 277428 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 1193 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 1217 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 56880 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 280881 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6185 # Number of read requests responded to by this memory
system.physmem.num_reads::total 683987 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 978778 # Number of write requests responded to by this memory
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.physmem.num_writes::cpu0.data 1983 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 590 # Number of write requests responded to by this memory
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.physmem.num_writes::total 981351 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 1446 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 1553 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 45858 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 342769 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 1474 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 1504 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 45880 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 347028 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 7642 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 795152 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 45858 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 45880 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 91737 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1209319 # Write bandwidth from this memory (bytes/s)
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.physmem.bw_write::cpu0.data 306 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 91 # Write bandwidth from this memory (bytes/s)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.physmem.bw_write::total 1209716 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1209319 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 1446 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 1553 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 45858 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 343075 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 1474 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 1504 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 45880 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 347119 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 7642 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2004869 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 683987 # Number of read requests accepted
system.physmem.writeReqs 981351 # Number of write requests accepted
system.physmem.readBursts 683987 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 981351 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 43730304 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 44864 # Total number of bytes read from write queue
system.physmem.bytesWritten 62662336 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 41188284 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 62662372 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 701 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.physmem.perBankRdBursts::0 41322 # Per bank write bursts
system.physmem.perBankRdBursts::1 41177 # Per bank write bursts
system.physmem.perBankRdBursts::2 39218 # Per bank write bursts
system.physmem.perBankRdBursts::3 39952 # Per bank write bursts
system.physmem.perBankRdBursts::4 41092 # Per bank write bursts
system.physmem.perBankRdBursts::5 49504 # Per bank write bursts
system.physmem.perBankRdBursts::6 36877 # Per bank write bursts
system.physmem.perBankRdBursts::7 36988 # Per bank write bursts
system.physmem.perBankRdBursts::8 38459 # Per bank write bursts
system.physmem.perBankRdBursts::9 81977 # Per bank write bursts
system.physmem.perBankRdBursts::10 39138 # Per bank write bursts
system.physmem.perBankRdBursts::11 41925 # Per bank write bursts
system.physmem.perBankRdBursts::12 38445 # Per bank write bursts
system.physmem.perBankRdBursts::13 41518 # Per bank write bursts
system.physmem.perBankRdBursts::14 36799 # Per bank write bursts
system.physmem.perBankRdBursts::15 38895 # Per bank write bursts
system.physmem.perBankWrBursts::0 61042 # Per bank write bursts
system.physmem.perBankWrBursts::1 63110 # Per bank write bursts
system.physmem.perBankWrBursts::2 61459 # Per bank write bursts
system.physmem.perBankWrBursts::3 62355 # Per bank write bursts
system.physmem.perBankWrBursts::4 60847 # Per bank write bursts
system.physmem.perBankWrBursts::5 67831 # Per bank write bursts
system.physmem.perBankWrBursts::6 59687 # Per bank write bursts
system.physmem.perBankWrBursts::7 59677 # Per bank write bursts
system.physmem.perBankWrBursts::8 60696 # Per bank write bursts
system.physmem.perBankWrBursts::9 62695 # Per bank write bursts
system.physmem.perBankWrBursts::10 60108 # Per bank write bursts
system.physmem.perBankWrBursts::11 60915 # Per bank write bursts
system.physmem.perBankWrBursts::12 59030 # Per bank write bursts
system.physmem.perBankWrBursts::13 62102 # Per bank write bursts
system.physmem.perBankWrBursts::14 56975 # Per bank write bursts
system.physmem.perBankWrBursts::15 60570 # Per bank write bursts
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.physmem.numWrRetry 35 # Number of times write queue was full causing retry
system.physmem.totGap 51799229214500 # Total gap between requests
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 43101 # Read request sizes (log2)
system.physmem.readPktSize::3 13 # Read request sizes (log2)
system.physmem.readPktSize::4 2 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.physmem.readPktSize::6 640871 # Read request sizes (log2)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 1 # Write request sizes (log2)
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.physmem.writePktSize::6 978778 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 654776 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 22950 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 392 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 323 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 447 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 529 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 496 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1170 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 667 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 289 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 342 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 149 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 147 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 110 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 105 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 101 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 90 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 88 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 66 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 49 # What read queue length does an incoming req see
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.physmem.wrQLenPdf::0 1596 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1526 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1505 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1480 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1461 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1451 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1436 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1423 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1403 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1385 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1368 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1354 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1352 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1337 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1326 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 31896 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 37595 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 53715 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 53386 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 56244 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 54082 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 56988 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 54298 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 54807 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 54383 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 55346 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 57492 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 55406 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 55164 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 56641 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 53923 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 52610 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 52233 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 2219 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 884 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 692 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 529 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 505 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 476 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 464 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 357 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 370 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 327 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 341 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 357 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 390 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 249 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 283 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 272 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 294 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 249 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 276 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 183 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 195 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 132 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 181 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 204 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 131 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 144 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 178 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 188 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 72 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 89 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 437346 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 243.268076 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 146.507272 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 286.058540 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 195461 44.69% 44.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 115696 26.45% 71.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 38501 8.80% 79.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 20148 4.61% 84.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 13086 2.99% 87.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 8742 2.00% 89.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 7314 1.67% 91.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 5744 1.31% 92.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 32654 7.47% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 437346 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 51642 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 13.230801 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 107.035752 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 51638 99.99% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::7168-8191 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::17408-18431 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 51642 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 51642 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 18.959355 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.129785 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 8.514310 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3 120 0.23% 0.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7 58 0.11% 0.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11 71 0.14% 0.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15 110 0.21% 0.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 46610 90.26% 90.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 2201 4.26% 95.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 409 0.79% 96.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 381 0.74% 96.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 125 0.24% 96.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 97 0.19% 97.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 249 0.48% 97.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 37 0.07% 97.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 313 0.61% 98.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 78 0.15% 98.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 24 0.05% 98.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 64 0.12% 98.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 317 0.61% 99.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 20 0.04% 99.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 23 0.04% 99.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 120 0.23% 99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 150 0.29% 99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 1 0.00% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 1 0.00% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 1 0.00% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 1 0.00% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 3 0.01% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 3 0.01% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 3 0.01% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 2 0.00% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 1 0.00% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 12 0.02% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 3 0.01% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139 2 0.00% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 4 0.01% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 17 0.03% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163 3 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179 4 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::196-199 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::252-255 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 51642 # Writes before turning the bus around for reads
system.physmem.totQLat 9080957107 # Total ticks spent queuing
system.physmem.totMemAccLat 21892569607 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 3416430000 # Total ticks spent in databus transfers
system.physmem.avgQLat 13290.13 # Average queueing delay per DRAM burst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.physmem.avgMemAccLat 32040.13 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 0.84 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.21 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 0.80 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.21 # Average system write bandwidth in MiByte/s
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.busUtil 0.02 # Data bus utilization in percentage
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.physmem.avgWrQLen 11.30 # Average write queue length when enqueuing
system.physmem.readRowHits 503634 # Number of row buffer hits during reads
system.physmem.writeRowHits 721404 # Number of row buffer hits during writes
system.physmem.readRowHitRate 73.71 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 73.68 # Row buffer hit rate for writes
system.physmem.avgGap 31104333.90 # Average gap between requests
system.physmem.pageHitRate 73.69 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 1696456440 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 925645875 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 2543814000 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 3214131840 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3383273718240 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1286151175755 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 29951333686500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 34629138628650 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.526160 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 49826371298908 # Time in different power states
system.physmem_0.memoryStateTime::REF 1729690040000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.physmem_0.memoryStateTime::ACT 243166128592 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.physmem_1.actEnergy 1609879320 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 878406375 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 2785777800 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 3130429680 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3383273718240 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 1282982007105 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 29954113659000 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 34628773877520 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.519119 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 49831003018963 # Time in different power states
system.physmem_1.memoryStateTime::REF 1729690040000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.physmem_1.memoryStateTime::ACT 238538435537 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dtb.walker.walks 118484 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 118484 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17724 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 86321 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples 118475 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean 0.236337 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 81.347587 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-2047 118474 100.00% 100.00% # Table walker wait (enqueue to first request) latency
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu0.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dtb.walker.walkWaitTime::total 118475 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples 104054 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 25330.679263 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 21934.679716 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 16178.136591 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535 103422 99.39% 99.39% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1 0.00% 99.39% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607 549 0.53% 99.92% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143 13 0.01% 99.93% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679 39 0.04% 99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215 8 0.01% 99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751 17 0.02% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total 104054 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples -2515798788 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 1.690729 # Table walker pending requests distribution
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu0.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dtb.walker.walksPending::0 1737735704 -69.07% -69.07% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1 -4253534492 169.07% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total -2515798788 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 86322 82.97% 82.97% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M 17724 17.03% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 104046 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 118484 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 118484 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 104046 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 104046 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 222530 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dtb.read_hits 78608030 # DTB read hits
system.cpu0.dtb.read_misses 90806 # DTB read misses
system.cpu0.dtb.write_hits 71283429 # DTB write hits
system.cpu0.dtb.write_misses 27678 # DTB write misses
system.cpu0.dtb.flush_tlb 51806 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dtb.flush_tlb_mva_asid 19521 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 503 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 69055 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dtb.prefetch_faults 4281 # Number of TLB faults due to prefetch
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dtb.perms_faults 9631 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 78698836 # DTB read accesses
system.cpu0.dtb.write_accesses 71311107 # DTB write accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dtb.hits 149891459 # DTB hits
system.cpu0.dtb.misses 118484 # DTB misses
system.cpu0.dtb.accesses 150009943 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.itb.walker.walks 76645 # Table walker walks requested
system.cpu0.itb.walker.walksLong 76645 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2 4248 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3 67077 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walkWaitTime::samples 76645 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0 76645 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 76645 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 71325 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 28947.290571 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 25637.754479 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 19237.260354 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535 70555 98.92% 98.92% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071 2 0.00% 98.92% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607 668 0.94% 99.86% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143 18 0.03% 99.89% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679 42 0.06% 99.94% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215 15 0.02% 99.96% # Table walker service (enqueue to completion) latency
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu0.itb.walker.walkCompletionTime::393216-458751 21 0.03% 99.99% # Table walker service (enqueue to completion) latency
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total 71325 # Table walker service (enqueue to completion) latency
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.itb.walker.walksPending::samples 1705681704 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 1705681704 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 1705681704 # Table walker pending requests distribution
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.itb.walker.walkPageSizes::4K 67077 94.04% 94.04% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M 4248 5.96% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 71325 # Table walker page sizes translated
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 76645 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 76645 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 71325 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 71325 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 147970 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 417906874 # ITB inst hits
system.cpu0.itb.inst_misses 76645 # ITB inst misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.itb.flush_tlb 51806 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.itb.flush_tlb_mva_asid 19521 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 503 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 51690 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.itb.inst_accesses 417983519 # ITB inst accesses
system.cpu0.itb.hits 417906874 # DTB hits
system.cpu0.itb.misses 76645 # DTB misses
system.cpu0.itb.accesses 417983519 # DTB accesses
system.cpu0.numCycles 51800067955 # number of cpu cycles simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update for UDelayEvent quiesce change
2015-10-10 23:45:41 +02:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.kern.inst.quiesce 16018 # number of quiesce instructions executed
system.cpu0.committedInsts 417645333 # Number of instructions committed
system.cpu0.committedOps 490761503 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 451046619 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 435772 # Number of float alu accesses
system.cpu0.num_func_calls 25047272 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 63386661 # number of instructions that are conditional controls
system.cpu0.num_int_insts 451046619 # number of integer instructions
system.cpu0.num_fp_insts 435772 # number of float instructions
system.cpu0.num_int_register_reads 653989680 # number of times the integer registers were read
system.cpu0.num_int_register_writes 357583746 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 703407 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 366712 # number of times the floating registers were written
system.cpu0.num_cc_register_reads 108509856 # number of times the CC registers were read
system.cpu0.num_cc_register_writes 108205607 # number of times the CC registers were written
system.cpu0.num_mem_refs 149883436 # number of memory refs
system.cpu0.num_load_insts 78604497 # Number of load instructions
system.cpu0.num_store_insts 71278939 # Number of store instructions
system.cpu0.num_idle_cycles 50264779959.264511 # Number of idle cycles
system.cpu0.num_busy_cycles 1535287995.735491 # Number of busy cycles
system.cpu0.not_idle_fraction 0.029639 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.970361 # Percentage of idle cycles
system.cpu0.Branches 93191056 # Number of branches fetched
system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu 339970284 69.23% 69.23% # Class of executed instruction
system.cpu0.op_class::IntMult 1088528 0.22% 69.46% # Class of executed instruction
system.cpu0.op_class::IntDiv 48838 0.01% 69.47% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 69.47% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 69.47% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 69.47% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 69.47% # Class of executed instruction
system.cpu0.op_class::FloatDiv 0 0.00% 69.47% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 69.47% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 69.47% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 69.47% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 69.47% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 69.47% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 69.47% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 69.47% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 69.47% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 69.47% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 69.47% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.47% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 69.47% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 4 0.00% 69.47% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.47% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 11 0.00% 69.47% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 16 0.00% 69.47% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.47% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 53987 0.01% 69.48% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.48% # Class of executed instruction
system.cpu0.op_class::MemRead 78604497 16.01% 85.48% # Class of executed instruction
system.cpu0.op_class::MemWrite 71278939 14.52% 100.00% # Class of executed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.op_class::total 491045105 # Class of executed instruction
system.cpu0.dcache.tags.replacements 9348690 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.942765 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 290545917 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 9349202 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 31.077082 # Average number of references to valid blocks.
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu0.dcache.tags.warmup_cycle 5830459500 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dcache.tags.occ_blocks::cpu0.data 239.060392 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 272.882373 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.466915 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.532973 # Average percentage of cache occupancy
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.tags.occ_percent::total 0.999888 # Average percentage of cache occupancy
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 54 # Occupied blocks per task id
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dcache.tags.tag_accesses 1209380446 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 1209380446 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 73565050 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 73675214 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 147240264 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 67654945 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 67959241 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 135614186 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 188452 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 185421 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 373873 # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data 174201 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu1.data 157964 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total 332165 # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1663387 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1666647 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 3330034 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1801503 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 1811825 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 3613328 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 141219995 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 141634455 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 282854450 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 141408447 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 141819876 # number of overall hits
system.cpu0.dcache.overall_hits::total 283228323 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 2455322 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 2424347 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 4879669 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1010929 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 979195 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 1990124 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 579794 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 548628 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 1128422 # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data 615937 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu1.data 604869 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total 1220806 # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 138893 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 146035 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 284928 # number of LoadLockedReq misses
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dcache.StoreCondReq_misses::cpu1.data 1 # number of StoreCondReq misses
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dcache.demand_misses::cpu0.data 3466251 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 3403542 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 6869793 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 4046045 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 3952170 # number of overall misses
system.cpu0.dcache.overall_misses::total 7998215 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 42484250000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 41555213000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 84039463000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 34427531000 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 34839037500 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 69266568500 # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 24097071500 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 24097548000 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total 48194619500 # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2157672000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 2231824000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 4389496000 # number of LoadLockedReq miss cycles
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 80000 # number of StoreCondReq miss cycles
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 82000 # number of StoreCondReq miss cycles
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu0.dcache.StoreCondReq_miss_latency::total 162000 # number of StoreCondReq miss cycles
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dcache.demand_miss_latency::cpu0.data 76911781000 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 76394250500 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 153306031500 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 76911781000 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 76394250500 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 153306031500 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 76020372 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 76099561 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 152119933 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 68665874 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 68938436 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 137604310 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 768246 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 734049 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 1502295 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 790138 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 762833 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total 1552971 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1802280 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 1812682 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 3614962 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1801504 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 1811826 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 3613330 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 144686246 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 145037997 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 289724243 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 145454492 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 145772046 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 291226538 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.032298 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.031858 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.032078 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.014722 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014204 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.014463 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.754698 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.747400 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.751132 # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.779531 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.792925 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total 0.786110 # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.077065 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.080563 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.078819 # miss rate for LoadLockedReq accesses
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000001 # miss rate for StoreCondReq accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000001 # miss rate for StoreCondReq accesses
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.023957 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.023467 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.023711 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027817 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.027112 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.027464 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17302.924016 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17140.785952 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 17222.369591 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34055.340187 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35579.264089 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 34805.152091 # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 39122.623742 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 39839.284209 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 39477.705303 # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15534.778571 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15282.802068 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15405.632300 # average LoadLockedReq miss latency
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 80000 # average StoreCondReq miss latency
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 82000 # average StoreCondReq miss latency
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 81000 # average StoreCondReq miss latency
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22188.751190 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 22445.514261 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 22315.960830 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19009.126443 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19329.697483 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 19167.530693 # average overall miss latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dcache.writebacks::writebacks 7311510 # number of writebacks
system.cpu0.dcache.writebacks::total 7311510 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 10741 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 10926 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 21667 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 9837 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 11420 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 21257 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 34142 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 33805 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 67947 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 20578 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 22346 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 42924 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 20578 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 22346 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 42924 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2444581 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 2413421 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 4858002 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1001092 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 967775 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 1968867 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 578929 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 547722 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 1126651 # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 615937 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 604869 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total 1220806 # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 104751 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 112230 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 216981 # number of LoadLockedReq MSHR misses
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 1 # number of StoreCondReq MSHR misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 1 # number of StoreCondReq MSHR misses
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dcache.demand_mshr_misses::cpu0.data 3445673 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 3381196 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 6826869 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 4024602 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 3928918 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 7953520 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17141 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 16563 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33704 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 18220 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 15489 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33709 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 35361 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 32052 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 67413 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 39404055500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 38485092000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 77889147500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 32954735000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 33366748000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 66321483000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 10711932500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 10507751500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 21219684000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 23481134500 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 23492679000 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 46973813500 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1456238000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1530654000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2986892000 # number of LoadLockedReq MSHR miss cycles
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 79000 # number of StoreCondReq MSHR miss cycles
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 81000 # number of StoreCondReq MSHR miss cycles
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 160000 # number of StoreCondReq MSHR miss cycles
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 72358790500 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 71851840000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 144210630500 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 83070723000 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 82359591500 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 165430314500 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3180599500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3018965000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6199564500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3329040000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2888636500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 6217676500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6509639500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5907601500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12417241000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032157 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.031714 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031935 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014579 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014038 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014308 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.753572 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.746165 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.749953 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.779531 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.792925 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.786110 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.058121 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.061914 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060023 # mshr miss rate for LoadLockedReq accesses
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000001 # mshr miss rate for StoreCondReq accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000001 # mshr miss rate for StoreCondReq accesses
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023815 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.023312 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.023563 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027669 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026952 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.027310 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16118.940424 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15946.282062 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16033.164972 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32918.787684 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34477.794942 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33685.100619 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 18503.015914 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19184.461278 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18834.300950 # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 38122.623742 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 38839.284209 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 38477.705303 # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13901.900698 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13638.545843 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13765.684553 # average LoadLockedReq mshr miss latency
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 79000 # average StoreCondReq mshr miss latency
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 81000 # average StoreCondReq mshr miss latency
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 80000 # average StoreCondReq mshr miss latency
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20999.900600 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21250.421449 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21123.977990 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20640.729941 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20962.410389 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20799.635193 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185555.072633 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 182271.629536 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183941.505459 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182713.501647 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 186495.997159 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184451.526299 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 184090.933514 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 184313.038188 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184196.534793 # average overall mshr uncacheable latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.icache.tags.replacements 13311280 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.820918 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 822940675 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 13311792 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 61.820428 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 49369795500 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 242.457113 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 269.363804 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.473549 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.526101 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999650 # Average percentage of cache occupancy
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 217 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.icache.tags.tag_accesses 849564269 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 849564269 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 411229460 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 411711215 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 822940675 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 411229460 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 411711215 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 822940675 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 411229460 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 411711215 # number of overall hits
system.cpu0.icache.overall_hits::total 822940675 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 6677414 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 6634383 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 13311797 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 6677414 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 6634383 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 13311797 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 6677414 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 6634383 # number of overall misses
system.cpu0.icache.overall_misses::total 13311797 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 91283856500 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 90751913000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 182035769500 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 91283856500 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 90751913000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 182035769500 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 91283856500 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 90751913000 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 182035769500 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 417906874 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 418345598 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 836252472 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 417906874 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 418345598 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 836252472 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 417906874 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 418345598 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 836252472 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015978 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015859 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.015918 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015978 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015859 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.015918 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015978 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015859 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.015918 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13670.540197 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13679.028329 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13674.770544 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13670.540197 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13679.028329 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13674.770544 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13670.540197 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13679.028329 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13674.770544 # average overall miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.icache.writebacks::writebacks 13311280 # number of writebacks
system.cpu0.icache.writebacks::total 13311280 # number of writebacks
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6677414 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 6634383 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 13311797 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 6677414 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 6634383 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 13311797 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 6677414 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 6634383 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 13311797 # number of overall MSHR misses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 22062 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst 21063 # number of ReadReq MSHR uncacheable
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 22062 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst 21063 # number of overall MSHR uncacheable misses
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 84606442500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 84117530000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 168723972500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 84606442500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 84117530000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 168723972500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 84606442500 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 84117530000 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 168723972500 # number of overall MSHR miss cycles
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2780591500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2656208000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 5436799500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2780591500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 2656208000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 5436799500 # number of overall MSHR uncacheable cycles
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.015978 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015859 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.015918 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.015978 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015859 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.015918 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.015978 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015859 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.015918 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12670.540197 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12679.028329 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12674.770544 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12670.540197 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12679.028329 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12674.770544 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12670.540197 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12679.028329 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12674.770544 # average overall mshr miss latency
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 126035.332245 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126107.771922 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.713043 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 126035.332245 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126107.771922 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 126070.713043 # average overall mshr uncacheable latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu1.dtb.walker.walks 116402 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 116402 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17438 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 84735 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore 8 # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples 116394 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean 0.103098 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 35.173529 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-1023 116393 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::11264-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 116394 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 102181 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 25297.388947 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 21878.077952 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 16308.937968 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535 101549 99.38% 99.38% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071 2 0.00% 99.38% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607 548 0.54% 99.92% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143 11 0.01% 99.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679 41 0.04% 99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215 2 0.00% 99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751 24 0.02% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 102181 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 344855740 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean -3.415840 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 1522827704 441.58% 441.58% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1 -1177971964 -341.58% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 344855740 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 84735 82.93% 82.93% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M 17438 17.07% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 102173 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 116402 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 116402 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 102173 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 102173 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 218575 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu1.dtb.read_hits 78662844 # DTB read hits
system.cpu1.dtb.read_misses 89684 # DTB read misses
system.cpu1.dtb.write_hits 71537174 # DTB write hits
system.cpu1.dtb.write_misses 26718 # DTB write misses
system.cpu1.dtb.flush_tlb 51800 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu1.dtb.flush_tlb_mva_asid 18845 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 504 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 67247 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu1.dtb.prefetch_faults 3767 # Number of TLB faults due to prefetch
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu1.dtb.perms_faults 9113 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 78752528 # DTB read accesses
system.cpu1.dtb.write_accesses 71563892 # DTB write accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu1.dtb.hits 150200018 # DTB hits
system.cpu1.dtb.misses 116402 # DTB misses
system.cpu1.dtb.accesses 150316420 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu1.itb.walker.walks 74223 # Table walker walks requested
system.cpu1.itb.walker.walksLong 74223 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2 4163 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3 64958 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples 74223 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0 74223 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 74223 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 69121 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 28935.417601 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 25541.870805 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 19930.697059 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535 68364 98.90% 98.90% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071 4 0.01% 98.91% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607 655 0.95% 99.86% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143 17 0.02% 99.88% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679 38 0.05% 99.94% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751 18 0.03% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::524288-589823 5 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 69121 # Table walker service (enqueue to completion) latency
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu1.itb.walker.walksPending::samples 1449734704 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 1449734704 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 1449734704 # Table walker pending requests distribution
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu1.itb.walker.walkPageSizes::4K 64958 93.98% 93.98% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M 4163 6.02% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 69121 # Table walker page sizes translated
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 74223 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 74223 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 69121 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 69121 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 143344 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 418345598 # ITB inst hits
system.cpu1.itb.inst_misses 74223 # ITB inst misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu1.itb.flush_tlb 51800 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu1.itb.flush_tlb_mva_asid 18845 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 504 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 49961 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu1.itb.inst_accesses 418419821 # ITB inst accesses
system.cpu1.itb.hits 418345598 # DTB hits
system.cpu1.itb.misses 74223 # DTB misses
system.cpu1.itb.accesses 418419821 # DTB accesses
system.cpu1.numCycles 51798396348 # number of cpu cycles simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update for UDelayEvent quiesce change
2015-10-10 23:45:41 +02:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu1.committedInsts 418091469 # Number of instructions committed
system.cpu1.committedOps 491344077 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 451749452 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 464131 # Number of float alu accesses
system.cpu1.num_func_calls 25120971 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 63413635 # number of instructions that are conditional controls
system.cpu1.num_int_insts 451749452 # number of integer instructions
system.cpu1.num_fp_insts 464131 # number of float instructions
system.cpu1.num_int_register_reads 653305653 # number of times the integer registers were read
system.cpu1.num_int_register_writes 357922313 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 749406 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 392664 # number of times the floating registers were written
system.cpu1.num_cc_register_reads 108141039 # number of times the CC registers were read
system.cpu1.num_cc_register_writes 107840924 # number of times the CC registers were written
system.cpu1.num_mem_refs 150187574 # number of memory refs
system.cpu1.num_load_insts 78657446 # Number of load instructions
system.cpu1.num_store_insts 71530128 # Number of store instructions
system.cpu1.num_idle_cycles 50264307367.295029 # Number of idle cycles
system.cpu1.num_busy_cycles 1534088980.704967 # Number of busy cycles
system.cpu1.not_idle_fraction 0.029617 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.970383 # Percentage of idle cycles
system.cpu1.Branches 93317418 # Number of branches fetched
system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu 340283943 69.22% 69.22% # Class of executed instruction
system.cpu1.op_class::IntMult 1041145 0.21% 69.43% # Class of executed instruction
system.cpu1.op_class::IntDiv 48269 0.01% 69.44% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 69.44% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 69.44% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 69.44% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 69.44% # Class of executed instruction
system.cpu1.op_class::FloatDiv 0 0.00% 69.44% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 69.44% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 69.44% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 69.44% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 69.44% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 69.44% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 69.44% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 69.44% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 69.44% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 69.44% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 69.44% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.44% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 69.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 4 0.00% 69.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 2 0.00% 69.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 5 0.00% 69.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 58327 0.01% 69.45% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 69.45% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.45% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.45% # Class of executed instruction
system.cpu1.op_class::MemRead 78657446 16.00% 85.45% # Class of executed instruction
system.cpu1.op_class::MemWrite 71530128 14.55% 100.00% # Class of executed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu1.op_class::total 491619269 # Class of executed instruction
system.iobus.trans_dist::ReadReq 40338 # Transaction distribution
system.iobus.trans_dist::ReadResp 40338 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231034 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 231034 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iobus.pkt_count::total 353818 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334568 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7334568 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iobus.pkt_size::total 7492488 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 42145500 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer2.occupancy 323000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer4.occupancy 11000 # Layer occupancy (ticks)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer10.occupancy 11000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer16.occupancy 17000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer23.occupancy 25719500 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer24.occupancy 38601500 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer25.occupancy 566847151 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iobus.respLayer3.occupancy 147794000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iocache.tags.replacements 115499 # number of replacements
system.iocache.tags.tagsinuse 10.451110 # Cycle average of tags in use
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iocache.tags.sampled_refs 115515 # Sample count of references to valid blocks.
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iocache.tags.warmup_cycle 13171691140000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 3.508460 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 6.942650 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.219279 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.433916 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.653194 # Average percentage of cache occupancy
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iocache.tags.tag_accesses 1040010 # Number of tag accesses
system.iocache.tags.data_accesses 1040010 # Number of data accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iocache.ReadReq_misses::realview.ide 8853 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8890 # number of ReadReq misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iocache.demand_misses::realview.ide 8853 # number of demand (read+write) misses
system.iocache.demand_misses::total 8893 # number of demand (read+write) misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iocache.overall_misses::realview.ide 8853 # number of overall misses
system.iocache.overall_misses::total 8893 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet 5070500 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide 1618419141 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 1623489641 # number of ReadReq miss cycles
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iocache.WriteLineReq_miss_latency::realview.ide 13411968510 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 13411968510 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet 5421500 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide 1618419141 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 1623840641 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet 5421500 # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide 1618419141 # number of overall miss cycles
system.iocache.overall_miss_latency::total 1623840641 # number of overall miss cycles
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iocache.ReadReq_accesses::realview.ide 8853 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8890 # number of ReadReq accesses(hits+misses)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iocache.demand_accesses::realview.ide 8853 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 8893 # number of demand (read+write) accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iocache.overall_accesses::realview.ide 8853 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 8893 # number of overall (read+write) accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137040.540541 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 182810.249746 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 182619.757143 # average ReadReq miss latency
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125740.348290 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 125740.348290 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 182810.249746 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 182597.620713 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 182810.249746 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 182597.620713 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 31642 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iocache.blocked::no_mshrs 3353 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iocache.avg_blocked_cycles::no_mshrs 9.436922 # average number of cycles each access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.cache_copies 0 # number of cache copies performed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.writebacks::writebacks 106631 # number of writebacks
system.iocache.writebacks::total 106631 # number of writebacks
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iocache.ReadReq_mshr_misses::realview.ide 8853 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 8890 # number of ReadReq MSHR misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iocache.demand_mshr_misses::realview.ide 8853 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 8893 # number of demand (read+write) MSHR misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iocache.overall_mshr_misses::realview.ide 8853 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 8893 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220500 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1175769141 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 1178989641 # number of ReadReq MSHR miss cycles
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8073599158 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 8073599158 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet 3421500 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 1175769141 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 1179190641 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet 3421500 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 1175769141 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 1179190641 # number of overall MSHR miss cycles
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87040.540541 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132810.249746 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 132619.757143 # average ReadReq mshr miss latency
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75691.884403 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75691.884403 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 132810.249746 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 132597.620713 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 132810.249746 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 132597.620713 # average overall mshr miss latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.l2c.tags.replacements 1026360 # number of replacements
system.l2c.tags.tagsinuse 65258.201118 # Cycle average of tags in use
system.l2c.tags.total_refs 41749797 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 1088957 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 38.339252 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 12386120500 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 37949.534950 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 104.286779 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 159.329733 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 4753.488207 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 9126.220322 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 118.614839 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 183.809686 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 3411.314898 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 9451.601704 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.579064 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001591 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.002431 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.072532 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.139255 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001810 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.002805 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.052053 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.144220 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.995761 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023 220 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 62377 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 220 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 392 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 2461 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 5447 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 54048 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.003357 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.951797 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 372663502 # Number of tag accesses
system.l2c.tags.data_accesses 372663502 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 212373 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 162936 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 207984 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 157286 # number of ReadReq hits
system.l2c.ReadReq_hits::total 740579 # number of ReadReq hits
system.l2c.WritebackDirty_hits::writebacks 7311510 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 7311510 # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks 13309724 # number of WritebackClean hits
system.l2c.WritebackClean_hits::total 13309724 # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data 4522 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 4435 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 8957 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 815767 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 776062 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 1591829 # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst 6641663 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst 6598566 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total 13240229 # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 3014297 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 2962809 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 5977106 # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data 376322 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data 363170 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total 739492 # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker 212373 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 162936 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 6641663 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 3830064 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 207984 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 157286 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 6598566 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 3738871 # number of demand (read+write) hits
system.l2c.demand_hits::total 21549743 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 212373 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 162936 # number of overall hits
system.l2c.overall_hits::cpu0.inst 6641663 # number of overall hits
system.l2c.overall_hits::cpu0.data 3830064 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 207984 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 157286 # number of overall hits
system.l2c.overall_hits::cpu1.inst 6598566 # number of overall hits
system.l2c.overall_hits::cpu1.data 3738871 # number of overall hits
system.l2c.overall_hits::total 21549743 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 1170 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 1257 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 1193 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker 1217 # number of ReadReq misses
system.l2c.ReadReq_misses::total 4837 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 16637 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 16471 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 33108 # number of UpgradeReq misses
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.l2c.ReadExReq_misses::cpu0.data 164166 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 170807 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 334973 # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst 35751 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst 35817 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total 71568 # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 113964 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 110564 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 224528 # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data 239615 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data 241699 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total 481314 # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker 1170 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 1257 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 35751 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 278130 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 1193 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 1217 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 35817 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 281371 # number of demand (read+write) misses
system.l2c.demand_misses::total 635906 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 1170 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 1257 # number of overall misses
system.l2c.overall_misses::cpu0.inst 35751 # number of overall misses
system.l2c.overall_misses::cpu0.data 278130 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 1193 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 1217 # number of overall misses
system.l2c.overall_misses::cpu1.inst 35817 # number of overall misses
system.l2c.overall_misses::cpu1.data 281371 # number of overall misses
system.l2c.overall_misses::total 635906 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 158334000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 173858500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 161742000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker 169455500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 663390000 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 664049000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 658035500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 1322084500 # number of UpgradeReq miss cycles
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 77500 # number of SCUpgradeReq miss cycles
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 79500 # number of SCUpgradeReq miss cycles
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.l2c.SCUpgradeReq_miss_latency::total 157000 # number of SCUpgradeReq miss cycles
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.l2c.ReadExReq_miss_latency::cpu0.data 21519096500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 22411791000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 43930887500 # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst 4720674000 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 4748397000 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total 9469071000 # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data 15191781000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data 14765909500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 29957690500 # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu0.data 155000 # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data 387500 # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total 542500 # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 158334000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 173858500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 4720674000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 36710877500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 161742000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker 169455500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 4748397000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 37177700500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 84021039000 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 158334000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 173858500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 4720674000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 36710877500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 161742000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker 169455500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 4748397000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 37177700500 # number of overall miss cycles
system.l2c.overall_miss_latency::total 84021039000 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 213543 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 164193 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 209177 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 158503 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 745416 # number of ReadReq accesses(hits+misses)
system.l2c.WritebackDirty_accesses::writebacks 7311510 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 7311510 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks 13309724 # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total 13309724 # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 21159 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 20906 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 42065 # number of UpgradeReq accesses(hits+misses)
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.l2c.SCUpgradeReq_accesses::cpu0.data 1 # number of SCUpgradeReq accesses(hits+misses)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.l2c.SCUpgradeReq_accesses::cpu1.data 1 # number of SCUpgradeReq accesses(hits+misses)
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.l2c.ReadExReq_accesses::cpu0.data 979933 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 946869 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 1926802 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst 6677414 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst 6634383 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total 13311797 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 3128261 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 3073373 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 6201634 # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data 615937 # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data 604869 # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total 1220806 # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 213543 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 164193 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 6677414 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 4108194 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 209177 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 158503 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 6634383 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 4020242 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 22185649 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 213543 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 164193 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 6677414 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 4108194 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 209177 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 158503 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 6634383 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 4020242 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 22185649 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.005479 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.007656 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.005703 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.007678 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.006489 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.786285 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.787860 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.787068 # miss rate for UpgradeReq accesses
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.l2c.ReadExReq_miss_rate::cpu0.data 0.167528 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.180391 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.173849 # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.005354 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.005399 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total 0.005376 # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.036430 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.035975 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.036205 # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data 0.389025 # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data 0.399589 # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total 0.394259 # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.005479 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.007656 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.005354 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.067701 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.005703 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker 0.007678 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.005399 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.069989 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.028663 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.005479 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.007656 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.005354 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.067701 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.005703 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker 0.007678 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.005399 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.069989 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.028663 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 135328.205128 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 138312.251392 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 135575.859179 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 139240.345111 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 137149.059334 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 39913.986897 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 39951.156578 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 39932.478555 # average UpgradeReq miss latency
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 77500 # average SCUpgradeReq miss latency
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 79500 # average SCUpgradeReq miss latency
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.l2c.SCUpgradeReq_avg_miss_latency::total 78500 # average SCUpgradeReq miss latency
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 131081.323173 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 131211.197433 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 131147.547713 # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 132043.131661 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 132573.833654 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 132308.727364 # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 133303.332631 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 133550.789588 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 133425.187504 # average ReadSharedReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 0.646871 # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 1.603234 # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::total 1.127123 # average InvalidateReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 135328.205128 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 138312.251392 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 132043.131661 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 131991.793406 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 135575.859179 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 139240.345111 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 132573.833654 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 132130.534064 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 132128.080251 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 135328.205128 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 138312.251392 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 132043.131661 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 131991.793406 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 135575.859179 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 139240.345111 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 132573.833654 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 132130.534064 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 132128.080251 # average overall miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.l2c.writebacks::writebacks 872147 # number of writebacks
system.l2c.writebacks::total 872147 # number of writebacks
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1170 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1257 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1193 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1217 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 4837 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 16637 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 16471 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 33108 # number of UpgradeReq MSHR misses
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1 # number of SCUpgradeReq MSHR misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1 # number of SCUpgradeReq MSHR misses
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.l2c.ReadExReq_mshr_misses::cpu0.data 164166 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 170807 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 334973 # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 35751 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 35817 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total 71568 # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data 113964 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 110564 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total 224528 # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu0.data 239615 # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data 241699 # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total 481314 # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker 1170 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker 1257 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 35751 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 278130 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 1193 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker 1217 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 35817 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 281371 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 635906 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker 1170 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker 1257 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 35751 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 278130 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 1193 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker 1217 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 35817 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 281371 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 635906 # number of overall MSHR misses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 22062 # number of ReadReq MSHR uncacheable
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.l2c.ReadReq_mshr_uncacheable::cpu0.data 17141 # number of ReadReq MSHR uncacheable
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 21063 # number of ReadReq MSHR uncacheable
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 16563 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total 76829 # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data 18220 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 15489 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total 33709 # number of WriteReq MSHR uncacheable
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 22062 # number of overall MSHR uncacheable misses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.l2c.overall_mshr_uncacheable_misses::cpu0.data 35361 # number of overall MSHR uncacheable misses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 21063 # number of overall MSHR uncacheable misses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 32052 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total 110538 # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 146634000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 161288500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 149812000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 157285500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 615020000 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1130206500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 1118915500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 2249122000 # number of UpgradeReq MSHR miss cycles
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 67500 # number of SCUpgradeReq MSHR miss cycles
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 69500 # number of SCUpgradeReq MSHR miss cycles
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.l2c.SCUpgradeReq_mshr_miss_latency::total 137000 # number of SCUpgradeReq MSHR miss cycles
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 19877436500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 20703721000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 40581157500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 4363164000 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 4390227000 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total 8753391000 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 14052033216 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 13660158223 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 27712191439 # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 16209692000 # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 16355100000 # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total 32564792000 # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 146634000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 161288500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 4363164000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 33929469716 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 149812000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 157285500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 4390227000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 34363879223 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 77661759939 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 146634000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 161288500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 4363164000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 33929469716 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 149812000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 157285500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 4390227000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 34363879223 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 77661759939 # number of overall MSHR miss cycles
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2504816500 # number of ReadReq MSHR uncacheable cycles
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2965958000 # number of ReadReq MSHR uncacheable cycles
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2392920500 # number of ReadReq MSHR uncacheable cycles
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2811531000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 10675226000 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3119505500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2710506500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 5830012000 # number of WriteReq MSHR uncacheable cycles
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2504816500 # number of overall MSHR uncacheable cycles
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6085463500 # number of overall MSHR uncacheable cycles
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2392920500 # number of overall MSHR uncacheable cycles
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5522037500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 16505238000 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.005479 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.007656 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.005703 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.007678 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.006489 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.786285 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.787860 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.787068 # mshr miss rate for UpgradeReq accesses
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.l2c.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.167528 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.180391 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.173849 # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.005354 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005399 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.005376 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.036430 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.035975 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.036205 # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.389025 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.399589 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total 0.394259 # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.005479 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.007656 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005354 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.067701 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.005703 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.007678 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005399 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.069989 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.028663 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.005479 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.007656 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005354 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.067701 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.005703 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.007678 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005399 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.069989 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.028663 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 125328.205128 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 128312.251392 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 125575.859179 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 129240.345111 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 127149.059334 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 67933.311294 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 67932.457046 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 67932.886311 # average UpgradeReq mshr miss latency
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 67500 # average SCUpgradeReq mshr miss latency
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 69500 # average SCUpgradeReq mshr miss latency
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68500 # average SCUpgradeReq mshr miss latency
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 121081.323173 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121211.197433 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 121147.547713 # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 122043.131661 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122573.833654 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 122308.727364 # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 123302.386859 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 123549.783139 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 123424.211853 # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 67648.903449 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 67667.222454 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 67658.102611 # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 125328.205128 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128312.251392 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122043.131661 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 121991.405875 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 125575.859179 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 129240.345111 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122573.833654 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 122130.138582 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 122127.735764 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 125328.205128 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128312.251392 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122043.131661 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 121991.405875 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 125575.859179 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 129240.345111 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122573.833654 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 122130.138582 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 122127.735764 # average overall mshr miss latency
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113535.332245 # average ReadReq mshr uncacheable latency
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 173032.961904 # average ReadReq mshr uncacheable latency
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 113607.771922 # average ReadReq mshr uncacheable latency
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169747.690636 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 138947.871247 # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171213.254665 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174995.577507 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172951.199976 # average WriteReq mshr uncacheable latency
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113535.332245 # average overall mshr uncacheable latency
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 172095.345154 # average overall mshr uncacheable latency
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 113607.771922 # average overall mshr uncacheable latency
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 172283.710845 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 149317.320740 # average overall mshr uncacheable latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.membus.trans_dist::ReadReq 76829 # Transaction distribution
system.membus.trans_dist::ReadResp 386652 # Transaction distribution
system.membus.trans_dist::WriteReq 33709 # Transaction distribution
system.membus.trans_dist::WriteResp 33709 # Transaction distribution
system.membus.trans_dist::WritebackDirty 978778 # Transaction distribution
system.membus.trans_dist::CleanEvict 162070 # Transaction distribution
system.membus.trans_dist::UpgradeReq 33685 # Transaction distribution
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
system.membus.trans_dist::UpgradeResp 7 # Transaction distribution
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.membus.trans_dist::ReadExReq 334406 # Transaction distribution
system.membus.trans_dist::ReadExResp 334406 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 309823 # Transaction distribution
system.membus.trans_dist::InvalidateReq 587971 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6936 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2901743 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 3031441 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237241 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 237241 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 3268682 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13872 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 96630432 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 96800270 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7220224 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7220224 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 104020494 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 3365 # Total snoops (count)
system.membus.snoop_fanout::samples 2517308 # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.membus.snoop_fanout::1 2517308 100.00% 100.00% # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.membus.snoop_fanout::total 2517308 # Request fanout histogram
system.membus.reqLayer0.occupancy 106894000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.membus.reqLayer2.occupancy 5659000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.membus.reqLayer5.occupancy 6490935886 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.membus.respLayer2.occupancy 3578419285 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.membus.respLayer3.occupancy 44788681 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: Update to reflect changes to RealView platform code
2015-12-04 01:19:05 +01:00
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 18 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
stats: Update to reflect changes to RealView platform code
2015-12-04 01:19:05 +01:00
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.toL2Bus.snoop_filter.tot_requests 45897959 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 23236926 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 1749 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 2692 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 2692 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.toL2Bus.trans_dist::ReadReq 1189053 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 20703336 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 33709 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 33709 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 8290323 # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean 13311280 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 2200261 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 42068 # Transaction distribution
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.toL2Bus.trans_dist::UpgradeResp 42070 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 1926802 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 1926802 # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq 13311797 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 6210524 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 1327470 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp 1220806 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 40021124 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 28266989 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 766613 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1091027 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 70145753 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1704049428 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 988401530 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2581568 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3381760 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 2698414286 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 1625114 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 25183319 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.021416 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.144767 # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.toL2Bus.snoop_fanout::0 24643989 97.86% 97.86% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 539330 2.14% 100.00% # Request fanout histogram
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.toL2Bus.snoop_fanout::total 25183319 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 43932563500 # Layer occupancy (ticks)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.toL2Bus.snoopLayer0.occupancy 1579898 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.toL2Bus.respLayer0.occupancy 20010820500 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.toL2Bus.respLayer1.occupancy 12874657982 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.toL2Bus.respLayer2.occupancy 443917000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.toL2Bus.respLayer3.occupancy 668307000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
---------- End Simulation Statistics ----------
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