2014-10-30 05:50:15 +01:00
---------- Begin Simulation Statistics ----------
2016-02-24 10:16:59 +01:00
sim_seconds 51.327140 # Number of seconds simulated
sim_ticks 51327140089000 # Number of ticks simulated
final_tick 51327140089000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2014-10-30 05:50:15 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-02-24 10:16:59 +01:00
host_inst_rate 155840 # Simulator instruction rate (inst/s)
host_op_rate 183117 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 9430836418 # Simulator tick rate (ticks/s)
host_mem_usage 687516 # Number of bytes of host memory used
host_seconds 5442.48 # Real time elapsed on the host
sim_insts 848158120 # Number of instructions simulated
sim_ops 996609834 # Number of ops (including micro ops) simulated
2014-10-30 05:50:15 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2016-02-24 10:16:59 +01:00
system.physmem.bytes_read::cpu.dtb.walker 211968 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 207872 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 5637664 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 41611720 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 447104 # Number of bytes read from this memory
system.physmem.bytes_read::total 48116328 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 5637664 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 5637664 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 68318336 # Number of bytes written to this memory
2014-12-02 12:08:25 +01:00
system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
2016-02-24 10:16:59 +01:00
system.physmem.bytes_written::total 68338916 # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker 3312 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 3248 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 104041 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 650196 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6986 # Number of read requests responded to by this memory
system.physmem.num_reads::total 767783 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1067474 # Number of write requests responded to by this memory
2014-12-02 12:08:25 +01:00
system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
2016-02-24 10:16:59 +01:00
system.physmem.num_writes::total 1070047 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker 4130 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 4050 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 109838 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 810716 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 8711 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 937444 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 109838 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 109838 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1331037 # Write bandwidth from this memory (bytes/s)
2015-09-25 13:27:03 +02:00
system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s)
2016-02-24 10:16:59 +01:00
system.physmem.bw_write::total 1331438 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1331037 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 4130 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 4050 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 109838 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 811117 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 8711 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2268882 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 767783 # Number of read requests accepted
system.physmem.writeReqs 1070047 # Number of write requests accepted
system.physmem.readBursts 767783 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1070047 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 49097152 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 40960 # Total number of bytes read from write queue
system.physmem.bytesWritten 68336896 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 48116328 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 68338916 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 640 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 2264 # Number of DRAM write bursts merged with an existing one
2016-02-10 10:08:27 +01:00
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2016-02-24 10:16:59 +01:00
system.physmem.perBankRdBursts::0 44980 # Per bank write bursts
system.physmem.perBankRdBursts::1 51602 # Per bank write bursts
system.physmem.perBankRdBursts::2 47368 # Per bank write bursts
system.physmem.perBankRdBursts::3 43602 # Per bank write bursts
system.physmem.perBankRdBursts::4 45132 # Per bank write bursts
system.physmem.perBankRdBursts::5 50541 # Per bank write bursts
system.physmem.perBankRdBursts::6 45264 # Per bank write bursts
system.physmem.perBankRdBursts::7 48215 # Per bank write bursts
system.physmem.perBankRdBursts::8 45181 # Per bank write bursts
system.physmem.perBankRdBursts::9 71916 # Per bank write bursts
system.physmem.perBankRdBursts::10 43746 # Per bank write bursts
system.physmem.perBankRdBursts::11 51986 # Per bank write bursts
system.physmem.perBankRdBursts::12 43936 # Per bank write bursts
system.physmem.perBankRdBursts::13 46943 # Per bank write bursts
system.physmem.perBankRdBursts::14 42923 # Per bank write bursts
system.physmem.perBankRdBursts::15 43808 # Per bank write bursts
system.physmem.perBankWrBursts::0 64378 # Per bank write bursts
system.physmem.perBankWrBursts::1 68822 # Per bank write bursts
system.physmem.perBankWrBursts::2 67360 # Per bank write bursts
system.physmem.perBankWrBursts::3 65401 # Per bank write bursts
system.physmem.perBankWrBursts::4 67058 # Per bank write bursts
system.physmem.perBankWrBursts::5 69359 # Per bank write bursts
system.physmem.perBankWrBursts::6 64813 # Per bank write bursts
system.physmem.perBankWrBursts::7 68136 # Per bank write bursts
system.physmem.perBankWrBursts::8 65855 # Per bank write bursts
system.physmem.perBankWrBursts::9 70723 # Per bank write bursts
system.physmem.perBankWrBursts::10 64194 # Per bank write bursts
system.physmem.perBankWrBursts::11 71056 # Per bank write bursts
system.physmem.perBankWrBursts::12 64787 # Per bank write bursts
system.physmem.perBankWrBursts::13 67120 # Per bank write bursts
system.physmem.perBankWrBursts::14 64460 # Per bank write bursts
system.physmem.perBankWrBursts::15 64242 # Per bank write bursts
2014-10-30 05:50:15 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
2016-02-24 10:16:59 +01:00
system.physmem.numWrRetry 33 # Number of times write queue was full causing retry
system.physmem.totGap 51327138675500 # Total gap between requests
2014-10-30 05:50:15 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 13 # Read request sizes (log2)
system.physmem.readPktSize::4 21272 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2016-02-24 10:16:59 +01:00
system.physmem.readPktSize::6 746498 # Read request sizes (log2)
2014-10-30 05:50:15 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 1 # Write request sizes (log2)
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2016-02-24 10:16:59 +01:00
system.physmem.writePktSize::6 1067474 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 514277 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 203743 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 30358 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 13038 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 584 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 588 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 567 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1290 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 814 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 357 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 374 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 174 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 171 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 141 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 138 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 135 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 118 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 111 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 96 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 63 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
2014-10-30 05:50:15 +01:00
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
2016-02-24 10:16:59 +01:00
system.physmem.wrQLenPdf::15 26644 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 32364 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 49179 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 54414 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 60551 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 60830 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 61808 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 61874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 61855 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 69991 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 63900 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 76806 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 62055 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 64795 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 68451 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 60364 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 58974 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 57166 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 3220 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 1478 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 1170 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 1018 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 1079 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 849 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 677 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 559 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 604 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 463 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 384 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 371 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 342 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 360 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 309 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 305 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 273 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 269 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 242 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 279 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 189 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 162 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 150 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 159 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 123 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 163 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 93 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 140 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 181 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 56 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 80 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 471185 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 249.230345 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 149.487407 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 290.645433 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 207601 44.06% 44.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 122052 25.90% 69.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 43152 9.16% 79.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 22522 4.78% 83.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 14798 3.14% 87.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 9568 2.03% 89.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 7612 1.62% 90.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 6084 1.29% 91.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 37796 8.02% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 471185 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 54136 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 14.170570 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 76.787361 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511 54130 99.99% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-1023 3 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 54136 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 54136 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 19.723733 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.769647 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 8.988954 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 40635 75.06% 75.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 4496 8.31% 83.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 5195 9.60% 92.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 1325 2.45% 95.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 409 0.76% 96.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 232 0.43% 96.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 326 0.60% 97.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 142 0.26% 97.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 398 0.74% 98.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 127 0.23% 98.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 56 0.10% 98.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 67 0.12% 98.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 319 0.59% 99.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 37 0.07% 99.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 24 0.04% 99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 111 0.21% 99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 168 0.31% 99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 2 0.00% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 3 0.01% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 3 0.01% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 2 0.00% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 5 0.01% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 1 0.00% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 2 0.00% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119 3 0.01% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 2 0.00% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 1 0.00% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 11 0.02% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139 1 0.00% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 5 0.01% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 17 0.03% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 2 0.00% 99.98% # Writes before turning the bus around for reads
2016-02-10 10:08:27 +01:00
system.physmem.wrPerTurnAround::160-163 2 0.00% 99.99% # Writes before turning the bus around for reads
2016-02-24 10:16:59 +01:00
system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179 4 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-211 2 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 54136 # Writes before turning the bus around for reads
system.physmem.totQLat 15242803686 # Total ticks spent queuing
system.physmem.totMemAccLat 29626734936 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 3835715000 # Total ticks spent in databus transfers
system.physmem.avgQLat 19869.57 # Average queueing delay per DRAM burst
2014-10-30 05:50:15 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2016-02-24 10:16:59 +01:00
system.physmem.avgMemAccLat 38619.57 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 0.96 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.33 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 0.94 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.33 # Average system write bandwidth in MiByte/s
2014-10-30 05:50:15 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2015-09-25 13:27:03 +02:00
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
2016-02-24 10:16:59 +01:00
system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing
system.physmem.avgWrQLen 23.33 # Average write queue length when enqueuing
system.physmem.readRowHits 579803 # Number of row buffer hits during reads
system.physmem.writeRowHits 783916 # Number of row buffer hits during writes
system.physmem.readRowHitRate 75.58 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 73.42 # Row buffer hit rate for writes
system.physmem.avgGap 27928121.03 # Average gap between requests
system.physmem.pageHitRate 74.32 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 1791077400 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 977274375 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 2938244400 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 3468841200 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3352439216880 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1235175473835 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 29712796340250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 34309586468340 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.449224 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 49429866192554 # Time in different power states
system.physmem_0.memoryStateTime::REF 1713925980000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-02-24 10:16:59 +01:00
system.physmem_0.memoryStateTime::ACT 183347171196 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2016-02-24 10:16:59 +01:00
system.physmem_1.actEnergy 1771020720 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 966330750 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 3045424200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 3450165840 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3352439216880 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 1235608843410 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 29712416191500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 34309697193300 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.451381 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 49429214230967 # Time in different power states
system.physmem_1.memoryStateTime::REF 1713925980000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-02-24 10:16:59 +01:00
system.physmem_1.memoryStateTime::ACT 183999255033 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-11-06 09:26:50 +01:00
system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
2015-11-06 09:26:50 +01:00
system.realview.nvmem.bytes_read::total 420 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 384 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 384 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
2014-10-30 05:50:15 +01:00
system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
2015-11-06 09:26:50 +01:00
system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s)
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
2015-10-10 23:45:41 +02:00
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
2015-11-06 09:26:50 +01:00
system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
2015-10-10 23:45:41 +02:00
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
2014-10-30 05:50:15 +01:00
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
2016-02-24 10:16:59 +01:00
system.cpu.branchPred.lookups 224297572 # Number of BP lookups
system.cpu.branchPred.condPredicted 149902957 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 12193787 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 158452721 # Number of BTB lookups
system.cpu.branchPred.BTBHits 103491021 # Number of BTB hits
2014-10-30 05:50:15 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2016-02-24 10:16:59 +01:00
system.cpu.branchPred.BTBHitPct 65.313502 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 30817326 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 343319 # Number of incorrect RAS predictions.
2014-12-02 12:08:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2014-12-23 15:31:20 +01:00
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-02-24 10:16:59 +01:00
system.cpu.checker.dtb.walker.walks 197812 # Table walker walks requested
system.cpu.checker.dtb.walker.walksLong 197812 # Table walker walks initiated with long descriptors
system.cpu.checker.dtb.walker.walkWaitTime::samples 197812 # Table walker wait (enqueue to first request) latency
system.cpu.checker.dtb.walker.walkWaitTime::0 197812 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.checker.dtb.walker.walkWaitTime::total 197812 # Table walker wait (enqueue to first request) latency
2015-11-06 09:26:50 +01:00
system.cpu.checker.dtb.walker.walksPending::samples -1584953796 # Table walker pending requests distribution
system.cpu.checker.dtb.walker.walksPending::0 -1584953796 100.00% 100.00% # Table walker pending requests distribution
system.cpu.checker.dtb.walker.walksPending::total -1584953796 # Table walker pending requests distribution
2016-02-24 10:16:59 +01:00
system.cpu.checker.dtb.walker.walkPageSizes::4K 154082 91.53% 91.53% # Table walker page sizes translated
system.cpu.checker.dtb.walker.walkPageSizes::2M 14256 8.47% 100.00% # Table walker page sizes translated
system.cpu.checker.dtb.walker.walkPageSizes::total 168338 # Table walker page sizes translated
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 197812 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2016-02-24 10:16:59 +01:00
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 197812 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 168338 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2016-02-24 10:16:59 +01:00
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 168338 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin::total 366150 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
2016-02-24 10:16:59 +01:00
system.cpu.checker.dtb.read_hits 159555068 # DTB read hits
system.cpu.checker.dtb.read_misses 147115 # DTB read misses
system.cpu.checker.dtb.write_hits 144752666 # DTB write hits
system.cpu.checker.dtb.write_misses 50697 # DTB write misses
2015-09-25 13:27:03 +02:00
system.cpu.checker.dtb.flush_tlb 20 # Number of times complete TLB was flushed
2014-10-30 05:50:15 +01:00
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2016-02-24 10:16:59 +01:00
system.cpu.checker.dtb.flush_tlb_mva_asid 78770 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid 2038 # Number of times TLB was flushed by ASID
system.cpu.checker.dtb.flush_entries 71773 # Number of entries that have been flushed from TLB
2014-10-30 05:50:15 +01:00
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
2016-02-24 10:16:59 +01:00
system.cpu.checker.dtb.prefetch_faults 6971 # Number of TLB faults due to prefetch
2014-10-30 05:50:15 +01:00
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-02-24 10:16:59 +01:00
system.cpu.checker.dtb.perms_faults 19053 # Number of TLB faults due to permissions restrictions
system.cpu.checker.dtb.read_accesses 159702183 # DTB read accesses
system.cpu.checker.dtb.write_accesses 144803363 # DTB write accesses
2014-10-30 05:50:15 +01:00
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
2016-02-24 10:16:59 +01:00
system.cpu.checker.dtb.hits 304307734 # DTB hits
system.cpu.checker.dtb.misses 197812 # DTB misses
system.cpu.checker.dtb.accesses 304505546 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-02-24 10:16:59 +01:00
system.cpu.checker.itb.walker.walks 119797 # Table walker walks requested
system.cpu.checker.itb.walker.walksLong 119797 # Table walker walks initiated with long descriptors
system.cpu.checker.itb.walker.walkWaitTime::samples 119797 # Table walker wait (enqueue to first request) latency
system.cpu.checker.itb.walker.walkWaitTime::0 119797 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.checker.itb.walker.walkWaitTime::total 119797 # Table walker wait (enqueue to first request) latency
2015-11-06 09:26:50 +01:00
system.cpu.checker.itb.walker.walksPending::samples -1586149296 # Table walker pending requests distribution
system.cpu.checker.itb.walker.walksPending::0 -1586149296 100.00% 100.00% # Table walker pending requests distribution
system.cpu.checker.itb.walker.walksPending::total -1586149296 # Table walker pending requests distribution
2016-02-24 10:16:59 +01:00
system.cpu.checker.itb.walker.walkPageSizes::4K 107938 98.83% 98.83% # Table walker page sizes translated
system.cpu.checker.itb.walker.walkPageSizes::2M 1280 1.17% 100.00% # Table walker page sizes translated
system.cpu.checker.itb.walker.walkPageSizes::total 109218 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2016-02-24 10:16:59 +01:00
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 119797 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 119797 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2016-02-24 10:16:59 +01:00
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 109218 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 109218 # Table walker requests started/completed, data/inst
2016-02-10 10:08:27 +01:00
system.cpu.checker.itb.walker.walkRequestOrigin::total 229015 # Table walker requests started/completed, data/inst
2016-02-24 10:16:59 +01:00
system.cpu.checker.itb.inst_hits 848564500 # ITB inst hits
system.cpu.checker.itb.inst_misses 119797 # ITB inst misses
2014-10-30 05:50:15 +01:00
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.write_hits 0 # DTB write hits
system.cpu.checker.itb.write_misses 0 # DTB write misses
2015-09-25 13:27:03 +02:00
system.cpu.checker.itb.flush_tlb 20 # Number of times complete TLB was flushed
2014-10-30 05:50:15 +01:00
system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2016-02-24 10:16:59 +01:00
system.cpu.checker.itb.flush_tlb_mva_asid 78770 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.itb.flush_tlb_asid 2038 # Number of times TLB was flushed by ASID
system.cpu.checker.itb.flush_entries 51743 # Number of entries that have been flushed from TLB
2014-10-30 05:50:15 +01:00
system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
2016-02-24 10:16:59 +01:00
system.cpu.checker.itb.inst_accesses 848684297 # ITB inst accesses
system.cpu.checker.itb.hits 848564500 # DTB hits
system.cpu.checker.itb.misses 119797 # DTB misses
system.cpu.checker.itb.accesses 848684297 # DTB accesses
system.cpu.checker.numCycles 997179136 # number of cpu cycles simulated
2014-10-30 05:50:15 +01:00
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
2014-12-23 15:31:20 +01:00
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-02-24 10:16:59 +01:00
system.cpu.dtb.walker.walks 949838 # Table walker walks requested
system.cpu.dtb.walker.walksLong 949838 # Table walker walks initiated with long descriptors
system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15818 # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksLongTerminationLevel::Level3 155419 # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksSquashedBefore 436827 # Table walks squashed before starting
system.cpu.dtb.walker.walkWaitTime::samples 513011 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::mean 2225.817770 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::stdev 14567.134273 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0-65535 509618 99.34% 99.34% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::65536-131071 1930 0.38% 99.71% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::131072-196607 987 0.19% 99.91% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::196608-262143 197 0.04% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::262144-327679 149 0.03% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::327680-393215 32 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::393216-458751 53 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::458752-524287 41 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::589824-655359 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total 513011 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples 485512 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 23036.801356 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 18084.539614 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 20755.830536 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-65535 474265 97.68% 97.68% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::65536-131071 7843 1.62% 99.30% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-196607 2427 0.50% 99.80% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::196608-262143 166 0.03% 99.83% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::262144-327679 551 0.11% 99.95% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::327680-393215 105 0.02% 99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::393216-458751 109 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::458752-524287 26 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::524288-589823 11 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::589824-655359 7 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total 485512 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples 779669132376 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::mean 0.722626 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::stdev 0.523315 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0-1 777439658376 99.71% 99.71% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::2-3 1176099000 0.15% 99.86% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::4-5 488850000 0.06% 99.93% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::6-7 205535000 0.03% 99.95% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::8-9 152105500 0.02% 99.97% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::10-11 121751500 0.02% 99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::12-13 29187500 0.00% 99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::14-15 53249500 0.01% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::16-17 2696000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total 779669132376 # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K 155420 90.76% 90.76% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::2M 15818 9.24% 100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total 171238 # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 949838 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2016-02-24 10:16:59 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 949838 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 171238 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2016-02-24 10:16:59 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 171238 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 1121076 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
2016-02-24 10:16:59 +01:00
system.cpu.dtb.read_hits 169331819 # DTB read hits
system.cpu.dtb.read_misses 674131 # DTB read misses
system.cpu.dtb.write_hits 147501461 # DTB write hits
system.cpu.dtb.write_misses 275707 # DTB write misses
2015-09-25 13:27:03 +02:00
system.cpu.dtb.flush_tlb 20 # Number of times complete TLB was flushed
2014-10-30 05:50:15 +01:00
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2016-02-24 10:16:59 +01:00
system.cpu.dtb.flush_tlb_mva_asid 78770 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 2038 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 72020 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 117 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 10130 # Number of TLB faults due to prefetch
2014-10-30 05:50:15 +01:00
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-02-24 10:16:59 +01:00
system.cpu.dtb.perms_faults 69829 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 170005950 # DTB read accesses
system.cpu.dtb.write_accesses 147777168 # DTB write accesses
2014-10-30 05:50:15 +01:00
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
2016-02-24 10:16:59 +01:00
system.cpu.dtb.hits 316833280 # DTB hits
system.cpu.dtb.misses 949838 # DTB misses
system.cpu.dtb.accesses 317783118 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-02-24 10:16:59 +01:00
system.cpu.itb.walker.walks 161333 # Table walker walks requested
system.cpu.itb.walker.walksLong 161333 # Table walker walks initiated with long descriptors
system.cpu.itb.walker.walksLongTerminationLevel::Level2 1433 # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksLongTerminationLevel::Level3 121604 # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksSquashedBefore 17607 # Table walks squashed before starting
system.cpu.itb.walker.walkWaitTime::samples 143726 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::mean 1329.870726 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::stdev 9693.373994 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0-32767 142645 99.25% 99.25% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::32768-65535 592 0.41% 99.66% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::65536-98303 67 0.05% 99.71% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::98304-131071 93 0.06% 99.77% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::131072-163839 270 0.19% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::163840-196607 24 0.02% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::196608-229375 6 0.00% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::229376-262143 5 0.00% 99.98% # Table walker wait (enqueue to first request) latency
2016-02-10 10:08:27 +01:00
system.cpu.itb.walker.walkWaitTime::262144-294911 15 0.01% 99.99% # Table walker wait (enqueue to first request) latency
2016-02-24 10:16:59 +01:00
system.cpu.itb.walker.walkWaitTime::294912-327679 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::360448-393215 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total 143726 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples 140644 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 29101.756918 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 24236.740283 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 22905.442201 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-65535 137486 97.75% 97.75% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::65536-131071 886 0.63% 98.38% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-196607 1961 1.39% 99.78% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::196608-262143 124 0.09% 99.87% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::262144-327679 124 0.09% 99.96% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::327680-393215 33 0.02% 99.98% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::393216-458751 20 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::458752-524287 7 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
2016-02-10 10:08:27 +01:00
system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
2016-02-24 10:16:59 +01:00
system.cpu.itb.walker.walkCompletionTime::total 140644 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples 672291747976 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::mean 0.944017 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::stdev 0.230261 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0 37693655356 5.61% 5.61% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::1 634541752620 94.38% 99.99% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::2 55651000 0.01% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::3 688000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::4 1000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total 672291747976 # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K 121604 98.84% 98.84% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::2M 1433 1.16% 100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total 123037 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2016-02-24 10:16:59 +01:00
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 161333 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 161333 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2016-02-24 10:16:59 +01:00
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 123037 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 123037 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 284370 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 356599136 # ITB inst hits
system.cpu.itb.inst_misses 161333 # ITB inst misses
2014-10-30 05:50:15 +01:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
2015-09-25 13:27:03 +02:00
system.cpu.itb.flush_tlb 20 # Number of times complete TLB was flushed
2014-10-30 05:50:15 +01:00
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2016-02-24 10:16:59 +01:00
system.cpu.itb.flush_tlb_mva_asid 78770 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 2038 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 53042 # Number of entries that have been flushed from TLB
2014-10-30 05:50:15 +01:00
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-02-24 10:16:59 +01:00
system.cpu.itb.perms_faults 369633 # Number of TLB faults due to permissions restrictions
2014-10-30 05:50:15 +01:00
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
2016-02-24 10:16:59 +01:00
system.cpu.itb.inst_accesses 356760469 # ITB inst accesses
system.cpu.itb.hits 356599136 # DTB hits
system.cpu.itb.misses 161333 # DTB misses
system.cpu.itb.accesses 356760469 # DTB accesses
system.cpu.numCycles 1628081885 # number of cpu cycles simulated
2014-10-30 05:50:15 +01:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-02-24 10:16:59 +01:00
system.cpu.fetch.icacheStallCycles 644023121 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1000825975 # Number of instructions fetch has processed
system.cpu.fetch.Branches 224297572 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 134308347 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 897356081 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 26042356 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 3815311 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles 27434 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 9297529 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 1037208 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 977 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 356212596 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 6096332 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 48851 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 1568578839 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.747604 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.149571 # Number of instructions fetched each cycle (Total)
2014-10-30 05:50:15 +01:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2016-02-24 10:16:59 +01:00
system.cpu.fetch.rateDist::0 1011708684 64.50% 64.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 213717515 13.62% 78.12% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 70499052 4.49% 82.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 272653588 17.38% 100.00% # Number of instructions fetched each cycle (Total)
2014-10-30 05:50:15 +01:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
2016-02-24 10:16:59 +01:00
system.cpu.fetch.rateDist::total 1568578839 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.137768 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.614727 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 523834599 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 552751170 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 433009950 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 49764409 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 9218711 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 33629126 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 3862659 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 1084582874 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 28977480 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 9218711 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 568372766 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 66217937 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 371830406 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 438295981 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 114643038 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 1064838864 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 6775021 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 5115924 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 336846 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 638712 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 63601510 # Number of times rename has blocked due to SQ full
system.cpu.rename.FullRegisterEvents 20546 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 1012729668 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 1640391275 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1259385666 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 1476745 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 947192806 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 65536859 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 26910765 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 23247835 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 101832167 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 173436334 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 151069277 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 9864131 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 8951241 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 1029826470 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 27204925 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1045231227 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 3279121 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 60421557 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 33664917 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 313528 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1568578839 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.666356 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 0.920348 # Number of insts issued each cycle
2014-10-30 05:50:15 +01:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2016-02-24 10:16:59 +01:00
system.cpu.iq.issued_per_cycle::0 921654762 58.76% 58.76% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 333747896 21.28% 80.03% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 234544221 14.95% 94.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 72152324 4.60% 99.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 6460263 0.41% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 19373 0.00% 100.00% # Number of insts issued each cycle
2014-10-30 05:50:15 +01:00
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
2016-02-24 10:16:59 +01:00
system.cpu.iq.issued_per_cycle::total 1568578839 # Number of insts issued each cycle
2014-10-30 05:50:15 +01:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2016-02-24 10:16:59 +01:00
system.cpu.iq.fu_full::IntAlu 57742950 35.03% 35.03% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 99825 0.06% 35.09% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 26740 0.02% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 625 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 44231739 26.83% 61.94% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 62727458 38.06% 100.00% # attempts to use FU when none available
2014-10-30 05:50:15 +01:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2016-02-24 10:16:59 +01:00
system.cpu.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 719843938 68.87% 68.87% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 2535420 0.24% 69.11% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 122954 0.01% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 380 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 121377 0.01% 69.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.14% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 173211987 16.57% 85.71% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 149395124 14.29% 100.00% # Type of FU issued
2014-10-30 05:50:15 +01:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2016-02-24 10:16:59 +01:00
system.cpu.iq.FU_type_0::total 1045231227 # Type of FU issued
system.cpu.iq.rate 0.642002 # Inst issue rate
system.cpu.iq.fu_busy_cnt 164829337 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.157697 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 3824665950 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 1116644145 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1027372601 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 2483800 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 950168 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 912054 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1208499896 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 1560667 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 4304106 # Number of loads that had data forwarded from stores
2014-10-30 05:50:15 +01:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2016-02-24 10:16:59 +01:00
system.cpu.iew.lsq.thread0.squashedLoads 13785862 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 14456 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 142604 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 6312817 # Number of stores squashed
2014-10-30 05:50:15 +01:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2016-02-24 10:16:59 +01:00
system.cpu.iew.lsq.thread0.rescheduledLoads 2532139 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 1442341 # Number of times an access to memory failed due to the cache being blocked
2014-10-30 05:50:15 +01:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2016-02-24 10:16:59 +01:00
system.cpu.iew.iewSquashCycles 9218711 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 7060342 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 6923682 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 1057253447 # Number of instructions dispatched to IQ
2014-10-30 05:50:15 +01:00
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2016-02-24 10:16:59 +01:00
system.cpu.iew.iewDispLoadInsts 173436334 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 151069277 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 22822922 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 57401 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 6792645 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 142604 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 3655399 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 5100784 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 8756183 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1034064574 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 169319677 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 10227871 # Number of squashed instructions skipped in execute
2014-10-30 05:50:15 +01:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
2016-02-24 10:16:59 +01:00
system.cpu.iew.exec_nop 222052 # number of nop insts executed
system.cpu.iew.exec_refs 316816486 # number of memory reference insts executed
system.cpu.iew.exec_branches 196206176 # Number of branches executed
system.cpu.iew.exec_stores 147496809 # Number of stores executed
system.cpu.iew.exec_rate 0.635143 # Inst execution rate
system.cpu.iew.wb_sent 1029092840 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1028284655 # cumulative count of insts written-back
system.cpu.iew.wb_producers 437786008 # num instructions producing a value
system.cpu.iew.wb_consumers 708231099 # num instructions consuming a value
system.cpu.iew.wb_rate 0.631593 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.618140 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 51332329 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 26891397 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 8391320 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1556613982 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.640242 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.274821 # Number of insts commited each cycle
2014-10-30 05:50:15 +01:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2016-02-24 10:16:59 +01:00
system.cpu.commit.committed_per_cycle::0 1044975044 67.13% 67.13% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 287768132 18.49% 85.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 120346121 7.73% 93.35% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 36551788 2.35% 95.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 28453995 1.83% 97.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 14010396 0.90% 98.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 8635881 0.55% 98.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 4170150 0.27% 99.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 11702475 0.75% 100.00% # Number of insts commited each cycle
2014-10-30 05:50:15 +01:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2016-02-24 10:16:59 +01:00
system.cpu.commit.committed_per_cycle::total 1556613982 # Number of insts commited each cycle
system.cpu.commit.committedInsts 848158120 # Number of instructions committed
system.cpu.commit.committedOps 996609834 # Number of ops (including micro ops) committed
2014-10-30 05:50:15 +01:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
2016-02-24 10:16:59 +01:00
system.cpu.commit.refs 304406931 # Number of memory references committed
system.cpu.commit.loads 159650471 # Number of loads committed
system.cpu.commit.membars 6926449 # Number of memory barriers committed
system.cpu.commit.branches 189300112 # Number of branches committed
system.cpu.commit.fp_insts 898776 # Number of committed floating point instructions.
system.cpu.commit.int_insts 915651780 # Number of committed integer instructions.
system.cpu.commit.function_calls 25280403 # Number of function calls committed.
2014-10-30 05:50:15 +01:00
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2016-02-24 10:16:59 +01:00
system.cpu.commit.op_class_0::IntAlu 689842559 69.22% 69.22% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 2150231 0.22% 69.43% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 98139 0.01% 69.44% # Class of committed instruction
2016-02-10 10:08:27 +01:00
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.44% # Class of committed instruction
2016-02-24 10:16:59 +01:00
system.cpu.commit.op_class_0::SimdFloatMisc 111932 0.01% 69.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 159650471 16.02% 85.48% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 144756460 14.52% 100.00% # Class of committed instruction
2014-10-30 05:50:15 +01:00
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2016-02-24 10:16:59 +01:00
system.cpu.commit.op_class_0::total 996609834 # Class of committed instruction
system.cpu.commit.bw_lim_events 11702475 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 2585312705 # The number of ROB reads
system.cpu.rob.rob_writes 2107755396 # The number of ROB writes
system.cpu.timesIdled 8146940 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 59503046 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 101026198411 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 848158120 # Number of Instructions Simulated
system.cpu.committedOps 996609834 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 1.919550 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.919550 # CPI: Total CPI of All Threads
system.cpu.ipc 0.520955 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.520955 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 1224113620 # number of integer regfile reads
system.cpu.int_regfile_writes 731134071 # number of integer regfile writes
system.cpu.fp_regfile_reads 1465257 # number of floating regfile reads
system.cpu.fp_regfile_writes 785096 # number of floating regfile writes
system.cpu.cc_regfile_reads 225210240 # number of cc regfile reads
system.cpu.cc_regfile_writes 225863400 # number of cc regfile writes
system.cpu.misc_regfile_reads 2555640420 # number of misc regfile reads
system.cpu.misc_regfile_writes 26930775 # number of misc regfile writes
system.cpu.dcache.tags.replacements 9682749 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.972800 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 283083620 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 9683261 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 29.234327 # Average number of references to valid blocks.
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.warmup_cycle 2743199500 # Cycle when the warmup percentage was hit.
2016-02-24 10:16:59 +01:00
system.cpu.dcache.tags.occ_blocks::cpu.data 511.972800 # Average occupied blocks per requestor
2015-09-25 13:27:03 +02:00
system.cpu.dcache.tags.occ_percent::cpu.data 0.999947 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999947 # Average percentage of cache occupancy
2014-12-02 12:08:25 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-02-24 10:16:59 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
2014-12-02 12:08:25 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-02-24 10:16:59 +01:00
system.cpu.dcache.tags.tag_accesses 1236470793 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1236470793 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 147113779 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 147113779 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 128236098 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 128236098 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 377977 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 377977 # number of SoftPFReq hits
system.cpu.dcache.WriteLineReq_hits::cpu.data 323653 # number of WriteLineReq hits
system.cpu.dcache.WriteLineReq_hits::total 323653 # number of WriteLineReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3296961 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 3296961 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 3691090 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 3691090 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 275349877 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 275349877 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 275727854 # number of overall hits
system.cpu.dcache.overall_hits::total 275727854 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 9547222 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 9547222 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 11260039 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 11260039 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 1170114 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 1170114 # number of SoftPFReq misses
system.cpu.dcache.WriteLineReq_misses::cpu.data 1233803 # number of WriteLineReq misses
system.cpu.dcache.WriteLineReq_misses::total 1233803 # number of WriteLineReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 446138 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 446138 # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data 6 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 6 # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data 20807261 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 20807261 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 21977375 # number of overall misses
system.cpu.dcache.overall_misses::total 21977375 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 168019956500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 168019956500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 444932022751 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 444932022751 # number of WriteReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 52262346938 # number of WriteLineReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::total 52262346938 # number of WriteLineReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6889431000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 6889431000 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 285500 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 285500 # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 612951979251 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 612951979251 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 612951979251 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 612951979251 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 156661001 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 156661001 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 139496137 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 139496137 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 1548091 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 1548091 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::cpu.data 1557456 # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::total 1557456 # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3743099 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 3743099 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3691096 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 3691096 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 296157138 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 296157138 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 297705229 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 297705229 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060942 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.060942 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080719 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.080719 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.755843 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.755843 # miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.792191 # miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::total 0.792191 # miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119189 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119189 # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.070258 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.070258 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.073823 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.073823 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17598.832048 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 17598.832048 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39514.252371 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 39514.252371 # average WriteReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 42358.745228 # average WriteLineReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::total 42358.745228 # average WriteLineReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15442.376574 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15442.376574 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 47583.333333 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 47583.333333 # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 29458.561569 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 29458.561569 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 27890.136072 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 27890.136072 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 32144751 # number of cycles access was blocked
2014-12-02 12:08:25 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-02-24 10:16:59 +01:00
system.cpu.dcache.blocked::no_mshrs 1600072 # number of cycles access was blocked
2014-12-02 12:08:25 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
2016-02-24 10:16:59 +01:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.089565 # average number of cycles each access was blocked
2014-12-02 12:08:25 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
2016-02-24 10:16:59 +01:00
system.cpu.dcache.writebacks::writebacks 7504258 # number of writebacks
system.cpu.dcache.writebacks::total 7504258 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4442516 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 4442516 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9255736 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 9255736 # number of WriteReq MSHR hits
system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7058 # number of WriteLineReq MSHR hits
system.cpu.dcache.WriteLineReq_mshr_hits::total 7058 # number of WriteLineReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 218425 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 218425 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 13698252 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 13698252 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 13698252 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 13698252 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5104706 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 5104706 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2004303 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 2004303 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1163297 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 1163297 # number of SoftPFReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1226745 # number of WriteLineReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::total 1226745 # number of WriteLineReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 227713 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 227713 # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 6 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 6 # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 7109009 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 7109009 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 8272306 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 8272306 # number of overall MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total 33678 # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67374 # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total 67374 # number of overall MSHR uncacheable misses
2016-02-24 10:16:59 +01:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84710979000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 84710979000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77672671390 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 77672671390 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 23648689000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 23648689000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 50594844438 # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 50594844438 # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3209583500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3209583500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 279500 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 279500 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 162383650390 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 162383650390 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 186032339390 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 186032339390 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6191842000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6191842000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6228406964 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6228406964 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12420248964 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 12420248964 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032584 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032584 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014368 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014368 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.751440 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.751440 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787659 # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787659 # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060835 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060835 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024004 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.024004 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027787 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.027787 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16594.683220 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16594.683220 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38752.958704 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38752.958704 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 20329.020878 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 20329.020878 # average SoftPFReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 41243.163362 # average WriteLineReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 41243.163362 # average WriteLineReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14094.862832 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14094.862832 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 46583.333333 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 46583.333333 # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22841.953132 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22841.953132 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22488.570828 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22488.570828 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183854.207495 # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183854.207495 # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184841.137346 # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184841.137346 # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184347.804257 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184347.804257 # average overall mshr uncacheable latency
2014-12-02 12:08:25 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2016-02-24 10:16:59 +01:00
system.cpu.icache.tags.replacements 15019267 # number of replacements
system.cpu.icache.tags.tagsinuse 511.928693 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 340404778 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 15019779 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 22.663767 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 20448016500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 511.928693 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.999861 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.999861 # Average percentage of cache occupancy
2014-10-30 05:50:15 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-02-24 10:16:59 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id
2014-10-30 05:50:15 +01:00
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-02-24 10:16:59 +01:00
system.cpu.icache.tags.tag_accesses 371211305 # Number of tag accesses
system.cpu.icache.tags.data_accesses 371211305 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 340404778 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 340404778 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 340404778 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 340404778 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 340404778 # number of overall hits
system.cpu.icache.overall_hits::total 340404778 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 15786521 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 15786521 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 15786521 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 15786521 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 15786521 # number of overall misses
system.cpu.icache.overall_misses::total 15786521 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 213423777380 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 213423777380 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 213423777380 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 213423777380 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 213423777380 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 213423777380 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 356191299 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 356191299 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 356191299 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 356191299 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 356191299 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 356191299 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044320 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.044320 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.044320 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.044320 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.044320 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.044320 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13519.367401 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13519.367401 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13519.367401 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13519.367401 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13519.367401 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13519.367401 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 24648 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-02-24 10:16:59 +01:00
system.cpu.icache.blocked::no_mshrs 1434 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
2016-02-24 10:16:59 +01:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 17.188285 # average number of cycles each access was blocked
2014-10-30 05:50:15 +01:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
2016-02-24 10:16:59 +01:00
system.cpu.icache.writebacks::writebacks 15019267 # number of writebacks
system.cpu.icache.writebacks::total 15019267 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 766515 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 766515 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 766515 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 766515 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 766515 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 766515 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15020006 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 15020006 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 15020006 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 15020006 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 15020006 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 15020006 # number of overall MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21294 # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total 21294 # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21294 # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total 21294 # number of overall MSHR uncacheable misses
2016-02-24 10:16:59 +01:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 191135995392 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 191135995392 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 191135995392 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 191135995392 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 191135995392 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 191135995392 # number of overall MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 2684938000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 2684938000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 2684938000 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 2684938000 # number of overall MSHR uncacheable cycles
2016-02-24 10:16:59 +01:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.042168 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.042168 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.042168 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.042168 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.042168 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.042168 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12725.427366 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12725.427366 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12725.427366 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12725.427366 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12725.427366 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12725.427366 # average overall mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126088.945243 # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126088.945243 # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126088.945243 # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126088.945243 # average overall mshr uncacheable latency
2014-10-30 05:50:15 +01:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2016-02-24 10:16:59 +01:00
system.cpu.l2cache.tags.replacements 1144462 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65297.598211 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 46017703 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 1207114 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 38.122085 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 4511701500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 37171.608657 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 289.486238 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 449.841209 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 7858.021749 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 19528.640359 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.567194 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004417 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006864 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.119904 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.297983 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.996362 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023 277 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 62375 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 277 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 573 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2650 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5065 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54017 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004227 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951767 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 408203781 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 408203781 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 781080 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 297784 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1078864 # number of ReadReq hits
system.cpu.l2cache.WritebackDirty_hits::writebacks 7504258 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 7504258 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 15016613 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 15016613 # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 9434 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 9434 # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1568735 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1568735 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14937013 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 14937013 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6236325 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 6236325 # number of ReadSharedReq hits
system.cpu.l2cache.InvalidateReq_hits::cpu.data 728917 # number of InvalidateReq hits
system.cpu.l2cache.InvalidateReq_hits::total 728917 # number of InvalidateReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 781080 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 297784 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 14937013 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 7805060 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 23820937 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 781080 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 297784 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 14937013 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 7805060 # number of overall hits
system.cpu.l2cache.overall_hits::total 23820937 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3313 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3248 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 6561 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 34060 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 34060 # number of UpgradeReq misses
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
2016-02-24 10:16:59 +01:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 395411 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 395411 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 82785 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 82785 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 256057 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 256057 # number of ReadSharedReq misses
system.cpu.l2cache.InvalidateReq_misses::cpu.data 497828 # number of InvalidateReq misses
system.cpu.l2cache.InvalidateReq_misses::total 497828 # number of InvalidateReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 3313 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 3248 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 82785 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 651468 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 740814 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 3313 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 3248 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 82785 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 651468 # number of overall misses
system.cpu.l2cache.overall_misses::total 740814 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 456063500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 443832500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 899896000 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1363124000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 1363124000 # number of UpgradeReq miss cycles
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 160500 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 160500 # number of SCUpgradeReq miss cycles
2016-02-24 10:16:59 +01:00
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 55147182500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 55147182500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 11136291500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 11136291500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 35748767000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 35748767000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 13337500 # number of InvalidateReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::total 13337500 # number of InvalidateReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 456063500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 443832500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 11136291500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 90895949500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 102932137000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 456063500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 443832500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 11136291500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 90895949500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 102932137000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 784393 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 301032 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1085425 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::writebacks 7504258 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 7504258 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 15016613 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 15016613 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 43494 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 43494 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 6 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 6 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1964146 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1964146 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15019798 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 15019798 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6492382 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 6492382 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1226745 # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::total 1226745 # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 784393 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 301032 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 15019798 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 8456528 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 24561751 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 784393 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 301032 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 15019798 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 8456528 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 24561751 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.004224 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.010790 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.006045 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.783097 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.783097 # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.201314 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.201314 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005512 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005512 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.039440 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.039440 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.405812 # miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::total 0.405812 # miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.004224 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.010790 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005512 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.077037 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.030161 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.004224 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.010790 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005512 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.077037 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.030161 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 137658.768488 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 136647.937192 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 137158.360006 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 40021.256606 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 40021.256606 # average UpgradeReq miss latency
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 53500 # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 53500 # average SCUpgradeReq miss latency
2016-02-24 10:16:59 +01:00
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 139468.002913 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 139468.002913 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134520.643836 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134520.643836 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 139612.535490 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 139612.535490 # average ReadSharedReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 26.791382 # average InvalidateReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 26.791382 # average InvalidateReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137658.768488 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 136647.937192 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134520.643836 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 139524.810889 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 138944.643325 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137658.768488 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 136647.937192 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134520.643836 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 139524.810889 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 138944.643325 # average overall miss latency
2014-10-30 05:50:15 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
2016-02-24 10:16:59 +01:00
system.cpu.l2cache.writebacks::writebacks 960844 # number of writebacks
system.cpu.l2cache.writebacks::total 960844 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.dtb.walker 1 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.dtb.walker 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.dtb.walker 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 22 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 3312 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3248 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 6560 # number of ReadReq MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses
2016-02-24 10:16:59 +01:00
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 34060 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 34060 # number of UpgradeReq MSHR misses
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
2016-02-24 10:16:59 +01:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 395411 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 395411 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 82785 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 82785 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 256036 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 256036 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 497828 # number of InvalidateReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::total 497828 # number of InvalidateReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 3312 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3248 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 82785 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 651447 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 740792 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 3312 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3248 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 82785 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 651447 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 740792 # number of overall MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 21294 # number of ReadReq MSHR uncacheable
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 54972 # number of ReadReq MSHR uncacheable
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 21294 # number of overall MSHR uncacheable misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67374 # number of overall MSHR uncacheable misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 88668 # number of overall MSHR uncacheable misses
2016-02-24 10:16:59 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 422876510 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 411352500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 834229010 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2316435500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2316435500 # number of UpgradeReq MSHR miss cycles
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 209000 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 209000 # number of SCUpgradeReq MSHR miss cycles
2016-02-24 10:16:59 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 51192062926 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 51192062926 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10308356184 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10308356184 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 33185372324 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 33185372324 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 34796895500 # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 34796895500 # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 422876510 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 411352500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10308356184 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 84377435250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 95520020444 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 422876510 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 411352500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10308356184 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 84377435250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 95520020444 # number of overall MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 2418763000 # number of ReadReq MSHR uncacheable cycles
2016-02-24 10:16:59 +01:00
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5770678500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8189441500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5836379500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5836379500 # number of WriteReq MSHR uncacheable cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2418763000 # number of overall MSHR uncacheable cycles
2016-02-24 10:16:59 +01:00
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11607058000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 14025821000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004222 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.010790 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.006044 # mshr miss rate for ReadReq accesses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2016-02-24 10:16:59 +01:00
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.783097 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.783097 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.201314 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.201314 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005512 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005512 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.039436 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.039436 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.405812 # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.405812 # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004222 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.010790 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005512 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.077035 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.030160 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004222 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.010790 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005512 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.077035 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.030160 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127680.105676 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 126647.937192 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127169.056402 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68010.437463 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68010.437463 # average UpgradeReq mshr miss latency
2016-02-10 10:08:27 +01:00
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69666.666667 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69666.666667 # average SCUpgradeReq mshr miss latency
2016-02-24 10:16:59 +01:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129465.449687 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129465.449687 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124519.613263 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124519.613263 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 129612.133934 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 129612.133934 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69897.425416 # average InvalidateReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69897.425416 # average InvalidateReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127680.105676 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126647.937192 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124519.613263 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 129523.100498 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128943.104737 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127680.105676 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126647.937192 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124519.613263 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129523.100498 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128943.104737 # average overall mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.945243 # average ReadReq mshr uncacheable latency
2016-02-24 10:16:59 +01:00
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171348.610369 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148974.778069 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173206.893993 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173206.893993 # average WriteReq mshr uncacheable latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.945243 # average overall mshr uncacheable latency
2016-02-24 10:16:59 +01:00
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172278.000416 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158183.572427 # average overall mshr uncacheable latency
2014-10-30 05:50:15 +01:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2016-02-24 10:16:59 +01:00
system.cpu.toL2Bus.snoop_filter.tot_requests 50149666 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 25446406 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3588 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 2163 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2163 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-02-24 10:16:59 +01:00
system.cpu.toL2Bus.trans_dist::ReadReq 1624231 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 23137410 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution
2016-02-24 10:16:59 +01:00
system.cpu.toL2Bus.trans_dist::WritebackDirty 8571764 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 15019267 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 2370936 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 43497 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 6 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 43503 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1964146 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1964146 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 15020006 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 6501231 # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq 1333409 # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateResp 1226745 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45101659 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29271837 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 729068 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1925616 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 77028180 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1922840864 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1021731230 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2408256 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6275144 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 2953255494 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 1860303 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 27780180 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.025443 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.157467 # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-02-24 10:16:59 +01:00
system.cpu.toL2Bus.snoop_fanout::0 27073367 97.46% 97.46% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 706813 2.54% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
2016-02-24 10:16:59 +01:00
system.cpu.toL2Bus.snoop_fanout::total 27780180 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 48093772959 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.cpu.toL2Bus.snoopLayer0.occupancy 1496382 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.cpu.toL2Bus.respLayer0.occupancy 22560257433 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 13373462829 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.cpu.toL2Bus.respLayer2.occupancy 428394234 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.cpu.toL2Bus.respLayer3.occupancy 1141603196 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.iobus.trans_dist::ReadReq 40297 # Transaction distribution
system.iobus.trans_dist::ReadResp 40297 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
2016-02-24 10:16:59 +01:00
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230952 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 230952 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
2016-02-24 10:16:59 +01:00
system.iobus.pkt_count::total 353736 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
2016-02-24 10:16:59 +01:00
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334240 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7334240 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
2016-02-24 10:16:59 +01:00
system.iobus.pkt_size::total 7492160 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 41874500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer2.occupancy 342500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer23.occupancy 25162500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer24.occupancy 36499500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer25.occupancy 567349755 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2015-07-03 16:15:03 +02:00
system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.iobus.respLayer3.occupancy 147712000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-07-03 16:15:03 +02:00
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.iocache.tags.replacements 115457 # number of replacements
system.iocache.tags.tagsinuse 10.423127 # Cycle average of tags in use
2014-10-30 05:50:15 +01:00
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
2016-02-24 10:16:59 +01:00
system.iocache.tags.sampled_refs 115473 # Sample count of references to valid blocks.
2014-10-30 05:50:15 +01:00
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
2016-02-24 10:16:59 +01:00
system.iocache.tags.warmup_cycle 13098803375000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 3.544202 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 6.878925 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.221513 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.429933 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.651445 # Average percentage of cache occupancy
2014-10-30 05:50:15 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2016-02-24 10:16:59 +01:00
system.iocache.tags.tag_accesses 1039641 # Number of tag accesses
system.iocache.tags.data_accesses 1039641 # Number of data accesses
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
2016-02-24 10:16:59 +01:00
system.iocache.ReadReq_misses::realview.ide 8812 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8849 # number of ReadReq misses
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
2014-10-30 05:50:15 +01:00
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
2016-02-24 10:16:59 +01:00
system.iocache.demand_misses::realview.ide 8812 # number of demand (read+write) misses
system.iocache.demand_misses::total 8852 # number of demand (read+write) misses
2014-10-30 05:50:15 +01:00
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
2016-02-24 10:16:59 +01:00
system.iocache.overall_misses::realview.ide 8812 # number of overall misses
system.iocache.overall_misses::total 8852 # number of overall misses
2016-02-10 10:08:27 +01:00
system.iocache.ReadReq_miss_latency::realview.ethernet 5069500 # number of ReadReq miss cycles
2016-02-24 10:16:59 +01:00
system.iocache.ReadReq_miss_latency::realview.ide 1683110232 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 1688179732 # number of ReadReq miss cycles
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles
2016-02-24 10:16:59 +01:00
system.iocache.WriteLineReq_miss_latency::realview.ide 13415109023 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 13415109023 # number of WriteLineReq miss cycles
2016-02-10 10:08:27 +01:00
system.iocache.demand_miss_latency::realview.ethernet 5420500 # number of demand (read+write) miss cycles
2016-02-24 10:16:59 +01:00
system.iocache.demand_miss_latency::realview.ide 1683110232 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 1688530732 # number of demand (read+write) miss cycles
2016-02-10 10:08:27 +01:00
system.iocache.overall_miss_latency::realview.ethernet 5420500 # number of overall miss cycles
2016-02-24 10:16:59 +01:00
system.iocache.overall_miss_latency::realview.ide 1683110232 # number of overall miss cycles
system.iocache.overall_miss_latency::total 1688530732 # number of overall miss cycles
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
2016-02-24 10:16:59 +01:00
system.iocache.ReadReq_accesses::realview.ide 8812 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8849 # number of ReadReq accesses(hits+misses)
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
2014-10-30 05:50:15 +01:00
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
2016-02-24 10:16:59 +01:00
system.iocache.demand_accesses::realview.ide 8812 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 8852 # number of demand (read+write) accesses
2014-10-30 05:50:15 +01:00
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
2016-02-24 10:16:59 +01:00
system.iocache.overall_accesses::realview.ide 8812 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 8852 # number of overall (read+write) accesses
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2014-10-30 05:50:15 +01:00
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2016-02-10 10:08:27 +01:00
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137013.513514 # average ReadReq miss latency
2016-02-24 10:16:59 +01:00
system.iocache.ReadReq_avg_miss_latency::realview.ide 191002.068997 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 190776.328625 # average ReadReq miss latency
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency
2016-02-24 10:16:59 +01:00
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125769.791335 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 125769.791335 # average WriteLineReq miss latency
2016-02-10 10:08:27 +01:00
system.iocache.demand_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency
2016-02-24 10:16:59 +01:00
system.iocache.demand_avg_miss_latency::realview.ide 191002.068997 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 190751.325350 # average overall miss latency
2016-02-10 10:08:27 +01:00
system.iocache.overall_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency
2016-02-24 10:16:59 +01:00
system.iocache.overall_avg_miss_latency::realview.ide 191002.068997 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 190751.325350 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 34444 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-02-24 10:16:59 +01:00
system.iocache.blocked::no_mshrs 3506 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2016-02-24 10:16:59 +01:00
system.iocache.avg_blocked_cycles::no_mshrs 9.824301 # average number of cycles each access was blocked
2014-10-30 05:50:15 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
2014-10-30 05:50:15 +01:00
system.iocache.cache_copies 0 # number of cache copies performed
2015-03-02 11:04:20 +01:00
system.iocache.writebacks::writebacks 106630 # number of writebacks
system.iocache.writebacks::total 106630 # number of writebacks
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
2016-02-24 10:16:59 +01:00
system.iocache.ReadReq_mshr_misses::realview.ide 8812 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 8849 # number of ReadReq MSHR misses
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
2016-02-24 10:16:59 +01:00
system.iocache.demand_mshr_misses::realview.ide 8812 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 8852 # number of demand (read+write) MSHR misses
2014-10-30 05:50:15 +01:00
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
2016-02-24 10:16:59 +01:00
system.iocache.overall_mshr_misses::realview.ide 8812 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 8852 # number of overall MSHR misses
2016-02-10 10:08:27 +01:00
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219500 # number of ReadReq MSHR miss cycles
2016-02-24 10:16:59 +01:00
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1242510232 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 1245729732 # number of ReadReq MSHR miss cycles
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles
2016-02-24 10:16:59 +01:00
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8076836456 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 8076836456 # number of WriteLineReq MSHR miss cycles
2016-02-10 10:08:27 +01:00
system.iocache.demand_mshr_miss_latency::realview.ethernet 3420500 # number of demand (read+write) MSHR miss cycles
2016-02-24 10:16:59 +01:00
system.iocache.demand_mshr_miss_latency::realview.ide 1242510232 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 1245930732 # number of demand (read+write) MSHR miss cycles
2016-02-10 10:08:27 +01:00
system.iocache.overall_mshr_miss_latency::realview.ethernet 3420500 # number of overall MSHR miss cycles
2016-02-24 10:16:59 +01:00
system.iocache.overall_mshr_miss_latency::realview.ide 1242510232 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 1245930732 # number of overall MSHR miss cycles
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2016-02-10 10:08:27 +01:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87013.513514 # average ReadReq mshr miss latency
2016-02-24 10:16:59 +01:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141002.068997 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 140776.328625 # average ReadReq mshr miss latency
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
2016-02-24 10:16:59 +01:00
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75722.234831 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75722.234831 # average WriteLineReq mshr miss latency
2016-02-10 10:08:27 +01:00
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency
2016-02-24 10:16:59 +01:00
system.iocache.demand_avg_mshr_miss_latency::realview.ide 141002.068997 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 140751.325350 # average overall mshr miss latency
2016-02-10 10:08:27 +01:00
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency
2016-02-24 10:16:59 +01:00
system.iocache.overall_avg_mshr_miss_latency::realview.ide 141002.068997 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 140751.325350 # average overall mshr miss latency
2014-10-30 05:50:15 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-06 09:26:50 +01:00
system.membus.trans_dist::ReadReq 54972 # Transaction distribution
2016-02-24 10:16:59 +01:00
system.membus.trans_dist::ReadResp 409202 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::WriteReq 33696 # Transaction distribution
system.membus.trans_dist::WriteResp 33696 # Transaction distribution
2016-02-24 10:16:59 +01:00
system.membus.trans_dist::WritebackDirty 1067474 # Transaction distribution
system.membus.trans_dist::CleanEvict 191385 # Transaction distribution
system.membus.trans_dist::UpgradeReq 34855 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
2016-02-10 10:08:27 +01:00
system.membus.trans_dist::UpgradeResp 8 # Transaction distribution
2016-02-24 10:16:59 +01:00
system.membus.trans_dist::ReadExReq 394790 # Transaction distribution
system.membus.trans_dist::ReadExResp 394790 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 354230 # Transaction distribution
system.membus.trans_dist::InvalidateReq 604321 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes)
2016-02-24 10:16:59 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3203313 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3332933 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237959 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 237959 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 3570892 # Packet count per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 420 # Cumulative packet size per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes)
2016-02-24 10:16:59 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 109183820 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 109353790 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7271424 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7271424 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 116625214 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 2530 # Total snoops (count)
system.membus.snoop_fanout::samples 2735759 # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2016-02-24 10:16:59 +01:00
system.membus.snoop_fanout::1 2735759 100.00% 100.00% # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2016-02-24 10:16:59 +01:00
system.membus.snoop_fanout::total 2735759 # Request fanout histogram
system.membus.reqLayer0.occupancy 103971500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.membus.reqLayer1.occupancy 32000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.membus.reqLayer2.occupancy 5468000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.membus.reqLayer5.occupancy 7155774176 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.membus.respLayer2.occupancy 4068025704 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.membus.respLayer3.occupancy 44802062 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-12-04 01:19:05 +01:00
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
2014-12-02 12:08:25 +01:00
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
2015-09-25 13:27:03 +02:00
system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
2014-12-02 12:08:25 +01:00
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
2015-09-25 13:27:03 +02:00
system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
2014-12-02 12:08:25 +01:00
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
2015-12-04 01:19:05 +01:00
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
2014-10-30 05:50:15 +01:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
2016-02-24 10:16:59 +01:00
system.cpu.kern.inst.quiesce 16114 # number of quiesce instructions executed
2014-10-30 05:50:15 +01:00
---------- End Simulation Statistics ----------
