gem5/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  1.647873                       # Number of seconds simulated
sim_ticks                                1647872849000                       # Number of ticks simulated
final_tick                               1647872849000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 379189                       # Simulator instruction rate (inst/s)
host_op_rate                                   701163                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              755680972                       # Simulator tick rate (ticks/s)
host_mem_usage                                 300836                       # Number of bytes of host memory used
host_seconds                                  2180.65                       # Real time elapsed on the host
sim_insts                                   826877110                       # Number of instructions simulated
sim_ops                                    1528988702                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            120704                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          24272448                       # Number of bytes read from this memory
system.physmem.bytes_read::total             24393152                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       120704                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          120704                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     18706304                       # Number of bytes written to this memory
system.physmem.bytes_written::total          18706304                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               1886                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             379257                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                381143                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          292286                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               292286                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst                73248                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             14729564                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                14802812                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst           73248                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total              73248                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          11351788                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               11351788                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          11351788                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst               73248                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            14729564                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               26154600                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls                  551                       # Number of system calls
system.cpu.numCycles                       3295745698                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   826877110                       # Number of instructions committed
system.cpu.committedOps                    1528988702                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses            1528317562                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
system.cpu.num_func_calls                           0                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts     92658795                       # number of instructions that are conditional controls
system.cpu.num_int_insts                   1528317562                       # number of integer instructions
system.cpu.num_fp_insts                             0                       # number of float instructions
system.cpu.num_int_register_reads          3855106260                       # number of times the integer registers were read
system.cpu.num_int_register_writes         1614040854                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
system.cpu.num_mem_refs                     533262343                       # number of memory refs
system.cpu.num_load_insts                   384102157                       # Number of load instructions
system.cpu.num_store_insts                  149160186                       # Number of store instructions
system.cpu.num_idle_cycles                          0                       # Number of idle cycles
system.cpu.num_busy_cycles                 3295745698                       # Number of busy cycles
system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
system.cpu.idle_fraction                            0                       # Percentage of idle cycles
system.cpu.icache.replacements                   1253                       # number of replacements
system.cpu.icache.tagsinuse                881.356491                       # Cycle average of tags in use
system.cpu.icache.total_refs               1068344252                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                   2814                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs               379653.252310                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     881.356491                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.430350                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.430350                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst   1068344252                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total      1068344252                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst    1068344252                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total       1068344252                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst   1068344252                       # number of overall hits
system.cpu.icache.overall_hits::total      1068344252                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst         2814                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total          2814                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst         2814                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total           2814                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst         2814                       # number of overall misses
system.cpu.icache.overall_misses::total          2814                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    115806000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    115806000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    115806000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    115806000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    115806000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    115806000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst   1068347066                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total   1068347066                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst   1068347066                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total   1068347066                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst   1068347066                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total   1068347066                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000003                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000003                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000003                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000003                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000003                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000003                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41153.518124                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 41153.518124                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 41153.518124                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 41153.518124                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 41153.518124                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 41153.518124                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst         2814                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total         2814                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst         2814                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total         2814                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst         2814                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total         2814                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    110178000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    110178000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    110178000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    110178000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    110178000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    110178000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000003                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000003                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000003                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39153.518124                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39153.518124                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39153.518124                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 39153.518124                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39153.518124                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 39153.518124                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                348459                       # number of replacements
system.cpu.l2cache.tagsinuse             29286.402664                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 3655011                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                380814                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  9.597890                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle          755936431000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 21041.299337                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst    139.758519                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data   8105.344807                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.642129                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.004265                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.247355                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.893750                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst          928                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1554848                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1555776                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      2323523                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      2323523                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       584353                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       584353                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst          928                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      2139201                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2140129                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst          928                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      2139201                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2140129                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         1886                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       172566                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       174452                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       206691                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       206691                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         1886                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       379257                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        381143                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         1886                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       379257                       # number of overall misses
system.cpu.l2cache.overall_misses::total       381143                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     98084000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   8973561000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   9071645000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10747939500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  10747939500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     98084000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  19721500500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  19819584500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     98084000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  19721500500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  19819584500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst         2814                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1727414                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1730228                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      2323523                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      2323523                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       791044                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       791044                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst         2814                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      2518458                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2521272                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst         2814                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      2518458                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2521272                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.670220                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.099898                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.100826                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.261289                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.261289                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.670220                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.150591                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.151171                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.670220                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.150591                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.151171                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52006.362672                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.747540                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.808245                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.036286                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.036286                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52006.362672                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.359914                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000.389618                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52006.362672                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.359914                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000.389618                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       292286                       # number of writebacks
system.cpu.l2cache.writebacks::total           292286                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1886                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       172566                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       174452                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206691                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       206691                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         1886                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       379257                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       381143                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         1886                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       379257                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       381143                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     75452000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   6902758000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   6978210000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8267645000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8267645000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     75452000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  15170403000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  15245855000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     75452000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  15170403000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  15245855000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.670220                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.099898                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.100826                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.261289                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.261289                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.670220                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.150591                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.151171                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.670220                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.150591                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.151171                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40006.362672                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.683796                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.745191                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.024191                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.024191                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40006.362672                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.324318                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.354198                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40006.362672                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.324318                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.354198                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                2514362                       # number of replacements
system.cpu.dcache.tagsinuse               4086.415783                       # Cycle average of tags in use
system.cpu.dcache.total_refs                530743930                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                2518458                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                 210.741624                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle             8211724000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    4086.415783                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.997660                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.997660                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data    382374772                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       382374772                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    148369158                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      148369158                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data     530743930                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        530743930                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    530743930                       # number of overall hits
system.cpu.dcache.overall_hits::total       530743930                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1727414                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1727414                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       791044                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       791044                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      2518458                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2518458                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2518458                       # number of overall misses
system.cpu.dcache.overall_misses::total       2518458                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  29704283000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  29704283000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  18964601500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  18964601500                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  48668884500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  48668884500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  48668884500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  48668884500                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    384102186                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    384102186                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    149160202                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    149160202                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    533262388                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    533262388                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    533262388                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    533262388                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004497                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.004497                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.005303                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.005303                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.004723                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.004723                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.004723                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.004723                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17195.810037                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 17195.810037                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23974.142399                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 23974.142399                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19324.874387                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 19324.874387                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 19324.874387                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 19324.874387                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      2323523                       # number of writebacks
system.cpu.dcache.writebacks::total           2323523                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1727414                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1727414                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       791044                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       791044                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      2518458                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      2518458                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      2518458                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      2518458                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  26249455000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  26249455000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  17382513500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  17382513500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  43631968500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  43631968500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  43631968500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  43631968500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.004497                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.004497                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005303                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005303                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.004723                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.004723                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.004723                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.004723                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15195.810037                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15195.810037                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21974.142399                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21974.142399                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17324.874387                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 17324.874387                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17324.874387                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17324.874387                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------