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gem5/tests/quick/50.memtest/ref/alpha/linux/memtest/simout

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Add short memtest run to quick regressions. Caveats: - Even though memtest is ISA-independent, it will only run for the Alpha builds, since there's no way to specify ISA-independent reference files and I didn't want to commit 3 copies since I'm not sure we want to run it for all the different ISAs anyway. - Reference outputs were generated on my laptop, so performance numbers will be low compared to zizzer. --HG-- extra : convert_revision : 210fe4abecc19fbab0b15402c6cb4863650bab66
2007-02-07 06:16:33 +01:00
M5 Simulator System
Bus: Update the stats for the recent bus fix. --HG-- extra : convert_revision : dc29f7b5e6fa30a50305193cb0e5aed942f7e407
2008-02-26 08:20:40 +01:00
Copyright (c) 2001-2008
Add short memtest run to quick regressions. Caveats: - Even though memtest is ISA-independent, it will only run for the Alpha builds, since there's no way to specify ISA-independent reference files and I didn't want to commit 3 copies since I'm not sure we want to run it for all the different ISAs anyway. - Reference outputs were generated on my laptop, so performance numbers will be low compared to zizzer. --HG-- extra : convert_revision : 210fe4abecc19fbab0b15402c6cb4863650bab66
2007-02-07 06:16:33 +01:00
The Regents of The University of Michigan
All Rights Reserved
stats: update stats for previous cset Coherence protocol change basically got rid of UpgradeReqs in L2 caches, other minor related cache stat changes.
2010-09-22 08:07:35 +02:00
M5 compiled Sep 20 2010 15:04:49
M5 revision 0c4a7d867247 7686 default qtip print-identical tip
M5 started Sep 20 2010 15:50:04
M5 executing on phenom
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest
Update refs for new CPU frequency changes. tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini: tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out: tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt: tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr: tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout: tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini: tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out: tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt: tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr: tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout: tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini: tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out: tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt: tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr: tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout: tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini: tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out: tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt: tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr: tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout: tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini: tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out: tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt: tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr: tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout: tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini: tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out: tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt: tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt: tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout: tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini: tests/quick/50.memtest/ref/alpha/linux/memtest/config.out: tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt: tests/quick/50.memtest/ref/alpha/linux/memtest/stdout: Update refs --HG-- extra : convert_revision : 8d9deb2b907843064b40e46207d9c9361941f022
2007-04-22 20:50:37 +02:00
Global frequency set at 1000000000000 ticks per second
Reference updates. Since split cache is gone, a lot of config.ini changes, and minor changes to stats that are likely due to the decoupling of insertions/evictions in the cache.
2008-11-06 17:11:42 +01:00
info: Entering event queue @ 0. Starting simulation...
stats: update stats for previous cset Coherence protocol change basically got rid of UpgradeReqs in L2 caches, other minor related cache stat changes.
2010-09-22 08:07:35 +02:00
Exiting @ tick 263488655 because maximum number of loads reached
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