13a15c55a4
Coherence protocol change basically got rid of UpgradeReqs in L2 caches, other minor related cache stat changes.
15 lines
616 B
Text
Executable file
15 lines
616 B
Text
Executable file
M5 Simulator System
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Copyright (c) 2001-2008
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The Regents of The University of Michigan
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All Rights Reserved
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M5 compiled Sep 20 2010 15:04:49
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M5 revision 0c4a7d867247 7686 default qtip print-identical tip
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M5 started Sep 20 2010 15:50:04
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M5 executing on phenom
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command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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Exiting @ tick 263488655 because maximum number of loads reached
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