2012-02-13 19:30:30 +01:00
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---------- Begin Simulation Statistics ----------
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2012-07-27 22:08:05 +02:00
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sim_seconds 0.912097 # Number of seconds simulated
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sim_ticks 912096763500 # Number of ticks simulated
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final_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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2012-02-13 19:30:30 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2012-10-25 19:14:42 +02:00
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host_inst_rate 1752000 # Simulator instruction rate (inst/s)
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host_op_rate 2255696 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 25930494646 # Simulator tick rate (ticks/s)
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host_mem_usage 382232 # Number of bytes of host memory used
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host_seconds 35.17 # Real time elapsed on the host
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2012-07-27 22:08:05 +02:00
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sim_insts 61625970 # Number of instructions simulated
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sim_ops 79343340 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 502180 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 6234996 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 214556 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 3364528 # Number of bytes read from this memory
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system.physmem.bytes_read::total 49638308 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 502180 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 214556 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 716736 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 4195776 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory
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system.physmem.bytes_written::total 7222864 # Number of bytes written to this memory
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system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.inst 14065 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 97494 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 3434 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 52597 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 5082797 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 65559 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 822331 # Number of write requests responded to by this memory
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system.physmem.bw_read::realview.clcd 43111215 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.dtb.walker 70 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.itb.walker 211 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.inst 550578 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 6835893 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.dtb.walker 211 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 235234 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 3688784 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 54422195 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 550578 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 235234 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 785811 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 4600144 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.data 18638 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1.data 3300185 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 7918967 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 4600144 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.clcd 43111215 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.dtb.walker 70 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 211 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 550578 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 6854532 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.dtb.walker 211 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 235234 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 6988969 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 62341162 # Total bandwidth to/from this memory (bytes/s)
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2012-10-25 19:14:42 +02:00
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system.physmem.readReqs 0 # Total number of read requests seen
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system.physmem.writeReqs 0 # Total number of write requests seen
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system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 0 # Total number of bytes read from memory
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system.physmem.bytesWritten 0 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 0 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 0 # Categorize read packet sizes
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system.physmem.readPktSize::7 0 # Categorize read packet sizes
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system.physmem.readPktSize::8 0 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # categorize write packet sizes
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system.physmem.writePktSize::1 0 # categorize write packet sizes
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system.physmem.writePktSize::2 0 # categorize write packet sizes
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system.physmem.writePktSize::3 0 # categorize write packet sizes
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system.physmem.writePktSize::4 0 # categorize write packet sizes
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system.physmem.writePktSize::5 0 # categorize write packet sizes
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system.physmem.writePktSize::6 0 # categorize write packet sizes
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system.physmem.writePktSize::7 0 # categorize write packet sizes
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system.physmem.writePktSize::8 0 # categorize write packet sizes
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system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
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system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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|
|
system.physmem.totQLat 0 # Total cycles spent in queuing delays
|
|
|
|
|
system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
|
|
|
|
|
system.physmem.totBusLat 0 # Total cycles spent in databus access
|
|
|
|
|
system.physmem.totBankLat 0 # Total cycles spent in bank access
|
|
|
|
|
system.physmem.avgQLat nan # Average queueing delay per request
|
|
|
|
|
system.physmem.avgBankLat nan # Average bank access latency per request
|
|
|
|
|
system.physmem.avgBusLat nan # Average bus latency per request
|
|
|
|
|
system.physmem.avgMemAccLat nan # Average memory access latency
|
|
|
|
|
system.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s
|
|
|
|
|
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
|
|
|
|
system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
|
|
|
|
|
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
|
|
|
|
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
|
|
|
|
|
system.physmem.busUtil 0.00 # Data bus utilization in percentage
|
|
|
|
|
system.physmem.avgRdQLen 0.00 # Average read queue length over time
|
|
|
|
|
system.physmem.avgWrQLen 0.00 # Average write queue length over time
|
|
|
|
|
system.physmem.readRowHits 0 # Number of row buffer hits during reads
|
|
|
|
|
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
|
|
|
|
system.physmem.readRowHitRate nan # Row buffer hit rate for reads
|
|
|
|
|
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
|
|
|
|
system.physmem.avgGap nan # Average gap between requests
|
2012-06-05 07:23:16 +02:00
|
|
|
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
|
|
|
|
|
system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
|
|
|
|
|
system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
|
|
|
|
|
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
|
|
|
|
|
system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
|
|
|
|
|
system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
|
|
|
|
|
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
|
|
|
|
|
system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
|
|
|
|
|
system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
|
|
|
|
|
system.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s)
|
|
|
|
|
system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s)
|
|
|
|
|
system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s)
|
2012-07-27 22:08:05 +02:00
|
|
|
system.l2c.replacements 70662 # number of replacements
|
|
|
|
|
system.l2c.tagsinuse 51560.217790 # Cycle average of tags in use
|
|
|
|
|
system.l2c.total_refs 1623342 # Total number of references to valid blocks.
|
|
|
|
|
system.l2c.sampled_refs 135814 # Sample count of references to valid blocks.
|
|
|
|
|
system.l2c.avg_refs 11.952685 # Average number of references to valid blocks.
|
2012-02-13 19:30:30 +01:00
|
|
|
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2012-07-27 22:08:05 +02:00
|
|
|
system.l2c.occ_blocks::writebacks 39276.104351 # Average occupied blocks per requestor
|
2012-06-29 17:19:03 +02:00
|
|
|
system.l2c.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor
|
2012-07-27 22:08:05 +02:00
|
|
|
system.l2c.occ_blocks::cpu0.itb.walker 0.001108 # Average occupied blocks per requestor
|
|
|
|
|
system.l2c.occ_blocks::cpu0.inst 4360.752038 # Average occupied blocks per requestor
|
|
|
|
|
system.l2c.occ_blocks::cpu0.data 2483.307369 # Average occupied blocks per requestor
|
|
|
|
|
system.l2c.occ_blocks::cpu1.dtb.walker 2.678940 # Average occupied blocks per requestor
|
|
|
|
|
system.l2c.occ_blocks::cpu1.inst 2126.451282 # Average occupied blocks per requestor
|
|
|
|
|
system.l2c.occ_blocks::cpu1.data 3310.922653 # Average occupied blocks per requestor
|
|
|
|
|
system.l2c.occ_percent::writebacks 0.599306 # Average percentage of cache occupancy
|
2012-06-29 17:19:03 +02:00
|
|
|
system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
|
2012-07-27 22:08:05 +02:00
|
|
|
system.l2c.occ_percent::cpu0.inst 0.066540 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_percent::cpu0.data 0.037892 # Average percentage of cache occupancy
|
2012-06-29 17:19:03 +02:00
|
|
|
system.l2c.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy
|
2012-07-27 22:08:05 +02:00
|
|
|
system.l2c.occ_percent::cpu1.inst 0.032447 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_percent::cpu1.data 0.050521 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_percent::total 0.786746 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.ReadReq_hits::cpu0.dtb.walker 3874 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::cpu0.itb.walker 1919 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::cpu0.inst 421038 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::cpu0.data 175188 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::cpu1.dtb.walker 5331 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::cpu1.itb.walker 1734 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::cpu1.inst 430511 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::cpu1.data 169511 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::total 1209106 # number of ReadReq hits
|
|
|
|
|
system.l2c.Writeback_hits::writebacks 567807 # number of Writeback hits
|
|
|
|
|
system.l2c.Writeback_hits::total 567807 # number of Writeback hits
|
|
|
|
|
system.l2c.UpgradeReq_hits::cpu0.data 611 # number of UpgradeReq hits
|
|
|
|
|
system.l2c.UpgradeReq_hits::cpu1.data 663 # number of UpgradeReq hits
|
|
|
|
|
system.l2c.UpgradeReq_hits::total 1274 # number of UpgradeReq hits
|
|
|
|
|
system.l2c.SCUpgradeReq_hits::cpu0.data 137 # number of SCUpgradeReq hits
|
|
|
|
|
system.l2c.SCUpgradeReq_hits::cpu1.data 31 # number of SCUpgradeReq hits
|
|
|
|
|
system.l2c.SCUpgradeReq_hits::total 168 # number of SCUpgradeReq hits
|
|
|
|
|
system.l2c.ReadExReq_hits::cpu0.data 58151 # number of ReadExReq hits
|
|
|
|
|
system.l2c.ReadExReq_hits::cpu1.data 50212 # number of ReadExReq hits
|
|
|
|
|
system.l2c.ReadExReq_hits::total 108363 # number of ReadExReq hits
|
|
|
|
|
system.l2c.demand_hits::cpu0.dtb.walker 3874 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::cpu0.itb.walker 1919 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::cpu0.inst 421038 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::cpu0.data 233339 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::cpu1.dtb.walker 5331 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::cpu1.itb.walker 1734 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::cpu1.inst 430511 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::cpu1.data 219723 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::total 1317469 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.overall_hits::cpu0.dtb.walker 3874 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::cpu0.itb.walker 1919 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::cpu0.inst 421038 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::cpu0.data 233339 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::cpu1.dtb.walker 5331 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::cpu1.itb.walker 1734 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::cpu1.inst 430511 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::cpu1.data 219723 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::total 1317469 # number of overall hits
|
2012-06-29 17:19:03 +02:00
|
|
|
system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses
|
2012-07-27 22:08:05 +02:00
|
|
|
system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::cpu0.inst 7432 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::cpu0.data 6392 # number of ReadReq misses
|
2012-06-29 17:19:03 +02:00
|
|
|
system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses
|
2012-07-27 22:08:05 +02:00
|
|
|
system.l2c.ReadReq_misses::cpu1.inst 3347 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::cpu1.data 5276 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::total 22454 # number of ReadReq misses
|
|
|
|
|
system.l2c.UpgradeReq_misses::cpu0.data 4932 # number of UpgradeReq misses
|
|
|
|
|
system.l2c.UpgradeReq_misses::cpu1.data 4304 # number of UpgradeReq misses
|
|
|
|
|
system.l2c.UpgradeReq_misses::total 9236 # number of UpgradeReq misses
|
|
|
|
|
system.l2c.SCUpgradeReq_misses::cpu0.data 741 # number of SCUpgradeReq misses
|
|
|
|
|
system.l2c.SCUpgradeReq_misses::cpu1.data 490 # number of SCUpgradeReq misses
|
|
|
|
|
system.l2c.SCUpgradeReq_misses::total 1231 # number of SCUpgradeReq misses
|
|
|
|
|
system.l2c.ReadExReq_misses::cpu0.data 92461 # number of ReadExReq misses
|
|
|
|
|
system.l2c.ReadExReq_misses::cpu1.data 48372 # number of ReadExReq misses
|
|
|
|
|
system.l2c.ReadExReq_misses::total 140833 # number of ReadExReq misses
|
2012-06-29 17:19:03 +02:00
|
|
|
system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses
|
2012-07-27 22:08:05 +02:00
|
|
|
system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses
|
|
|
|
|
system.l2c.demand_misses::cpu0.inst 7432 # number of demand (read+write) misses
|
|
|
|
|
system.l2c.demand_misses::cpu0.data 98853 # number of demand (read+write) misses
|
2012-06-29 17:19:03 +02:00
|
|
|
system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses
|
2012-07-27 22:08:05 +02:00
|
|
|
system.l2c.demand_misses::cpu1.inst 3347 # number of demand (read+write) misses
|
|
|
|
|
system.l2c.demand_misses::cpu1.data 53648 # number of demand (read+write) misses
|
|
|
|
|
system.l2c.demand_misses::total 163287 # number of demand (read+write) misses
|
2012-06-29 17:19:03 +02:00
|
|
|
system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses
|
2012-07-27 22:08:05 +02:00
|
|
|
system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses
|
|
|
|
|
system.l2c.overall_misses::cpu0.inst 7432 # number of overall misses
|
|
|
|
|
system.l2c.overall_misses::cpu0.data 98853 # number of overall misses
|
2012-06-29 17:19:03 +02:00
|
|
|
system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses
|
2012-07-27 22:08:05 +02:00
|
|
|
system.l2c.overall_misses::cpu1.inst 3347 # number of overall misses
|
|
|
|
|
system.l2c.overall_misses::cpu1.data 53648 # number of overall misses
|
|
|
|
|
system.l2c.overall_misses::total 163287 # number of overall misses
|
|
|
|
|
system.l2c.ReadReq_accesses::cpu0.dtb.walker 3875 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::cpu0.itb.walker 1922 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::cpu0.inst 428470 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::cpu0.data 181580 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::cpu1.dtb.walker 5334 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::cpu1.itb.walker 1734 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::cpu1.inst 433858 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::cpu1.data 174787 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::total 1231560 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.Writeback_accesses::writebacks 567807 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.l2c.Writeback_accesses::total 567807 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 5543 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 4967 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.UpgradeReq_accesses::total 10510 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.SCUpgradeReq_accesses::cpu0.data 878 # number of SCUpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.SCUpgradeReq_accesses::cpu1.data 521 # number of SCUpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.SCUpgradeReq_accesses::total 1399 # number of SCUpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadExReq_accesses::cpu0.data 150612 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadExReq_accesses::cpu1.data 98584 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadExReq_accesses::total 249196 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.l2c.demand_accesses::cpu0.dtb.walker 3875 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::cpu0.itb.walker 1922 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::cpu0.inst 428470 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::cpu0.data 332192 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::cpu1.dtb.walker 5334 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::cpu1.itb.walker 1734 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::cpu1.inst 433858 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::cpu1.data 273371 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::total 1480756 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::cpu0.dtb.walker 3875 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::cpu0.itb.walker 1922 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::cpu0.inst 428470 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::cpu0.data 332192 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::cpu1.dtb.walker 5334 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::cpu1.itb.walker 1734 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::cpu1.inst 433858 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::cpu1.data 273371 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::total 1480756 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001561 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::cpu0.inst 0.017345 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::cpu0.data 0.035202 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::cpu1.inst 0.007715 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::cpu1.data 0.030185 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::total 0.018232 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.889771 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.866519 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_miss_rate::total 0.878782 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.843964 # miss rate for SCUpgradeReq accesses
|
|
|
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.940499 # miss rate for SCUpgradeReq accesses
|
|
|
|
|
system.l2c.SCUpgradeReq_miss_rate::total 0.879914 # miss rate for SCUpgradeReq accesses
|
|
|
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 0.613902 # miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 0.490668 # miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_miss_rate::total 0.565150 # miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::cpu0.itb.walker 0.001561 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.017345 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::cpu0.data 0.297578 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.007715 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::cpu1.data 0.196246 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::total 0.110273 # miss rate for demand accesses
|
|
|
|
|
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::cpu0.itb.walker 0.001561 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.017345 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::cpu0.data 0.297578 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.007715 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::cpu1.data 0.196246 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::total 0.110273 # miss rate for overall accesses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2012-02-13 19:30:30 +01:00
|
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
2012-07-27 22:08:05 +02:00
|
|
|
system.l2c.writebacks::writebacks 65559 # number of writebacks
|
|
|
|
|
system.l2c.writebacks::total 65559 # number of writebacks
|
2012-02-13 19:30:30 +01:00
|
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
|
|
|
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
|
|
|
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
|
|
|
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
|
|
|
|
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
|
|
|
|
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
|
|
|
|
system.cpu0.dtb.inst_hits 0 # ITB inst hits
|
|
|
|
|
system.cpu0.dtb.inst_misses 0 # ITB inst misses
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu0.dtb.read_hits 7975768 # DTB read hits
|
|
|
|
|
system.cpu0.dtb.read_misses 3611 # DTB read misses
|
|
|
|
|
system.cpu0.dtb.write_hits 5966574 # DTB write hits
|
|
|
|
|
system.cpu0.dtb.write_misses 672 # DTB write misses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu0.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu0.dtb.prefetch_faults 135 # Number of TLB faults due to prefetch
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu0.dtb.read_accesses 7979379 # DTB read accesses
|
|
|
|
|
system.cpu0.dtb.write_accesses 5967246 # DTB write accesses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu0.dtb.hits 13942342 # DTB hits
|
|
|
|
|
system.cpu0.dtb.misses 4283 # DTB misses
|
|
|
|
|
system.cpu0.dtb.accesses 13946625 # DTB accesses
|
|
|
|
|
system.cpu0.itb.inst_hits 30238804 # ITB inst hits
|
|
|
|
|
system.cpu0.itb.inst_misses 2175 # ITB inst misses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu0.itb.flush_entries 1499 # Number of entries that have been flushed from TLB
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
|
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu0.itb.inst_accesses 30240979 # ITB inst accesses
|
|
|
|
|
system.cpu0.itb.hits 30238804 # DTB hits
|
|
|
|
|
system.cpu0.itb.misses 2175 # DTB misses
|
|
|
|
|
system.cpu0.itb.accesses 30240979 # DTB accesses
|
|
|
|
|
system.cpu0.numCycles 1823633059 # number of cpu cycles simulated
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu0.committedInsts 29750005 # Number of instructions committed
|
|
|
|
|
system.cpu0.committedOps 39129633 # Number of ops (including micro ops) committed
|
|
|
|
|
system.cpu0.num_int_alu_accesses 34471201 # Number of integer alu accesses
|
|
|
|
|
system.cpu0.num_fp_alu_accesses 5449 # Number of float alu accesses
|
|
|
|
|
system.cpu0.num_func_calls 1241903 # number of times a function call or return occured
|
2012-09-25 18:49:41 +02:00
|
|
|
system.cpu0.num_conditional_control_insts 4044057 # number of instructions that are conditional controls
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu0.num_int_insts 34471201 # number of integer instructions
|
|
|
|
|
system.cpu0.num_fp_insts 5449 # number of float instructions
|
|
|
|
|
system.cpu0.num_int_register_reads 175121947 # number of times the integer registers were read
|
|
|
|
|
system.cpu0.num_int_register_writes 36551788 # number of times the integer registers were written
|
|
|
|
|
system.cpu0.num_fp_register_reads 4535 # number of times the floating registers were read
|
|
|
|
|
system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written
|
|
|
|
|
system.cpu0.num_mem_refs 14626951 # number of memory refs
|
|
|
|
|
system.cpu0.num_load_insts 8357226 # Number of load instructions
|
|
|
|
|
system.cpu0.num_store_insts 6269725 # Number of store instructions
|
|
|
|
|
system.cpu0.num_idle_cycles 1783968822.941743 # Number of idle cycles
|
|
|
|
|
system.cpu0.num_busy_cycles 39664236.058257 # Number of busy cycles
|
|
|
|
|
system.cpu0.not_idle_fraction 0.021750 # Percentage of non-idle cycles
|
|
|
|
|
system.cpu0.idle_fraction 0.978250 # Percentage of idle cycles
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu0.kern.inst.quiesce 49966 # number of quiesce instructions executed
|
|
|
|
|
system.cpu0.icache.replacements 428547 # number of replacements
|
|
|
|
|
system.cpu0.icache.tagsinuse 511.020000 # Cycle average of tags in use
|
|
|
|
|
system.cpu0.icache.total_refs 29811115 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu0.icache.sampled_refs 429059 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu0.icache.avg_refs 69.480223 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu0.icache.warmup_cycle 64537139000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu0.icache.occ_blocks::cpu0.inst 511.020000 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu0.icache.occ_percent::cpu0.inst 0.998086 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu0.icache.occ_percent::total 0.998086 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 29811115 # number of ReadReq hits
|
|
|
|
|
system.cpu0.icache.ReadReq_hits::total 29811115 # number of ReadReq hits
|
|
|
|
|
system.cpu0.icache.demand_hits::cpu0.inst 29811115 # number of demand (read+write) hits
|
|
|
|
|
system.cpu0.icache.demand_hits::total 29811115 # number of demand (read+write) hits
|
|
|
|
|
system.cpu0.icache.overall_hits::cpu0.inst 29811115 # number of overall hits
|
|
|
|
|
system.cpu0.icache.overall_hits::total 29811115 # number of overall hits
|
|
|
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 429059 # number of ReadReq misses
|
|
|
|
|
system.cpu0.icache.ReadReq_misses::total 429059 # number of ReadReq misses
|
|
|
|
|
system.cpu0.icache.demand_misses::cpu0.inst 429059 # number of demand (read+write) misses
|
|
|
|
|
system.cpu0.icache.demand_misses::total 429059 # number of demand (read+write) misses
|
|
|
|
|
system.cpu0.icache.overall_misses::cpu0.inst 429059 # number of overall misses
|
|
|
|
|
system.cpu0.icache.overall_misses::total 429059 # number of overall misses
|
|
|
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 30240174 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.icache.ReadReq_accesses::total 30240174 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 30240174 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu0.icache.demand_accesses::total 30240174 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 30240174 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu0.icache.overall_accesses::total 30240174 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014188 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.014188 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014188 # miss rate for demand accesses
|
|
|
|
|
system.cpu0.icache.demand_miss_rate::total 0.014188 # miss rate for demand accesses
|
|
|
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014188 # miss rate for overall accesses
|
|
|
|
|
system.cpu0.icache.overall_miss_rate::total 0.014188 # miss rate for overall accesses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu0.dcache.replacements 323609 # number of replacements
|
|
|
|
|
system.cpu0.dcache.tagsinuse 494.763091 # Cycle average of tags in use
|
|
|
|
|
system.cpu0.dcache.total_refs 12467604 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu0.dcache.sampled_refs 323981 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu0.dcache.avg_refs 38.482516 # Average number of references to valid blocks.
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu0.dcache.warmup_cycle 22115000 # Cycle when the warmup percentage was hit.
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu0.dcache.occ_blocks::cpu0.data 494.763091 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu0.dcache.occ_percent::cpu0.data 0.966334 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu0.dcache.occ_percent::total 0.966334 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 6512305 # number of ReadReq hits
|
|
|
|
|
system.cpu0.dcache.ReadReq_hits::total 6512305 # number of ReadReq hits
|
|
|
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 5630881 # number of WriteReq hits
|
|
|
|
|
system.cpu0.dcache.WriteReq_hits::total 5630881 # number of WriteReq hits
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 151619 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 151619 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 153180 # number of StoreCondReq hits
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_hits::total 153180 # number of StoreCondReq hits
|
|
|
|
|
system.cpu0.dcache.demand_hits::cpu0.data 12143186 # number of demand (read+write) hits
|
|
|
|
|
system.cpu0.dcache.demand_hits::total 12143186 # number of demand (read+write) hits
|
|
|
|
|
system.cpu0.dcache.overall_hits::cpu0.data 12143186 # number of overall hits
|
|
|
|
|
system.cpu0.dcache.overall_hits::total 12143186 # number of overall hits
|
|
|
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 197167 # number of ReadReq misses
|
|
|
|
|
system.cpu0.dcache.ReadReq_misses::total 197167 # number of ReadReq misses
|
|
|
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 167342 # number of WriteReq misses
|
|
|
|
|
system.cpu0.dcache.WriteReq_misses::total 167342 # number of WriteReq misses
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9062 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 9062 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7469 # number of StoreCondReq misses
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_misses::total 7469 # number of StoreCondReq misses
|
|
|
|
|
system.cpu0.dcache.demand_misses::cpu0.data 364509 # number of demand (read+write) misses
|
|
|
|
|
system.cpu0.dcache.demand_misses::total 364509 # number of demand (read+write) misses
|
|
|
|
|
system.cpu0.dcache.overall_misses::cpu0.data 364509 # number of overall misses
|
|
|
|
|
system.cpu0.dcache.overall_misses::total 364509 # number of overall misses
|
|
|
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 6709472 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.dcache.ReadReq_accesses::total 6709472 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5798223 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.dcache.WriteReq_accesses::total 5798223 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 160681 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 160681 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160649 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 160649 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 12507695 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu0.dcache.demand_accesses::total 12507695 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 12507695 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu0.dcache.overall_accesses::total 12507695 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029386 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.029386 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.028861 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.028861 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056397 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056397 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.046493 # miss rate for StoreCondReq accesses
|
|
|
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.046493 # miss rate for StoreCondReq accesses
|
|
|
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029143 # miss rate for demand accesses
|
|
|
|
|
system.cpu0.dcache.demand_miss_rate::total 0.029143 # miss rate for demand accesses
|
|
|
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029143 # miss rate for overall accesses
|
|
|
|
|
system.cpu0.dcache.overall_miss_rate::total 0.029143 # miss rate for overall accesses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu0.dcache.writebacks::writebacks 300958 # number of writebacks
|
|
|
|
|
system.cpu0.dcache.writebacks::total 300958 # number of writebacks
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
|
|
|
|
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu1.dtb.read_hits 7364781 # DTB read hits
|
|
|
|
|
system.cpu1.dtb.read_misses 3705 # DTB read misses
|
|
|
|
|
system.cpu1.dtb.write_hits 5489656 # DTB write hits
|
|
|
|
|
system.cpu1.dtb.write_misses 1595 # DTB write misses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu1.dtb.flush_entries 1788 # Number of entries that have been flushed from TLB
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu1.dtb.prefetch_faults 145 # Number of TLB faults due to prefetch
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu1.dtb.read_accesses 7368486 # DTB read accesses
|
|
|
|
|
system.cpu1.dtb.write_accesses 5491251 # DTB write accesses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu1.dtb.hits 12854437 # DTB hits
|
|
|
|
|
system.cpu1.dtb.misses 5300 # DTB misses
|
|
|
|
|
system.cpu1.dtb.accesses 12859737 # DTB accesses
|
|
|
|
|
system.cpu1.itb.inst_hits 32412306 # ITB inst hits
|
|
|
|
|
system.cpu1.itb.inst_misses 2200 # ITB inst misses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu1.itb.flush_entries 1327 # Number of entries that have been flushed from TLB
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
|
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu1.itb.inst_accesses 32414506 # ITB inst accesses
|
|
|
|
|
system.cpu1.itb.hits 32412306 # DTB hits
|
|
|
|
|
system.cpu1.itb.misses 2200 # DTB misses
|
|
|
|
|
system.cpu1.itb.accesses 32414506 # DTB accesses
|
|
|
|
|
system.cpu1.numCycles 1824154149 # number of cpu cycles simulated
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu1.committedInsts 31875965 # Number of instructions committed
|
|
|
|
|
system.cpu1.committedOps 40213707 # Number of ops (including micro ops) committed
|
|
|
|
|
system.cpu1.num_int_alu_accesses 35797832 # Number of integer alu accesses
|
|
|
|
|
system.cpu1.num_fp_alu_accesses 4436 # Number of float alu accesses
|
|
|
|
|
system.cpu1.num_func_calls 955227 # number of times a function call or return occured
|
2012-09-25 18:49:41 +02:00
|
|
|
system.cpu1.num_conditional_control_insts 4048022 # number of instructions that are conditional controls
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu1.num_int_insts 35797832 # number of integer instructions
|
|
|
|
|
system.cpu1.num_fp_insts 4436 # number of float instructions
|
|
|
|
|
system.cpu1.num_int_register_reads 181634271 # number of times the integer registers were read
|
|
|
|
|
system.cpu1.num_int_register_writes 39007898 # number of times the integer registers were written
|
|
|
|
|
system.cpu1.num_fp_register_reads 3022 # number of times the floating registers were read
|
|
|
|
|
system.cpu1.num_fp_register_writes 1416 # number of times the floating registers were written
|
|
|
|
|
system.cpu1.num_mem_refs 13370713 # number of memory refs
|
|
|
|
|
system.cpu1.num_load_insts 7642673 # Number of load instructions
|
|
|
|
|
system.cpu1.num_store_insts 5728040 # Number of store instructions
|
|
|
|
|
system.cpu1.num_idle_cycles 1783362859.317266 # Number of idle cycles
|
|
|
|
|
system.cpu1.num_busy_cycles 40791289.682734 # Number of busy cycles
|
|
|
|
|
system.cpu1.not_idle_fraction 0.022362 # Percentage of non-idle cycles
|
|
|
|
|
system.cpu1.idle_fraction 0.977638 # Percentage of idle cycles
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu1.kern.inst.quiesce 40379 # number of quiesce instructions executed
|
|
|
|
|
system.cpu1.icache.replacements 433942 # number of replacements
|
|
|
|
|
system.cpu1.icache.tagsinuse 475.447912 # Cycle average of tags in use
|
|
|
|
|
system.cpu1.icache.total_refs 31979125 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu1.icache.sampled_refs 434454 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu1.icache.avg_refs 73.607620 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu1.icache.warmup_cycle 69967763000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu1.icache.occ_blocks::cpu1.inst 475.447912 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu1.icache.occ_percent::cpu1.inst 0.928609 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu1.icache.occ_percent::total 0.928609 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 31979125 # number of ReadReq hits
|
|
|
|
|
system.cpu1.icache.ReadReq_hits::total 31979125 # number of ReadReq hits
|
|
|
|
|
system.cpu1.icache.demand_hits::cpu1.inst 31979125 # number of demand (read+write) hits
|
|
|
|
|
system.cpu1.icache.demand_hits::total 31979125 # number of demand (read+write) hits
|
|
|
|
|
system.cpu1.icache.overall_hits::cpu1.inst 31979125 # number of overall hits
|
|
|
|
|
system.cpu1.icache.overall_hits::total 31979125 # number of overall hits
|
|
|
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 434454 # number of ReadReq misses
|
|
|
|
|
system.cpu1.icache.ReadReq_misses::total 434454 # number of ReadReq misses
|
|
|
|
|
system.cpu1.icache.demand_misses::cpu1.inst 434454 # number of demand (read+write) misses
|
|
|
|
|
system.cpu1.icache.demand_misses::total 434454 # number of demand (read+write) misses
|
|
|
|
|
system.cpu1.icache.overall_misses::cpu1.inst 434454 # number of overall misses
|
|
|
|
|
system.cpu1.icache.overall_misses::total 434454 # number of overall misses
|
|
|
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 32413579 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.icache.ReadReq_accesses::total 32413579 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 32413579 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu1.icache.demand_accesses::total 32413579 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 32413579 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu1.icache.overall_accesses::total 32413579 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013403 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.013403 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013403 # miss rate for demand accesses
|
|
|
|
|
system.cpu1.icache.demand_miss_rate::total 0.013403 # miss rate for demand accesses
|
|
|
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013403 # miss rate for overall accesses
|
|
|
|
|
system.cpu1.icache.overall_miss_rate::total 0.013403 # miss rate for overall accesses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu1.dcache.replacements 294289 # number of replacements
|
|
|
|
|
system.cpu1.dcache.tagsinuse 447.573682 # Cycle average of tags in use
|
|
|
|
|
system.cpu1.dcache.total_refs 11707745 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu1.dcache.sampled_refs 294801 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu1.dcache.avg_refs 39.714061 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu1.dcache.warmup_cycle 67293493000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu1.dcache.occ_blocks::cpu1.data 447.573682 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu1.dcache.occ_percent::cpu1.data 0.874167 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu1.dcache.occ_percent::total 0.874167 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 7002209 # number of ReadReq hits
|
|
|
|
|
system.cpu1.dcache.ReadReq_hits::total 7002209 # number of ReadReq hits
|
|
|
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 4520313 # number of WriteReq hits
|
|
|
|
|
system.cpu1.dcache.WriteReq_hits::total 4520313 # number of WriteReq hits
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 77954 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_hits::total 77954 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79030 # number of StoreCondReq hits
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_hits::total 79030 # number of StoreCondReq hits
|
|
|
|
|
system.cpu1.dcache.demand_hits::cpu1.data 11522522 # number of demand (read+write) hits
|
|
|
|
|
system.cpu1.dcache.demand_hits::total 11522522 # number of demand (read+write) hits
|
|
|
|
|
system.cpu1.dcache.overall_hits::cpu1.data 11522522 # number of overall hits
|
|
|
|
|
system.cpu1.dcache.overall_hits::total 11522522 # number of overall hits
|
|
|
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 198275 # number of ReadReq misses
|
|
|
|
|
system.cpu1.dcache.ReadReq_misses::total 198275 # number of ReadReq misses
|
|
|
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 125920 # number of WriteReq misses
|
|
|
|
|
system.cpu1.dcache.WriteReq_misses::total 125920 # number of WriteReq misses
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11251 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_misses::total 11251 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10139 # number of StoreCondReq misses
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_misses::total 10139 # number of StoreCondReq misses
|
|
|
|
|
system.cpu1.dcache.demand_misses::cpu1.data 324195 # number of demand (read+write) misses
|
|
|
|
|
system.cpu1.dcache.demand_misses::total 324195 # number of demand (read+write) misses
|
|
|
|
|
system.cpu1.dcache.overall_misses::cpu1.data 324195 # number of overall misses
|
|
|
|
|
system.cpu1.dcache.overall_misses::total 324195 # number of overall misses
|
|
|
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 7200484 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.ReadReq_accesses::total 7200484 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 4646233 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.WriteReq_accesses::total 4646233 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 89205 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_accesses::total 89205 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 89169 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_accesses::total 89169 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 11846717 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu1.dcache.demand_accesses::total 11846717 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 11846717 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu1.dcache.overall_accesses::total 11846717 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027536 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.027536 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027102 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.027102 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.126125 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.126125 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113705 # miss rate for StoreCondReq accesses
|
|
|
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113705 # miss rate for StoreCondReq accesses
|
|
|
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027366 # miss rate for demand accesses
|
|
|
|
|
system.cpu1.dcache.demand_miss_rate::total 0.027366 # miss rate for demand accesses
|
|
|
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027366 # miss rate for overall accesses
|
|
|
|
|
system.cpu1.dcache.overall_miss_rate::total 0.027366 # miss rate for overall accesses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
2012-07-27 22:08:05 +02:00
|
|
|
system.cpu1.dcache.writebacks::writebacks 266849 # number of writebacks
|
|
|
|
|
system.cpu1.dcache.writebacks::total 266849 # number of writebacks
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.iocache.replacements 0 # number of replacements
|
|
|
|
|
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
|
|
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
|
|
|
|
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
2012-05-09 20:52:14 +02:00
|
|
|
system.iocache.avg_refs nan # Average number of references to valid blocks.
|
2012-02-13 19:30:30 +01:00
|
|
|
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2012-02-13 19:30:30 +01:00
|
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
