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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt

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arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
---------- Begin Simulation Statistics ----------
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
sim_seconds 51.329008 # Number of seconds simulated
sim_ticks 51329007806000 # Number of ticks simulated
final_tick 51329007806000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
host_inst_rate 122530 # Simulator instruction rate (inst/s)
host_op_rate 143983 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 7088851393 # Simulator tick rate (ticks/s)
host_mem_usage 738964 # Number of bytes of host memory used
host_seconds 7240.81 # Real time elapsed on the host
sim_insts 887219290 # Number of instructions simulated
sim_ops 1042552088 # Number of ops (including micro ops) simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.physmem.bytes_read::cpu0.dtb.walker 156608 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 147648 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 4011328 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 41948256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 137216 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 124672 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 3256192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 42225192 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 430144 # Number of bytes read from this memory
system.physmem.bytes_read::total 92437256 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 4011328 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 3256192 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 7267520 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 78326464 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 4 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 20576 # Number of bytes written to this memory
system.physmem.bytes_written::total 78347044 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 2447 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2307 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 62677 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 655450 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 2144 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 1948 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 50878 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 659773 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6721 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1444345 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1223851 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 1 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 2572 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1226424 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 3051 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 2877 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 78149 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 817243 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 2673 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 2429 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 63438 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 822638 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 8380 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1800878 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 78149 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 63438 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 141587 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1525969 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 0 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 401 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1526370 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1525969 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 3051 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 2877 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 78149 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 817243 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 2673 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 2429 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 63438 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 823039 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 8380 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3327247 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1444345 # Number of read requests accepted
system.physmem.writeReqs 1226424 # Number of write requests accepted
system.physmem.readBursts 1444345 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1226424 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 92386688 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 51392 # Total number of bytes read from write queue
system.physmem.bytesWritten 78346944 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 92437256 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 78347044 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 803 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 143260 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 87933 # Per bank write bursts
system.physmem.perBankRdBursts::1 93643 # Per bank write bursts
system.physmem.perBankRdBursts::2 85045 # Per bank write bursts
system.physmem.perBankRdBursts::3 85481 # Per bank write bursts
system.physmem.perBankRdBursts::4 86547 # Per bank write bursts
system.physmem.perBankRdBursts::5 98902 # Per bank write bursts
system.physmem.perBankRdBursts::6 89510 # Per bank write bursts
system.physmem.perBankRdBursts::7 89009 # Per bank write bursts
system.physmem.perBankRdBursts::8 83048 # Per bank write bursts
system.physmem.perBankRdBursts::9 114994 # Per bank write bursts
system.physmem.perBankRdBursts::10 94557 # Per bank write bursts
system.physmem.perBankRdBursts::11 91990 # Per bank write bursts
system.physmem.perBankRdBursts::12 84421 # Per bank write bursts
system.physmem.perBankRdBursts::13 88294 # Per bank write bursts
system.physmem.perBankRdBursts::14 83729 # Per bank write bursts
system.physmem.perBankRdBursts::15 86439 # Per bank write bursts
system.physmem.perBankWrBursts::0 75039 # Per bank write bursts
system.physmem.perBankWrBursts::1 78494 # Per bank write bursts
system.physmem.perBankWrBursts::2 73313 # Per bank write bursts
system.physmem.perBankWrBursts::3 75746 # Per bank write bursts
system.physmem.perBankWrBursts::4 74304 # Per bank write bursts
system.physmem.perBankWrBursts::5 82444 # Per bank write bursts
system.physmem.perBankWrBursts::6 75935 # Per bank write bursts
system.physmem.perBankWrBursts::7 77729 # Per bank write bursts
system.physmem.perBankWrBursts::8 72743 # Per bank write bursts
system.physmem.perBankWrBursts::9 81620 # Per bank write bursts
system.physmem.perBankWrBursts::10 78637 # Per bank write bursts
system.physmem.perBankWrBursts::11 78702 # Per bank write bursts
system.physmem.perBankWrBursts::12 73730 # Per bank write bursts
system.physmem.perBankWrBursts::13 77135 # Per bank write bursts
system.physmem.perBankWrBursts::14 73140 # Per bank write bursts
system.physmem.perBankWrBursts::15 75460 # Per bank write bursts
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.physmem.numWrRetry 20 # Number of times write queue was full causing retry
system.physmem.totGap 51329006651000 # Total gap between requests
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 13 # Read request sizes (log2)
system.physmem.readPktSize::4 2 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.physmem.readPktSize::6 1444330 # Read request sizes (log2)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 1 # Write request sizes (log2)
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.physmem.writePktSize::6 1223851 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 664689 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 399415 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 215277 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 158221 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 875 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 607 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 566 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1187 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 757 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 399 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 382 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 201 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 189 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 139 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 139 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 121 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 110 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 108 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 88 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 64 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.physmem.wrQLenPdf::0 798 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 783 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 771 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 756 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 756 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 752 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 751 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 746 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 748 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 752 # What write queue length does an incoming req see
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.physmem.wrQLenPdf::10 746 # What write queue length does an incoming req see
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.physmem.wrQLenPdf::11 745 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 741 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 744 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 745 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 13504 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 15490 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 29705 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 43548 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 61632 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 73660 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 75063 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 75253 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 78109 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 77353 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 77886 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 84511 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 79729 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 90742 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 98017 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 76207 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 79989 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 72267 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 1721 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 1117 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 705 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 530 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 627 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 516 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 467 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 405 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 362 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 385 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 288 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 298 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 261 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 222 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 275 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 237 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 306 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 223 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 177 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 177 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 183 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 141 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 109 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 88 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 54 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 62 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 62 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 41 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 50 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 563229 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 303.133596 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 174.783036 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 331.925309 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 224869 39.92% 39.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 128828 22.87% 62.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 55416 9.84% 72.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 26482 4.70% 77.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 23365 4.15% 81.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 12858 2.28% 83.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 13591 2.41% 86.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 8972 1.59% 87.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 68848 12.22% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 563229 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 70176 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 20.570010 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 230.699325 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 70171 99.99% 99.99% # Reads before turning the bus around for writes
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.rdPerTurnAround::2048-4095 2 0.00% 100.00% # Reads before turning the bus around for writes
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.physmem.rdPerTurnAround::4096-6143 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-8191 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::59392-61439 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 70176 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 70176 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 17.444297 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.915567 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 6.713323 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3 50 0.07% 0.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7 20 0.03% 0.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11 12 0.02% 0.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15 57 0.08% 0.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 66189 94.32% 94.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 1492 2.13% 96.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 215 0.31% 96.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 476 0.68% 97.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 85 0.12% 97.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 378 0.54% 98.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 194 0.28% 98.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 38 0.05% 98.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 68 0.10% 98.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 132 0.19% 98.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 29 0.04% 98.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 30 0.04% 98.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 483 0.69% 99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 27 0.04% 99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 29 0.04% 99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 113 0.16% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 6 0.01% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 2 0.00% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 3 0.00% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 5 0.01% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 2 0.00% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 2 0.00% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 1 0.00% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119 3 0.00% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 3 0.00% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 20 0.03% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 2 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 3 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 3 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167 2 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 70176 # Writes before turning the bus around for reads
system.physmem.totQLat 41972985964 # Total ticks spent queuing
system.physmem.totMemAccLat 69039398464 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 7217710000 # Total ticks spent in databus transfers
system.physmem.avgQLat 29076.39 # Average queueing delay per DRAM burst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.physmem.avgMemAccLat 47826.39 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.80 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.53 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.80 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.53 # Average system write bandwidth in MiByte/s
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.physmem.avgRdQLen 1.20 # Average read queue length when enqueuing
system.physmem.avgWrQLen 9.49 # Average write queue length when enqueuing
system.physmem.readRowHits 1185538 # Number of row buffer hits during reads
system.physmem.writeRowHits 918946 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.13 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 75.07 # Row buffer hit rate for writes
system.physmem.avgGap 19218811.75 # Average gap between requests
system.physmem.pageHitRate 78.89 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 2148975360 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 1172556000 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 5585346000 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 3972265920 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3352561271280 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1240688413800 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 29709081656250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 34315210484610 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.534456 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 49423456234980 # Time in different power states
system.physmem_0.memoryStateTime::REF 1713988120000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.physmem_0.memoryStateTime::ACT 191563442520 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.physmem_1.actEnergy 2109035880 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 1150763625 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 5674281600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 3960362160 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3352561271280 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 1239780982635 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 29709877648500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 34315114345680 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.532583 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 49424762025236 # Time in different power states
system.physmem_1.memoryStateTime::REF 1713988120000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.physmem_1.memoryStateTime::ACT 190257652264 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.realview.nvmem.bytes_read::cpu0.inst 1088 # Number of bytes read from this memory
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.realview.nvmem.bytes_read::cpu1.inst 1024 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 2148 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 1088 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 1024 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 2112 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 17 # Number of read requests responded to by this memory
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 38 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 21 # Total read bandwidth from this memory (bytes/s)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.realview.nvmem.bw_read::cpu1.inst 20 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 42 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 21 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 20 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 41 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 21 # Total bandwidth to/from this memory (bytes/s)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.realview.nvmem.bw_total::cpu1.inst 20 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 42 # Total bandwidth to/from this memory (bytes/s)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.branchPred.lookups 131402033 # Number of BP lookups
system.cpu0.branchPred.condPredicted 89056413 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 5742935 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 89027832 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 64073858 # Number of BTB hits
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.branchPred.BTBHitPct 71.970592 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 17186238 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 188408 # Number of incorrect RAS predictions.
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.dtb.walker.walks 880195 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 880195 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 16466 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 89406 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore 539518 # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples 340677 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean 2766.077546 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 16593.074042 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-65535 337825 99.16% 99.16% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-131071 1415 0.42% 99.58% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::131072-196607 964 0.28% 99.86% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::196608-262143 183 0.05% 99.91% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::262144-327679 175 0.05% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::327680-393215 39 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::393216-458751 38 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::458752-524287 35 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 340677 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples 406676 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 23311.011714 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 18634.861317 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 20757.119040 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535 397195 97.67% 97.67% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071 6941 1.71% 99.38% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1728 0.42% 99.80% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143 125 0.03% 99.83% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679 435 0.11% 99.94% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215 140 0.03% 99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751 69 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287 34 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823 8 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total 406676 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 373167653756 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 0.157772 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev 0.693071 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-3 372147551256 99.73% 99.73% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-7 557799500 0.15% 99.88% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-11 204631000 0.05% 99.93% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-15 121085000 0.03% 99.96% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-19 47750000 0.01% 99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::20-23 25413500 0.01% 99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::24-27 26015000 0.01% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::28-31 31058000 0.01% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::32-35 5928000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::36-39 324500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::40-43 31000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::44-47 25000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::48-51 28000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::52-55 7000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::56-59 7000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 373167653756 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 89406 84.45% 84.45% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M 16466 15.55% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 105872 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 880195 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 880195 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 105872 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 105872 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 986067 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.dtb.read_hits 104380254 # DTB read hits
system.cpu0.dtb.read_misses 607183 # DTB read misses
system.cpu0.dtb.write_hits 80883417 # DTB write hits
system.cpu0.dtb.write_misses 273012 # DTB write misses
system.cpu0.dtb.flush_tlb 1104 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.dtb.flush_tlb_mva_asid 21323 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 546 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 55971 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 172 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 8743 # Number of TLB faults due to prefetch
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.dtb.perms_faults 56844 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 104987437 # DTB read accesses
system.cpu0.dtb.write_accesses 81156429 # DTB write accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.dtb.hits 185263671 # DTB hits
system.cpu0.dtb.misses 880195 # DTB misses
system.cpu0.dtb.accesses 186143866 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.itb.walker.walks 105005 # Table walker walks requested
system.cpu0.itb.walker.walksLong 105005 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2 3046 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3 71369 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore 14507 # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples 90498 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean 1949.556896 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev 12931.664385 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-32767 89434 98.82% 98.82% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-65535 551 0.61% 99.43% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-98303 86 0.10% 99.53% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::98304-131071 107 0.12% 99.65% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::131072-163839 211 0.23% 99.88% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::163840-196607 47 0.05% 99.93% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::196608-229375 19 0.02% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::229376-262143 12 0.01% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::262144-294911 14 0.02% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::294912-327679 3 0.00% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::327680-360447 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::360448-393215 5 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 90498 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 88922 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 29750.028115 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 24620.054553 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 24536.459942 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535 86625 97.42% 97.42% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071 636 0.72% 98.13% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607 1404 1.58% 99.71% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143 86 0.10% 99.81% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679 126 0.14% 99.95% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215 27 0.03% 99.98% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751 13 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total 88922 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 300108383224 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean 1.830431 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 -249135515800 -83.02% -83.02% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1 549170051524 182.99% 99.98% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2 65847000 0.02% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3 6561000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4 1119000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::5 120500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::6 200000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 300108383224 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 71369 95.91% 95.91% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M 3046 4.09% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 74415 # Table walker page sizes translated
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 105005 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 105005 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 74415 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 74415 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 179420 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 94426208 # ITB inst hits
system.cpu0.itb.inst_misses 105005 # ITB inst misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.itb.flush_tlb 1104 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.itb.flush_tlb_mva_asid 21323 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 546 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 41718 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.itb.perms_faults 203794 # Number of TLB faults due to permissions restrictions
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.itb.inst_accesses 94531213 # ITB inst accesses
system.cpu0.itb.hits 94426208 # DTB hits
system.cpu0.itb.misses 105005 # DTB misses
system.cpu0.itb.accesses 94531213 # DTB accesses
system.cpu0.numCycles 693924076 # number of cpu cycles simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.fetch.icacheStallCycles 245365223 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 583481750 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 131402033 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 81260096 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 404572474 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 13127390 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 2693259 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles 25075 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles 5895 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles 5426941 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 179188 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 4152 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 94205115 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 3543246 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 41874 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 664835628 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 1.027383 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 2.280090 # Number of instructions fetched each cycle (Total)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.fetch.rateDist::0 520667894 78.32% 78.32% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 18098994 2.72% 81.04% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 18311074 2.75% 83.79% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 13311384 2.00% 85.79% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 28016067 4.21% 90.01% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5 9084552 1.37% 91.37% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 9729872 1.46% 92.84% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 8406845 1.26% 94.10% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 39208946 5.90% 100.00% # Number of instructions fetched each cycle (Total)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.fetch.rateDist::total 664835628 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.189361 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.840844 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 199358459 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 341820249 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 105168047 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 13323606 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 5162847 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 19689498 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 1420951 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 636719093 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 4377127 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 5162847 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 206863652 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 31387432 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 259611771 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 110843507 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 50963626 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 621821272 # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents 119952 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 2228381 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents 1945503 # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents 31637065 # Number of times rename has blocked due to SQ full
system.cpu0.rename.FullRegisterEvents 3952 # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands 595122984 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 956623907 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 735190096 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 738559 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 501301772 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 93821212 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 14866038 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 12879620 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 74385297 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 100195270 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 85014336 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 13702275 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 14674859 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 590272104 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 14944858 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 591104249 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 830680 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 78609056 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 50293897 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 361003 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 664835628 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.889098 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.627888 # Number of insts issued each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.iq.issued_per_cycle::0 433426304 65.19% 65.19% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 96952426 14.58% 79.78% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 43294447 6.51% 86.29% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 30849550 4.64% 90.93% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 22862967 3.44% 94.37% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 15973478 2.40% 96.77% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 10856280 1.63% 98.40% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 6404067 0.96% 99.37% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 4216109 0.63% 100.00% # Number of insts issued each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.iq.issued_per_cycle::total 664835628 # Number of insts issued each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.iq.fu_full::IntAlu 3013815 25.84% 25.84% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 22977 0.20% 26.04% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 2673 0.02% 26.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 26.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 26.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 26.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 26.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 26.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 26.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 26.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 26.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 26.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 26.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 26.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 26.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 26.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 26.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 26.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 26.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 26.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 26.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 26.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 26.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 26.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 26.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 2 0.00% 26.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 26.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 26.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 4796217 41.12% 67.19% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 3826853 32.81% 100.00% # attempts to use FU when none available
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.iq.FU_type_0::No_OpClass 58 0.00% 0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 401137490 67.86% 67.86% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 1467252 0.25% 68.11% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 65623 0.01% 68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 154 0.00% 68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 9 0.00% 68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 57449 0.01% 68.13% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.13% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.13% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.13% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 106450027 18.01% 86.14% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 81926148 13.86% 100.00% # Type of FU issued
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.iq.FU_type_0::total 591104249 # Type of FU issued
system.cpu0.iq.rate 0.851828 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 11662537 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.019730 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 1858540164 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 684045272 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 569697611 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 997179 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 495349 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 443319 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 602234444 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 532284 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 4680430 # Number of loads that had data forwarded from stores
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.iew.lsq.thread0.squashedLoads 15887962 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 20586 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 725982 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 8698150 # Number of stores squashed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.iew.lsq.thread0.rescheduledLoads 3921331 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 7846897 # Number of times an access to memory failed due to the cache being blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.iew.iewSquashCycles 5162847 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 16668961 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 12768791 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 605350499 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 1734594 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 100195270 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 85014336 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 12589274 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 229167 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 12454098 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 725982 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 2593635 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 2277415 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 4871050 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 584543415 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 104370380 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 5693430 # Number of squashed instructions skipped in execute
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.iew.exec_swp 0 # number of swp insts executed
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.iew.exec_nop 133537 # number of nop insts executed
system.cpu0.iew.exec_refs 185253232 # number of memory reference insts executed
system.cpu0.iew.exec_branches 108623271 # Number of branches executed
system.cpu0.iew.exec_stores 80882852 # Number of stores executed
system.cpu0.iew.exec_rate 0.842374 # Inst execution rate
system.cpu0.iew.wb_sent 571363680 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 570140930 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 281574536 # num instructions producing a value
system.cpu0.iew.wb_consumers 488934383 # num instructions consuming a value
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.iew.wb_rate 0.821619 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.575894 # average fanout of values written-back
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.commit.commitSquashedInsts 78652927 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 14583855 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 4341813 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 651404193 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.808420 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.807572 # Number of insts commited each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.commit.committed_per_cycle::0 458550730 70.39% 70.39% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 94732366 14.54% 84.94% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 33042086 5.07% 90.01% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 15126484 2.32% 92.33% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 10907840 1.67% 94.01% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 6532170 1.00% 95.01% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 6050361 0.93% 95.94% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 3879708 0.60% 96.53% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 22582448 3.47% 100.00% # Number of insts commited each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.commit.committed_per_cycle::total 651404193 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 448281871 # Number of instructions committed
system.cpu0.commit.committedOps 526607906 # Number of ops (including micro ops) committed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.commit.refs 160623494 # Number of memory references committed
system.cpu0.commit.loads 84307308 # Number of loads committed
system.cpu0.commit.membars 3712250 # Number of memory barriers committed
system.cpu0.commit.branches 100326253 # Number of branches committed
system.cpu0.commit.fp_insts 425629 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 483420006 # Number of committed integer instructions.
system.cpu0.commit.function_calls 13315515 # Number of function calls committed.
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.commit.op_class_0::IntAlu 364753410 69.26% 69.26% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult 1133090 0.22% 69.48% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv 49128 0.01% 69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc 48742 0.01% 69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead 84307308 16.01% 85.51% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite 76316186 14.49% 100.00% # Class of committed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.commit.op_class_0::total 526607906 # Class of committed instruction
system.cpu0.commit.bw_lim_events 22582448 # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads 1230128311 # The number of ROB reads
system.cpu0.rob.rob_writes 1223973004 # The number of ROB writes
system.cpu0.timesIdled 4124129 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 29088448 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 48650709972 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 448281871 # Number of Instructions Simulated
system.cpu0.committedOps 526607906 # Number of Ops (including micro ops) Simulated
system.cpu0.cpi 1.547964 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 1.547964 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.646010 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.646010 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 689327095 # number of integer regfile reads
system.cpu0.int_regfile_writes 407367655 # number of integer regfile writes
system.cpu0.fp_regfile_reads 801695 # number of floating regfile reads
system.cpu0.fp_regfile_writes 483656 # number of floating regfile writes
system.cpu0.cc_regfile_reads 125240184 # number of cc regfile reads
system.cpu0.cc_regfile_writes 126404355 # number of cc regfile writes
system.cpu0.misc_regfile_reads 1208337968 # number of misc regfile reads
system.cpu0.misc_regfile_writes 14686021 # number of misc regfile writes
system.cpu0.dcache.tags.replacements 10424389 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.972987 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 299585117 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 10424901 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 28.737454 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 2716190500 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 307.327232 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 204.645755 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.600249 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.399699 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999947 # Average percentage of cache occupancy
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 165 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.tags.tag_accesses 1321394222 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 1321394222 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 79981443 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 78050702 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 158032145 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 67196950 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 66097721 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 133294671 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 207918 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 193439 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 401357 # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data 180362 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu1.data 144303 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total 324665 # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1756226 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1719412 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 3475638 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2032769 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 1975290 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 4008059 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 147178393 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 144148423 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 291326816 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 147386311 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 144341862 # number of overall hits
system.cpu0.dcache.overall_hits::total 291728173 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 6301112 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 6119243 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 12420355 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 6289754 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 6328811 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 12618565 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 639748 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 640862 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 1280610 # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data 612213 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu1.data 625423 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total 1237636 # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 334540 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 314072 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 648612 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data 8 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 14 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 12590866 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 12448054 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 25038920 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 13230614 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 13088916 # number of overall misses
system.cpu0.dcache.overall_misses::total 26319530 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 113064286500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 108108870000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 221173156500 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 276449168684 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 278428675960 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 554877844644 # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 44578044858 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 46798866739 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total 91376911597 # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4672280500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 4294049500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 8966330000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 152500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 179500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 332000 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 389513455184 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 386537545960 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 776051001144 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 389513455184 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 386537545960 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 776051001144 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 86282555 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 84169945 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 170452500 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 73486704 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 72426532 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 145913236 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 847666 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 834301 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 1681967 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 792575 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 769726 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total 1562301 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2090766 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 2033484 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 4124250 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2032775 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 1975298 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 4008073 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 159769259 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 156596477 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 316365736 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 160616925 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 157430778 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 318047703 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.073029 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.072701 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.072867 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.085590 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.087382 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.086480 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.754717 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.768142 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.761376 # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.772435 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.812527 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total 0.792188 # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.160008 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.154450 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.157268 # miss rate for LoadLockedReq accesses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000003 # miss rate for StoreCondReq accesses
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000004 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000003 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.078807 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.079491 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.079145 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.082374 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.083141 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.082753 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17943.544965 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17667.033324 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 17807.313599 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43952.302218 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 43993.836435 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 43973.133605 # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 72814.600242 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 74827.543501 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 73831.814521 # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13966.283554 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13672.181856 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13823.873132 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25416.666667 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 22437.500000 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23714.285714 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30936.192569 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 31052.046044 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 30993.788915 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 29440.315860 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 29531.669846 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 29485.746939 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 88111611 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 115903 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 3495469 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 1125 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 25.207379 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 103.024889 # average number of cycles each access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.writebacks::writebacks 7991214 # number of writebacks
system.cpu0.dcache.writebacks::total 7991214 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3464471 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3351244 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 6815715 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5224362 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 5266759 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 10491121 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 3656 # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu1.data 3377 # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total 7033 # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 205182 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 192160 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 397342 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 8688833 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 8618003 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 17306836 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 8688833 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 8618003 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 17306836 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2836641 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 2767999 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 5604640 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1065392 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 1062052 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 2127444 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 627345 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 629314 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 1256659 # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 608557 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 622046 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total 1230603 # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 129358 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 121912 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 251270 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 6 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 8 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 14 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 3902033 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 3830051 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 7732084 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 4529378 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 4459365 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 8988743 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16634 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 17045 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33679 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15429 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 18268 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33697 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 32063 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 35313 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 67376 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 49995248000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 48172731500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 98167979500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 49660180532 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 49261074515 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 98921255047 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 12282644500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12531175500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 24813820000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 43753423358 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 45991136239 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 89744559597 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1882000000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1743297500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3625297500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 146500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 171500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 318000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 99655428532 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 97433806015 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 197089234547 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 111938073032 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 109964981515 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 221903054547 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2842965000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2999163000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5842128000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2733695000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3088704498 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5822399498 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5576660000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 6087867498 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11664527498 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032876 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032886 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032881 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014498 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014664 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014580 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.740085 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.754301 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.747137 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.767823 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.808140 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.787686 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061871 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.059952 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060925 # mshr miss rate for LoadLockedReq accesses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000003 # mshr miss rate for StoreCondReq accesses
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000004 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000003 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024423 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024458 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.024440 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028200 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028326 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.028262 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 17624.806241 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17403.449748 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17515.483510 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46612.120733 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46382.921472 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46497.701019 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 19578.771649 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19912.437194 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19745.865824 # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 71897.001198 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 73935.265622 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 72927.304417 # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14548.771626 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14299.638264 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14427.896287 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24416.666667 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21437.500000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22714.285714 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25539.360772 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25439.297287 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25489.794801 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24713.784770 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24659.336366 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24686.772616 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170912.889263 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 175955.588149 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173465.007868 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 177179.013546 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169077.320889 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172786.880078 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 173928.203849 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 172397.346530 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 173125.853390 # average overall mshr uncacheable latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.icache.tags.replacements 15972029 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.921299 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 168505999 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 15972541 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 10.549730 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 23717372500 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 278.025579 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 233.895720 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.543019 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.456828 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999846 # Average percentage of cache occupancy
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.icache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.icache.tags.tag_accesses 201675938 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 201675938 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 85459133 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 83046866 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 168505999 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 85459133 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 83046866 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 168505999 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 85459133 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 83046866 # number of overall hits
system.cpu0.icache.overall_hits::total 168505999 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 8732822 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 8464461 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 17197283 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 8732822 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 8464461 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 17197283 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 8732822 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 8464461 # number of overall misses
system.cpu0.icache.overall_misses::total 17197283 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 117557791336 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 113249081857 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 230806873193 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 117557791336 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 113249081857 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 230806873193 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 117557791336 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 113249081857 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 230806873193 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 94191955 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 91511327 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 185703282 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 94191955 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 91511327 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 185703282 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 94191955 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 91511327 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 185703282 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.092713 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.092496 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.092606 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.092713 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.092496 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.092606 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.092713 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.092496 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.092606 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13461.603974 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13379.361292 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13421.124325 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13461.603974 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13379.361292 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13421.124325 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13461.603974 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13379.361292 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13421.124325 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 124198 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.icache.blocked::no_mshrs 8505 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.602939 # average number of cycles each access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 623432 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 601195 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 1224627 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 623432 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst 601195 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 1224627 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 623432 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst 601195 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 1224627 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8109390 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 7863266 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 15972656 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 8109390 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 7863266 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 15972656 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 8109390 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 7863266 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 15972656 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 13120 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst 7526 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total 20646 # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 13120 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst 7526 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total 20646 # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 103682474880 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 99950191908 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 203632666788 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 103682474880 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 99950191908 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 203632666788 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 103682474880 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 99950191908 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 203632666788 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1675462000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 960778000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2636240000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1675462000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 960778000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 2636240000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.086094 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.085927 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.086012 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.086094 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.085927 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.086012 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.086094 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.085927 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.086012 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12785.483850 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12711.027696 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12748.829424 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12785.483850 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12711.027696 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12748.829424 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12785.483850 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12711.027696 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12748.829424 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 127702.896341 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127661.174595 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 127687.687688 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 127702.896341 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127661.174595 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 127687.687688 # average overall mshr uncacheable latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.branchPred.lookups 127789270 # Number of BP lookups
system.cpu1.branchPred.condPredicted 86858303 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 5584682 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 87369575 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 62601289 # Number of BTB hits
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.branchPred.BTBHitPct 71.651131 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 16643705 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 184713 # Number of incorrect RAS predictions.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.dtb.walker.walks 886728 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 886728 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 16477 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 90200 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore 549590 # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples 337138 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean 2560.840071 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 15205.071993 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-65535 334698 99.28% 99.28% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-131071 1295 0.38% 99.66% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::131072-196607 786 0.23% 99.89% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::196608-262143 134 0.04% 99.93% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::262144-327679 132 0.04% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::327680-393215 32 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::393216-458751 35 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::458752-524287 25 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 337138 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 413502 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 23222.124681 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 18719.794007 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 19687.471539 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535 404370 97.79% 97.79% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071 6829 1.65% 99.44% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1627 0.39% 99.84% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143 122 0.03% 99.87% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679 359 0.09% 99.95% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215 93 0.02% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751 61 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287 23 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823 16 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 413502 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 343450342184 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean 0.162233 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev 0.725616 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-3 342433135184 99.70% 99.70% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-7 558046000 0.16% 99.87% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-11 195137000 0.06% 99.92% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-15 122093500 0.04% 99.96% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-19 46703500 0.01% 99.97% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::20-23 26952500 0.01% 99.98% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::24-27 27089500 0.01% 99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::28-31 34276500 0.01% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::32-35 6435000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::36-39 311500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::40-43 102500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::44-47 19500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::48-51 38500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::52-55 1500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 343450342184 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 90201 84.55% 84.55% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M 16477 15.45% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 106678 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 886728 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 886728 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 106678 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 106678 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 993406 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.dtb.read_hits 101925383 # DTB read hits
system.cpu1.dtb.read_misses 607794 # DTB read misses
system.cpu1.dtb.write_hits 79659263 # DTB write hits
system.cpu1.dtb.write_misses 278934 # DTB write misses
system.cpu1.dtb.flush_tlb 1096 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.dtb.flush_tlb_mva_asid 21110 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 511 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 54027 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 180 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 8646 # Number of TLB faults due to prefetch
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.dtb.perms_faults 55500 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 102533177 # DTB read accesses
system.cpu1.dtb.write_accesses 79938197 # DTB write accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.dtb.hits 181584646 # DTB hits
system.cpu1.dtb.misses 886728 # DTB misses
system.cpu1.dtb.accesses 182471374 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.itb.walker.walks 104027 # Table walker walks requested
system.cpu1.itb.walker.walksLong 104027 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2 2965 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3 70858 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore 14434 # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples 89593 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean 1868.019823 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev 12006.495125 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-32767 88555 98.84% 98.84% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::32768-65535 538 0.60% 99.44% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-98303 104 0.12% 99.56% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::98304-131071 108 0.12% 99.68% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::131072-163839 209 0.23% 99.91% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::163840-196607 38 0.04% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::196608-229375 9 0.01% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::229376-262143 12 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::262144-294911 10 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::294912-327679 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::327680-360447 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 89593 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 88257 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 29154.191735 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 24307.950547 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 23207.189467 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535 86230 97.70% 97.70% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071 592 0.67% 98.37% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607 1228 1.39% 99.77% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143 55 0.06% 99.83% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679 107 0.12% 99.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215 29 0.03% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751 11 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 88257 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 296203153428 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean 1.803727 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 -237987293372 -80.35% -80.35% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1 534122343800 180.32% 99.98% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2 59128000 0.02% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3 7492500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4 1022500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::5 250000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::6 210000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 296203153428 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 70858 95.98% 95.98% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M 2965 4.02% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 73823 # Table walker page sizes translated
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 104027 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 104027 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 73823 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 73823 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 177850 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 91745725 # ITB inst hits
system.cpu1.itb.inst_misses 104027 # ITB inst misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.itb.flush_tlb 1096 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.itb.flush_tlb_mva_asid 21110 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 511 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 40011 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.itb.perms_faults 204194 # Number of TLB faults due to permissions restrictions
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.itb.inst_accesses 91849752 # ITB inst accesses
system.cpu1.itb.hits 91745725 # DTB hits
system.cpu1.itb.misses 104027 # DTB misses
system.cpu1.itb.accesses 91849752 # DTB accesses
system.cpu1.numCycles 682447871 # number of cpu cycles simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.fetch.icacheStallCycles 237751767 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 569981698 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 127789270 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 79244994 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 403874148 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 12747214 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 2621326 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles 22891 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles 5452 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles 5355964 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 162889 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 2912 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 91518882 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 3441613 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 41515 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 656170682 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 1.017476 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.271778 # Number of instructions fetched each cycle (Total)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.fetch.rateDist::0 515442690 78.55% 78.55% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 17560626 2.68% 81.23% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 17609646 2.68% 83.91% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 13074345 1.99% 85.91% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 27836031 4.24% 90.15% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 8626345 1.31% 91.46% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 9437454 1.44% 92.90% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 8134103 1.24% 94.14% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 38449442 5.86% 100.00% # Number of instructions fetched each cycle (Total)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.fetch.rateDist::total 656170682 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.187251 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.835202 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 193456459 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 342166734 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 102287783 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 13239744 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 5017523 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 18910299 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 1375576 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 622643781 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 4236982 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 5017523 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 200842686 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 30883178 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 258887608 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 108004065 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 52532870 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 608141114 # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents 110721 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 2023681 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents 1854971 # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents 33287436 # Number of times rename has blocked due to SQ full
system.cpu1.rename.FullRegisterEvents 3642 # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands 582179449 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 939040277 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 719307421 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 813140 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 491677026 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 90502418 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 15019602 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 13109435 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 74431382 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 97738010 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 83701683 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 13087583 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 14003001 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 577050532 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 15100250 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 578680532 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 823139 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 76206595 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 48603059 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 352691 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 656170682 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.881905 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.622817 # Number of insts issued each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.iq.issued_per_cycle::0 428729858 65.34% 65.34% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 96527772 14.71% 80.05% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 41990375 6.40% 86.45% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 29917551 4.56% 91.01% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 22305055 3.40% 94.41% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 15606448 2.38% 96.79% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 10670315 1.63% 98.41% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 6241457 0.95% 99.36% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 4181851 0.64% 100.00% # Number of insts issued each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.iq.issued_per_cycle::total 656170682 # Number of insts issued each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.iq.fu_full::IntAlu 2907149 25.23% 25.23% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 25340 0.22% 25.45% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 2712 0.02% 25.47% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.47% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.47% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.47% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.47% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.47% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.47% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.47% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.47% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.47% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.47% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.47% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.47% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.47% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.47% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.47% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.47% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.47% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.47% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.47% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.47% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.47% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.47% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 2 0.00% 25.47% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.47% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.47% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.47% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 4700245 40.79% 66.27% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 3886684 33.73% 100.00% # attempts to use FU when none available
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 392511580 67.83% 67.83% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 1384098 0.24% 68.07% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 66455 0.01% 68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 76 0.00% 68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 5 0.00% 68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 1 0.00% 68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.08% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 71678 0.01% 68.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.09% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.09% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 103950145 17.96% 86.06% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 80696483 13.94% 100.00% # Type of FU issued
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.iq.FU_type_0::total 578680532 # Type of FU issued
system.cpu1.iq.rate 0.847948 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 11522132 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.019911 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 1824781458 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 668482518 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 557668794 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 1095559 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 542505 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 489305 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 589617138 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 585515 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 4580122 # Number of loads that had data forwarded from stores
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.iew.lsq.thread0.squashedLoads 15421998 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 21561 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 678629 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 8522052 # Number of stores squashed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.iew.lsq.thread0.rescheduledLoads 3766919 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 7862357 # Number of times an access to memory failed due to the cache being blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.iew.iewSquashCycles 5017523 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 16098124 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 12731672 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 592283961 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 1683866 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 97738010 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 83701683 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 12822867 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 226624 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 12419238 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 678629 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 2534874 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 2203490 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 4738364 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 572262856 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 101914202 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 5543088 # Number of squashed instructions skipped in execute
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.iew.exec_swp 0 # number of swp insts executed
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.iew.exec_nop 133179 # number of nop insts executed
system.cpu1.iew.exec_refs 181576481 # number of memory reference insts executed
system.cpu1.iew.exec_branches 105801109 # Number of branches executed
system.cpu1.iew.exec_stores 79662279 # Number of stores executed
system.cpu1.iew.exec_rate 0.838544 # Inst execution rate
system.cpu1.iew.wb_sent 559345130 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 558158099 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 275625677 # num instructions producing a value
system.cpu1.iew.wb_consumers 478553206 # num instructions consuming a value
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.iew.wb_rate 0.817877 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.575956 # average fanout of values written-back
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.commit.commitSquashedInsts 76251521 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 14747559 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 4228324 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 643144454 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.802221 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.802123 # Number of insts commited each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.commit.committed_per_cycle::0 453619473 70.53% 70.53% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 93903191 14.60% 85.13% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 31983690 4.97% 90.11% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 14866669 2.31% 92.42% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 10513323 1.63% 94.05% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 6352313 0.99% 95.04% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 5895751 0.92% 95.96% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 3796111 0.59% 96.55% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 22213933 3.45% 100.00% # Number of insts commited each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.commit.committed_per_cycle::total 643144454 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 438937419 # Number of instructions committed
system.cpu1.commit.committedOps 515944182 # Number of ops (including micro ops) committed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.commit.refs 157495642 # Number of memory references committed
system.cpu1.commit.loads 82316011 # Number of loads committed
system.cpu1.commit.membars 3580111 # Number of memory barriers committed
system.cpu1.commit.branches 97766699 # Number of branches committed
system.cpu1.commit.fp_insts 469643 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 473710297 # Number of committed integer instructions.
system.cpu1.commit.function_calls 12866382 # Number of function calls committed.
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.commit.op_class_0::IntAlu 357259636 69.24% 69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult 1077544 0.21% 69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv 49642 0.01% 69.46% # Class of committed instruction
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.46% # Class of committed instruction
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.46% # Class of committed instruction
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.46% # Class of committed instruction
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.46% # Class of committed instruction
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.46% # Class of committed instruction
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.commit.op_class_0::SimdFloatMisc 61718 0.01% 69.47% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.47% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.47% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.47% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead 82316011 15.95% 85.43% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite 75179631 14.57% 100.00% # Class of committed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu1.commit.op_class_0::total 515944182 # Class of committed instruction
system.cpu1.commit.bw_lim_events 22213933 # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads 1209227164 # The number of ROB reads
system.cpu1.rob.rob_writes 1197436777 # The number of ROB writes
system.cpu1.timesIdled 3994160 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 26277189 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 52630560458 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 438937419 # Number of Instructions Simulated
system.cpu1.committedOps 515944182 # Number of Ops (including micro ops) Simulated
system.cpu1.cpi 1.554773 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 1.554773 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.643181 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.643181 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 675192691 # number of integer regfile reads
system.cpu1.int_regfile_writes 398302134 # number of integer regfile writes
system.cpu1.fp_regfile_reads 877858 # number of floating regfile reads
system.cpu1.fp_regfile_writes 519852 # number of floating regfile writes
system.cpu1.cc_regfile_reads 122926890 # number of cc regfile reads
system.cpu1.cc_regfile_writes 124034847 # number of cc regfile writes
system.cpu1.misc_regfile_reads 1190535376 # number of misc regfile reads
system.cpu1.misc_regfile_writes 14866281 # number of misc regfile writes
system.iobus.trans_dist::ReadReq 40297 # Transaction distribution
system.iobus.trans_dist::ReadResp 40297 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230952 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 230952 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.iobus.pkt_count::total 353736 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334240 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7334240 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.iobus.pkt_size::total 7492160 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.iobus.reqLayer27.occupancy 565947735 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.iobus.respLayer3.occupancy 147712000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.iocache.tags.replacements 115457 # number of replacements
system.iocache.tags.tagsinuse 10.423099 # Cycle average of tags in use
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.iocache.tags.sampled_refs 115473 # Sample count of references to valid blocks.
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.iocache.tags.warmup_cycle 13100950743000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 3.543553 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 6.879545 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.221472 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.429972 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.651444 # Average percentage of cache occupancy
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.iocache.tags.tag_accesses 1039641 # Number of tag accesses
system.iocache.tags.data_accesses 1039641 # Number of data accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.iocache.ReadReq_misses::realview.ide 8812 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8849 # number of ReadReq misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.iocache.demand_misses::realview.ide 8812 # number of demand (read+write) misses
system.iocache.demand_misses::total 8852 # number of demand (read+write) misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.iocache.overall_misses::realview.ide 8812 # number of overall misses
system.iocache.overall_misses::total 8852 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet 5085000 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide 1678499822 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 1683584822 # number of ReadReq miss cycles
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.iocache.WriteLineReq_miss_latency::realview.ide 13828150913 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 13828150913 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet 5436000 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide 1678499822 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 1683935822 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet 5436000 # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide 1678499822 # number of overall miss cycles
system.iocache.overall_miss_latency::total 1683935822 # number of overall miss cycles
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.iocache.ReadReq_accesses::realview.ide 8812 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8849 # number of ReadReq accesses(hits+misses)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.iocache.demand_accesses::realview.ide 8812 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 8852 # number of demand (read+write) accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.iocache.overall_accesses::realview.ide 8812 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 8852 # number of overall (read+write) accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137432.432432 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 190478.872220 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 190257.071081 # average ReadReq miss latency
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129642.155863 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 129642.155863 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 135900 # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 190478.872220 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 190232.243787 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 135900 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 190478.872220 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 190232.243787 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 34183 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.iocache.blocked::no_mshrs 3488 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.iocache.avg_blocked_cycles::no_mshrs 9.800172 # average number of cycles each access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.cache_copies 0 # number of cache copies performed
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.writebacks::writebacks 106630 # number of writebacks
system.iocache.writebacks::total 106630 # number of writebacks
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.iocache.ReadReq_mshr_misses::realview.ide 8812 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 8849 # number of ReadReq MSHR misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.iocache.demand_mshr_misses::realview.ide 8812 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 8852 # number of demand (read+write) MSHR misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.iocache.overall_mshr_misses::realview.ide 8812 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 8852 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3235000 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1237899822 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 1241134822 # number of ReadReq MSHR miss cycles
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8494950913 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 8494950913 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet 3436000 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 1237899822 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 1241335822 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet 3436000 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 1237899822 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 1241335822 # number of overall MSHR miss cycles
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87432.432432 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 140478.872220 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 140257.071081 # average ReadReq mshr miss latency
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79642.155863 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79642.155863 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85900 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 140478.872220 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 140232.243787 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85900 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 140478.872220 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 140232.243787 # average overall mshr miss latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.l2c.tags.replacements 1325572 # number of replacements
system.l2c.tags.tagsinuse 65300.626435 # Cycle average of tags in use
system.l2c.tags.total_refs 49426863 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 1388345 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 35.601283 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 22417690500 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 35099.515174 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 181.714209 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 264.901724 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 3752.412980 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 11620.218077 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 175.372061 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 249.085946 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 3742.787723 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 10214.618542 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.535576 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002773 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.004042 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.057257 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.177310 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002676 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.003801 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.057110 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.155863 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.996408 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023 309 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 62464 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 305 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 528 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 2753 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 5058 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 54000 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.004715 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.953125 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 438866823 # Number of tag accesses
system.l2c.tags.data_accesses 438866823 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 522786 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 189596 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 519108 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 186433 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1417923 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 7991214 # number of Writeback hits
system.l2c.Writeback_hits::total 7991214 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 5012 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 4909 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 9921 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 7 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 12 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 792043 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 793357 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 1585400 # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst 8059683 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst 7819802 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total 15879485 # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 3433496 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 3365802 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 6799298 # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data 362601 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data 360924 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total 723525 # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker 522786 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 189596 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 8059683 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 4225539 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 519108 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 186433 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 7819802 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 4159159 # number of demand (read+write) hits
system.l2c.demand_hits::total 25682106 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 522786 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 189596 # number of overall hits
system.l2c.overall_hits::cpu0.inst 8059683 # number of overall hits
system.l2c.overall_hits::cpu0.data 4225539 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 519108 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 186433 # number of overall hits
system.l2c.overall_hits::cpu1.inst 7819802 # number of overall hits
system.l2c.overall_hits::cpu1.data 4159159 # number of overall hits
system.l2c.overall_hits::total 25682106 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 2462 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 2334 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 2152 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker 1980 # number of ReadReq misses
system.l2c.ReadReq_misses::total 8928 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 17966 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 17816 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 35782 # number of UpgradeReq misses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.l2c.ReadExReq_misses::cpu0.data 256677 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 251876 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 508553 # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst 49575 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst 43384 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total 92959 # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 153543 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 147517 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 301060 # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data 245956 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data 261122 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total 507078 # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker 2462 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 2334 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 49575 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 410220 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 2152 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 1980 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 43384 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 399393 # number of demand (read+write) misses
system.l2c.demand_misses::total 911500 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 2462 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 2334 # number of overall misses
system.l2c.overall_misses::cpu0.inst 49575 # number of overall misses
system.l2c.overall_misses::cpu0.data 410220 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 2152 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 1980 # number of overall misses
system.l2c.overall_misses::cpu1.inst 43384 # number of overall misses
system.l2c.overall_misses::cpu1.data 399393 # number of overall misses
system.l2c.overall_misses::total 911500 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 341090000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 324451500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 295493500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker 271039500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 1232074500 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 743559500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 726622500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 1470182000 # number of UpgradeReq miss cycles
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 81000 # number of SCUpgradeReq miss cycles
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 81000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 162000 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 38224402000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 37800818000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 76025220000 # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst 6708035000 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 5866905500 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total 12574940500 # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data 21567558000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data 20709037500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 42276595500 # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu0.data 38310507500 # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data 40517146000 # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total 78827653500 # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 341090000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 324451500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 6708035000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 59791960000 # number of demand (read+write) miss cycles
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system.l2c.demand_miss_latency::cpu1.inst 5866905500 # number of demand (read+write) miss cycles
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system.l2c.demand_miss_latency::total 132108830500 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 341090000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 324451500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 6708035000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 59791960000 # number of overall miss cycles
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system.l2c.overall_miss_latency::cpu1.itb.walker 271039500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 5866905500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 58509855500 # number of overall miss cycles
system.l2c.overall_miss_latency::total 132108830500 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 525248 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 191930 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 521260 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 188413 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1426851 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 7991214 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 7991214 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 22978 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 22725 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 45703 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 6 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 8 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 14 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 1048720 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 1045233 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 2093953 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst 8109258 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst 7863186 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total 15972444 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 3587039 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 3513319 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 7100358 # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data 608557 # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data 622046 # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total 1230603 # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 525248 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 191930 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 8109258 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 4635759 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 521260 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 188413 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 7863186 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 4558552 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 26593606 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 525248 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 191930 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 8109258 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 4635759 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 521260 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 188413 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 7863186 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 4558552 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 26593606 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.004687 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.012161 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.004128 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.010509 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.006257 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.781878 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.783982 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.782925 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.166667 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.125000 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.142857 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.244753 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.240976 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.242867 # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.006113 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.005517 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total 0.005820 # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.042805 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.041988 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.042401 # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data 0.404163 # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data 0.419779 # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total 0.412057 # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.004687 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.012161 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.006113 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.088490 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.004128 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker 0.010509 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.005517 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.087614 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.034275 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.004687 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.012161 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.006113 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.088490 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.004128 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker 0.010509 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.005517 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.087614 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.034275 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 138541.835906 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 139010.925450 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 137311.105948 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 136888.636364 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 138001.176075 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 41387.036625 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 40784.828244 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 41087.194679 # average UpgradeReq miss latency
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 81000 # average SCUpgradeReq miss latency
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 81000 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 81000 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 148920.246068 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 150077.093490 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 149493.209164 # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 135310.842158 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 135232.009497 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 135274.050926 # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 140465.915086 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140384.074378 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 140425.813791 # average ReadSharedReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 155761.630129 # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 155165.577776 # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::total 155454.690403 # average InvalidateReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 138541.835906 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 139010.925450 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 135310.842158 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 145755.838331 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 137311.105948 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 136888.636364 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 135232.009497 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 146496.947868 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 144935.634120 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 138541.835906 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 139010.925450 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 135310.842158 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 145755.838331 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 137311.105948 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 136888.636364 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 135232.009497 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 146496.947868 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 144935.634120 # average overall miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.l2c.writebacks::writebacks 1117221 # number of writebacks
system.l2c.writebacks::total 1117221 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.dtb.walker 15 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.itb.walker 27 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.dtb.walker 8 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.itb.walker 32 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 2 # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data 8 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data 14 # number of ReadSharedReq MSHR hits
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.ReadSharedReq_mshr_hits::total 22 # number of ReadSharedReq MSHR hits
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.l2c.demand_mshr_hits::cpu0.dtb.walker 15 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.itb.walker 27 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data 8 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.dtb.walker 8 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.itb.walker 32 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data 14 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 107 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.dtb.walker 15 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.itb.walker 27 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data 8 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.dtb.walker 8 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.itb.walker 32 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data 14 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 107 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 2447 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2307 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2144 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1948 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 8846 # number of ReadReq MSHR misses
system.l2c.CleanEvict_mshr_misses::writebacks 1095 # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total 1095 # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 17966 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 17816 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 35782 # number of UpgradeReq MSHR misses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1 # number of SCUpgradeReq MSHR misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1 # number of SCUpgradeReq MSHR misses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.l2c.ReadExReq_mshr_misses::cpu0.data 256677 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 251876 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 508553 # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 49574 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 43382 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total 92956 # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data 153535 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 147503 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total 301038 # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu0.data 245956 # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data 261122 # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total 507078 # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker 2447 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker 2307 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 49574 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 410212 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 2144 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker 1948 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 43382 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 399379 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 911393 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker 2447 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker 2307 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 49574 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 410212 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 2144 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker 1948 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 43382 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 399379 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 911393 # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 13120 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data 16634 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 7526 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 17045 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total 54325 # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data 15429 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 18268 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total 33697 # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 13120 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data 32063 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 7526 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 35313 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total 88022 # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 314681500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 298236000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 273201000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 247501500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 1133620000 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1271061500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 1260406999 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 2531468499 # number of UpgradeReq MSHR miss cycles
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 71000 # number of SCUpgradeReq MSHR miss cycles
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 71000 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 142000 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 35657632000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 35282058000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 70939690000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 6212266000 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 5433048000 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total 11645314000 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 20031221000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 19232396500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 39263617500 # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 35850947500 # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 37905926000 # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total 73756873500 # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 314681500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 298236000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 6212266000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 55688853000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 273201000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 247501500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 5433048000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 54514454500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 122982241500 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 314681500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 298236000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 6212266000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 55688853000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 273201000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 247501500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 5433048000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 54514454500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 122982241500 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1472102000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2635039000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 844005498 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2786100500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 7737246998 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2556241000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2877054000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 5433295000 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1472102000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5191280000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 844005498 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5663154500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 13170541998 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.004659 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.012020 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.004113 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.010339 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.006200 # mshr miss rate for ReadReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.781878 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.783982 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.782925 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.166667 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.125000 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.142857 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.244753 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.240976 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.242867 # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.006113 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005517 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.005820 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.042803 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.041984 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.042398 # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.404163 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.419779 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total 0.412057 # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.004659 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.012020 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.006113 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.088489 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.004113 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.010339 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005517 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.087611 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.034271 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.004659 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.012020 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.006113 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.088489 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.004113 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.010339 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005517 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.087611 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.034271 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 128598.896608 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 129274.382315 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 127425.839552 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 127054.158111 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 128150.576532 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70748.163197 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70745.790245 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70746.981695 # average UpgradeReq mshr miss latency
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71000 # average SCUpgradeReq mshr miss latency
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71000 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71000 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 138920.246068 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 140077.093490 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 139493.209164 # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 125312.986646 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 125237.379558 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 125277.701278 # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 130466.805614 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130386.476885 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 130427.446037 # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 145761.630129 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 145165.577776 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 145454.690403 # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 128598.896608 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 129274.382315 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125312.986646 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 135756.274804 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 127425.839552 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 127054.158111 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125237.379558 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 136498.049472 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 134938.760227 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 128598.896608 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 129274.382315 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125312.986646 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 135756.274804 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 127425.839552 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 127054.158111 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125237.379558 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 136498.049472 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 134938.760227 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112202.896341 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158412.829145 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 112145.296040 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163455.588149 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 142425.163332 # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165677.684879 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 157491.460477 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 161239.724605 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112202.896341 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 161908.742164 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 112145.296040 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 160370.246085 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 149627.843017 # average overall mshr uncacheable latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::ReadReq 54325 # Transaction distribution
system.membus.trans_dist::ReadResp 466014 # Transaction distribution
system.membus.trans_dist::WriteReq 33697 # Transaction distribution
system.membus.trans_dist::WriteResp 33697 # Transaction distribution
system.membus.trans_dist::Writeback 1223851 # Transaction distribution
system.membus.trans_dist::CleanEvict 214858 # Transaction distribution
system.membus.trans_dist::UpgradeReq 36602 # Transaction distribution
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::UpgradeResp 36604 # Transaction distribution
system.membus.trans_dist::ReadExReq 1014814 # Transaction distribution
system.membus.trans_dist::ReadExResp 1014814 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 411689 # Transaction distribution
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution
system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6862 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4279818 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 4409460 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342041 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 342041 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 4751501 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 2148 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13724 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 163529836 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 163701542 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7254464 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7254464 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 170956006 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 2794 # Total snoops (count)
system.membus.snoop_fanout::samples 3098842 # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.membus.snoop_fanout::1 3098842 100.00% 100.00% # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.membus.snoop_fanout::total 3098842 # Request fanout histogram
system.membus.reqLayer0.occupancy 114250999 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.membus.reqLayer1.occupancy 50156 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.membus.reqLayer2.occupancy 5591500 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.membus.reqLayer5.occupancy 8287460048 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.membus.respLayer2.occupancy 7742269755 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.membus.respLayer3.occupancy 228310464 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 18 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks
stats: Update ARM stats to include programmable oscillators
2015-08-07 16:39:17 +02:00
system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks
system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks
system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks
system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks
system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks
system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_filter.tot_requests 53652655 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 27255089 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 4361 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 2133 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 2133 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq 2023578 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 25097341 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 33697 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 33697 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 9215084 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 18618130 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 45706 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 14 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 45720 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 2093953 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 2093953 # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq 15972656 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 7109207 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 1337267 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp 1230603 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47955066 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31500258 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 906342 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2489762 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 82851428 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1023557760 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1100111846 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3042744 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8372064 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 2135084414 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 2099930 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 56453563 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.014593 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.119915 # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::0 55629759 98.54% 98.54% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 823804 1.46% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 56453563 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 35456582958 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoopLayer0.occupancy 1421406 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.toL2Bus.respLayer0.occupancy 24004091061 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.toL2Bus.respLayer1.occupancy 14485026242 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.toL2Bus.respLayer2.occupancy 526450560 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.toL2Bus.respLayer3.occupancy 1445956414 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.kern.inst.quiesce 19211 # number of quiesce instructions executed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink