2006-09-01 23:59:36 +02:00
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|
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|
|
|
|
---------- Begin Simulation Statistics ----------
|
2010-05-14 05:45:59 +02:00
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|
|
host_inst_rate 84020 # Simulator instruction rate (inst/s)
|
|
|
|
|
host_mem_usage 204400 # Number of bytes of host memory used
|
|
|
|
|
host_seconds 0.08 # Real time elapsed on the host
|
|
|
|
|
host_tick_rate 163850067 # Simulator tick rate (ticks/s)
|
2006-09-01 23:59:36 +02:00
|
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
2008-12-05 18:09:29 +01:00
|
|
|
sim_insts 6386 # Number of instructions simulated
|
2008-08-04 00:13:29 +02:00
|
|
|
sim_seconds 0.000012 # Number of seconds simulated
|
2010-05-14 05:45:59 +02:00
|
|
|
sim_ticks 12497500 # Number of ticks simulated
|
2009-03-07 23:30:55 +01:00
|
|
|
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.BPredUnit.BTBHits 692 # Number of BTB hits
|
|
|
|
|
system.cpu.BPredUnit.BTBLookups 1820 # Number of BTB lookups
|
|
|
|
|
system.cpu.BPredUnit.RASInCorrect 65 # Number of incorrect RAS predictions.
|
|
|
|
|
system.cpu.BPredUnit.condIncorrect 443 # Number of conditional branches incorrect
|
|
|
|
|
system.cpu.BPredUnit.condPredicted 1337 # Number of conditional branches predicted
|
|
|
|
|
system.cpu.BPredUnit.lookups 2245 # Number of BP lookups
|
|
|
|
|
system.cpu.BPredUnit.usedRAS 315 # Number of times the RAS was used to get a target.
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.commit.COM:branches 1051 # Number of branches committed
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.commit.COM:bw_lim_events 119 # number cycles where commit BW limit reached
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle::samples 12431 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.COM:committed_per_cycle::mean 0.515083 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.COM:committed_per_cycle::stdev 1.305811 # Number of insts commited each cycle
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle::0-1 9528 76.65% 76.65% # Number of insts commited each cycle
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|
|
|
|
system.cpu.commit.COM:committed_per_cycle::1-2 1629 13.10% 89.75% # Number of insts commited each cycle
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|
|
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|
system.cpu.commit.COM:committed_per_cycle::2-3 491 3.95% 93.70% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.COM:committed_per_cycle::3-4 259 2.08% 95.78% # Number of insts commited each cycle
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|
|
|
|
system.cpu.commit.COM:committed_per_cycle::4-5 156 1.25% 97.04% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.COM:committed_per_cycle::5-6 104 0.84% 97.88% # Number of insts commited each cycle
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle::6-7 96 0.77% 98.65% # Number of insts commited each cycle
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle::7-8 49 0.39% 99.04% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.COM:committed_per_cycle::8 119 0.96% 100.00% # Number of insts commited each cycle
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle::total 12431 # Number of insts commited each cycle
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.commit.COM:count 6403 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.COM:loads 1185 # Number of loads committed
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.commit.COM:refs 2050 # Number of memory references committed
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.commit.branchMispredicts 369 # The number of times a branch was mispredicted
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.commit.commitSquashedInsts 4622 # The number of squashed insts skipped by commit
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.committedInsts 6386 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 6386 # Number of Instructions Simulated
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.cpi 3.914187 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 3.914187 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 1782 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 34993.902439 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36257.425743 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 1618 # number of ReadReq hits
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|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 5739000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.092031 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 164 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 63 # number of ReadReq MSHR hits
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|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 3662000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.056678 # mshr miss rate for ReadReq accesses
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses)
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 35082.894737 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35729.885057 # average WriteReq mshr miss latency
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.dcache.WriteReq_hits 485 # number of WriteReq hits
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.dcache.WriteReq_miss_latency 13331500 # number of WriteReq miss cycles
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.439306 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 380 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 293 # number of WriteReq MSHR hits
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 3108500 # number of WriteReq MSHR miss cycles
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses
|
2007-08-04 00:04:30 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.dcache.avg_refs 12.275862 # Average number of references to valid blocks.
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.dcache.demand_accesses 2647 # number of demand (read+write) accesses
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|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 35056.066176 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 36013.297872 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_hits 2103 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 19070500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.205516 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_misses 544 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 356 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 6770500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.071024 # mshr miss rate for demand accesses
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.dcache.demand_mshr_misses 188 # number of demand (read+write) MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.dcache.occ_%::0 0.026868 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.occ_blocks::0 110.050975 # Average occupied blocks per context
|
|
|
|
|
system.cpu.dcache.overall_accesses 2647 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 35056.066176 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 36013.297872 # average overall mshr miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.dcache.overall_hits 2103 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 19070500 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.205516 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_misses 544 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 356 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 6770500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.071024 # mshr miss rate for overall accesses
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.dcache.overall_mshr_misses 188 # number of overall MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.dcache.tagsinuse 110.050975 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 2136 # Total number of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.writebacks 0 # number of writebacks
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.decode.DECODE:BlockedCycles 1123 # Number of cycles decode is blocked
|
|
|
|
|
system.cpu.decode.DECODE:BranchMispred 75 # Number of times decode detected a branch misprediction
|
|
|
|
|
system.cpu.decode.DECODE:BranchResolved 188 # Number of times decode resolved a branch
|
|
|
|
|
system.cpu.decode.DECODE:DecodedInsts 12474 # Number of instructions handled by decode
|
|
|
|
|
system.cpu.decode.DECODE:IdleCycles 8945 # Number of cycles decode is idle
|
|
|
|
|
system.cpu.decode.DECODE:RunCycles 2313 # Number of cycles decode is running
|
|
|
|
|
system.cpu.decode.DECODE:SquashCycles 900 # Number of cycles decode is squashing
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.decode.DECODE:SquashedInsts 209 # Number of squashed instructions handled by decode
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.decode.DECODE:UnblockCycles 50 # Number of cycles decode is unblocking
|
|
|
|
|
system.cpu.dtb.data_accesses 2948 # DTB accesses
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.dtb.data_hits 2887 # DTB hits
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu.dtb.data_misses 61 # DTB misses
|
|
|
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
|
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
|
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
|
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.dtb.read_accesses 1865 # DTB read accesses
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.dtb.read_hits 1829 # DTB read hits
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.dtb.read_misses 36 # DTB read misses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.dtb.write_accesses 1083 # DTB write accesses
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.dtb.write_hits 1058 # DTB write hits
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.dtb.write_misses 25 # DTB write misses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.fetch.Branches 2245 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu.fetch.CacheLines 1792 # Number of cache lines fetched
|
|
|
|
|
system.cpu.fetch.Cycles 4238 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu.fetch.Insts 13309 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu.fetch.SquashCycles 504 # Number of cycles fetch has spent squashing
|
|
|
|
|
system.cpu.fetch.branchRate 0.089814 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu.fetch.icacheStallCycles 1792 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu.fetch.predictedBranches 1007 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu.fetch.rate 0.532445 # Number of inst fetches per cycle
|
|
|
|
|
system.cpu.fetch.rateDist::samples 13331 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::mean 0.998350 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::stdev 2.390717 # Number of instructions fetched each cycle (Total)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.fetch.rateDist::0-1 10920 81.91% 81.91% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::1-2 245 1.84% 83.75% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::2-3 221 1.66% 85.41% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::3-4 185 1.39% 86.80% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::4-5 233 1.75% 88.55% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::5-6 164 1.23% 89.78% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::6-7 228 1.71% 91.49% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::7-8 133 1.00% 92.48% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::8 1002 7.52% 100.00% # Number of instructions fetched each cycle (Total)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.fetch.rateDist::total 13331 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 1792 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 35303.990610 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35283.387622 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_hits 1366 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 15039500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.237723 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_misses 426 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 119 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 10832000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.171317 # mshr miss rate for ReadReq accesses
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.avg_refs 4.449511 # Average number of references to valid blocks.
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.demand_accesses 1792 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 35303.990610 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_hits 1366 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_miss_latency 15039500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.237723 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_misses 426 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 119 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 10832000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.171317 # mshr miss rate for demand accesses
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.icache.demand_mshr_misses 307 # number of demand (read+write) MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.occ_%::0 0.077094 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.occ_blocks::0 157.888110 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.overall_accesses 1792 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 35303.990610 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.overall_hits 1366 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_miss_latency 15039500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.237723 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_misses 426 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 119 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 10832000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.171317 # mshr miss rate for overall accesses
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.icache.overall_mshr_misses 307 # number of overall MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.icache.replacements 0 # number of replacements
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.icache.sampled_refs 307 # Sample count of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.icache.tagsinuse 157.888110 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 1366 # Total number of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.idleCycles 11665 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.iew.EXEC:branches 1448 # Number of branches executed
|
|
|
|
|
system.cpu.iew.EXEC:nop 83 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.EXEC:rate 0.362498 # Inst execution rate
|
|
|
|
|
system.cpu.iew.EXEC:refs 2956 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.EXEC:stores 1085 # Number of stores executed
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iew.WB:consumers 6049 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.WB:count 8759 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.WB:fanout 0.745247 # average fanout of values written-back
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iew.WB:producers 4508 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.WB:rate 0.350416 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.WB:sent 8858 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.branchMispredicts 427 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewBlockCycles 73 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 2269 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 191 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 1271 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 11059 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 1871 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 304 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 9061 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2007-04-22 20:50:37 +02:00
|
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 900 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.forwLoads 46 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 64 # Number of memory ordering violations
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 1084 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedStores 406 # Number of stores squashed
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.iew.memOrderViolationEvents 64 # Number of memory order violations
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 302 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.ipc 0.255481 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.255481 # IPC: Total IPC of All Threads
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntAlu 6287 67.13% 67.15% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% 67.16% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.16% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 67.19% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.19% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.19% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.19% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.19% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.19% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::MemRead 1968 21.01% 88.20% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::MemWrite 1105 11.80% 100.00% # Type of FU issued
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::total 9365 # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 92 # FU busy when requested
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.009824 # FU busy rate (busy events/executed inst)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full::IntAlu 1 1.09% 1.09% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 1.09% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.09% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.09% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.09% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.09% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.09% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.09% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.09% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::MemRead 56 60.87% 61.96% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::MemWrite 35 38.04% 100.00% # attempts to use FU when none available
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::samples 13331 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::mean 0.702498 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.304735 # Number of insts issued each cycle
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::0-1 9142 68.58% 68.58% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::1-2 1697 12.73% 81.31% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::2-3 1062 7.97% 89.27% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::3-4 730 5.48% 94.75% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::4-5 359 2.69% 97.44% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::5-6 188 1.41% 98.85% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::6-7 105 0.79% 99.64% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::7-8 36 0.27% 99.91% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::total 13331 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:rate 0.374660 # Inst issue rate
|
|
|
|
|
system.cpu.iq.iqInstsAdded 10951 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqInstsIssued 9365 # Number of instructions issued
|
|
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu.iq.iqSquashedInstsExamined 4181 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 44 # Number of squashed instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 2504 # Number of squashed operands that are examined and possibly removed from graph
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
|
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
|
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
|
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.itb.fetch_accesses 1827 # ITB accesses
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.itb.fetch_hits 1792 # ITB hits
|
|
|
|
|
system.cpu.itb.fetch_misses 35 # ITB misses
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34465.753425 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31376.712329 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 2516000 # number of ReadExReq miss cycles
|
2007-08-04 00:04:30 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2290500 # number of ReadExReq MSHR miss cycles
|
2007-08-04 00:04:30 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.l2cache.ReadReq_accesses 408 # number of ReadReq accesses(hits+misses)
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34418.918919 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31239.557740 # average ReadReq mshr miss latency
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 14008500 # number of ReadReq miss cycles
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.997549 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 407 # number of ReadReq misses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 12714500 # number of ReadReq MSHR miss cycles
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997549 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 407 # number of ReadReq MSHR misses
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34250 # average UpgradeReq miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31035.714286 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_latency 479500 # number of UpgradeReq miss cycles
|
2007-08-04 00:04:30 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 434500 # number of UpgradeReq MSHR miss cycles
|
2007-08-04 00:04:30 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.l2cache.avg_refs 0.002545 # Average number of references to valid blocks.
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34426.041667 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31260.416667 # average overall mshr miss latency
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.demand_miss_latency 16524500 # number of demand (read+write) miss cycles
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.l2cache.demand_miss_rate 0.997921 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 15005000 # number of demand (read+write) MSHR miss cycles
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.997921 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.occ_%::0 0.006535 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_blocks::0 214.135921 # Average occupied blocks per context
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34426.041667 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31260.416667 # average overall mshr miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.l2cache.overall_hits 1 # number of overall hits
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.overall_miss_latency 16524500 # number of overall miss cycles
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.l2cache.overall_miss_rate 0.997921 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_misses 480 # number of overall misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 15005000 # number of overall MSHR miss cycles
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.997921 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 214.135921 # Cycle average of tags in use
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
2009-03-07 23:30:55 +01:00
|
|
|
system.cpu.memDep0.conflictingLoads 36 # Number of conflicting loads.
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.memDep0.conflictingStores 26 # Number of conflicting stores.
|
|
|
|
|
system.cpu.memDep0.insertedLoads 2269 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.insertedStores 1271 # Number of stores inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.numCycles 24996 # number of cpu cycles simulated
|
|
|
|
|
system.cpu.rename.RENAME:BlockCycles 340 # Number of cycles rename is blocking
|
2008-12-05 18:09:29 +01:00
|
|
|
system.cpu.rename.RENAME:CommittedMaps 4583 # Number of HB maps that are committed
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.rename.RENAME:IQFullEvents 9 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.RENAME:IdleCycles 9098 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.RENAME:LSQFullEvents 255 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu.rename.RENAME:RenameLookups 15174 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.RENAME:RenamedInsts 12043 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.RENAME:RenamedOperands 8961 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RENAME:RunCycles 2203 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.RENAME:SquashCycles 900 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.RENAME:UnblockCycles 292 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RENAME:UndoneMaps 4378 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.RENAME:serializeStallCycles 498 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RENAME:serializingInsts 28 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.RENAME:skidInsts 750 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu.timesIdled 240 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
