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gem5/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt

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Update ref stats. tests/test1/ref/alpha/atomic/stdout: tests/test1/ref/alpha/detailed/stderr: tests/test1/ref/alpha/detailed/stdout: tests/test1/ref/alpha/timing/stdout: Updated output. --HG-- extra : convert_revision : 3189564725ac4d2b3d63e6a71151a52326f8d416
2006-07-27 23:47:43 +02:00
---------- Begin Simulation Statistics ----------
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
sim_seconds 1.954691 # Number of seconds simulated
sim_ticks 1954691371500 # Number of ticks simulated
final_tick 1954691371500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
host_inst_rate 798728 # Simulator instruction rate (inst/s)
host_op_rate 798728 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 26318676085 # Simulator tick rate (ticks/s)
host_mem_usage 332420 # Number of bytes of host memory used
host_seconds 74.27 # Real time elapsed on the host
sim_insts 59321614 # Number of instructions simulated
sim_ops 59321614 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 829376 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 24757440 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 34176 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 389696 # Number of bytes read from this memory
system.physmem.bytes_read::total 28661504 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 829376 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 34176 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 863552 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7676992 # Number of bytes written to this memory
system.physmem.bytes_written::total 7676992 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst 12959 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 386835 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 534 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 6089 # Number of read requests responded to by this memory
system.physmem.num_reads::total 447836 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 119953 # Number of write requests responded to by this memory
system.physmem.num_writes::total 119953 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst 424300 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 12665652 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 1356130 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 17484 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 199364 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14662931 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 424300 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 17484 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 441784 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 3927470 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 3927470 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 3927470 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 424300 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 12665652 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1356130 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 17484 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 199364 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 18590401 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 447836 # Total number of read requests seen
system.physmem.writeReqs 119953 # Total number of write requests seen
system.physmem.cpureqs 572898 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 28661504 # Total number of bytes read from memory
system.physmem.bytesWritten 7676992 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 28661504 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 7676992 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 69 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 3161 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 28180 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 28120 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 28097 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 27826 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 27944 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 27900 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 27858 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 27869 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 28342 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 28141 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 28250 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 28016 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 27813 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 27987 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 27674 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 27750 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 7637 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 7504 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 7585 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 7374 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 7488 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 7379 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 7353 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 7437 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 7887 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 7685 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 7821 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 7507 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 7382 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 7492 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 7142 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 7280 # Track writes on a per bank basis
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.numWrRetry 1948 # Number of times wr buffer was full causing retry
system.physmem.totGap 1954684300500 # Total gap between requests
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.readPktSize::6 447836 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 119953 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 407021 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 4814 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 3665 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 2219 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3122 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2946 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2699 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 2701 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 2643 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 2593 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1538 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1461 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1424 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1368 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1347 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 1387 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 1607 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 1512 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 904 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 783 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.wrQLenPdf::0 3709 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 3875 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 4276 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 4328 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 4843 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 5193 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 5199 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 5202 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 5201 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 5215 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 5215 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 5215 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 5215 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 5215 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 5215 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 5215 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 5215 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5215 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5215 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5215 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5215 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5215 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 5215 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 1507 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 1341 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 940 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 888 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 373 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see
system.physmem.totQLat 4783798250 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 13397999500 # Sum of mem lat for all requests
system.physmem.totBusLat 2238835000 # Total cycles spent in databus access
system.physmem.totBankLat 6375366250 # Total cycles spent in bank access
system.physmem.avgQLat 10683.68 # Average queueing delay per request
system.physmem.avgBankLat 14238.13 # Average bank access latency per request
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per request
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.avgMemAccLat 29921.81 # Average memory access latency
system.physmem.avgRdBW 14.66 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 3.93 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 14.66 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 3.93 # Average consumed write bandwidth in MB/s
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.15 # Data bus utilization in percentage
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.avgRdQLen 0.01 # Average read queue length over time
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.avgWrQLen 10.91 # Average write queue length over time
system.physmem.readRowHits 419870 # Number of row buffer hits during reads
system.physmem.writeRowHits 92076 # Number of row buffer hits during writes
system.physmem.readRowHitRate 93.77 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 76.76 # Row buffer hit rate for writes
system.physmem.avgGap 3442624.46 # Average gap between requests
system.l2c.replacements 340771 # number of replacements
system.l2c.tagsinuse 65303.436480 # Cycle average of tags in use
system.l2c.total_refs 2493415 # Total number of references to valid blocks.
system.l2c.sampled_refs 405943 # Sample count of references to valid blocks.
system.l2c.avg_refs 6.142279 # Average number of references to valid blocks.
system.l2c.warmup_cycle 6937754751 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 55559.705668 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst 4839.489270 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data 4775.815267 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 117.980929 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 10.445347 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.847774 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst 0.073845 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.072873 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst 0.001800 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.000159 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.996451 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst 902966 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 773506 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 86370 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 33767 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1796609 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 820435 # number of Writeback hits
system.l2c.Writeback_hits::total 820435 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 163 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 56 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 219 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 21 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 19 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 40 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 171833 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 12858 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 184691 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst 902966 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 945339 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 86370 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 46625 # number of demand (read+write) hits
system.l2c.demand_hits::total 1981300 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 902966 # number of overall hits
system.l2c.overall_hits::cpu0.data 945339 # number of overall hits
system.l2c.overall_hits::cpu1.inst 86370 # number of overall hits
system.l2c.overall_hits::cpu1.data 46625 # number of overall hits
system.l2c.overall_hits::total 1981300 # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst 12959 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 271596 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 545 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 189 # number of ReadReq misses
system.l2c.ReadReq_misses::total 285289 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 2442 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 483 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 2925 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 27 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 73 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 100 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 115623 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 5918 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 121541 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst 12959 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 387219 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 545 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 6107 # number of demand (read+write) misses
system.l2c.demand_misses::total 406830 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst 12959 # number of overall misses
system.l2c.overall_misses::cpu0.data 387219 # number of overall misses
system.l2c.overall_misses::cpu1.inst 545 # number of overall misses
system.l2c.overall_misses::cpu1.data 6107 # number of overall misses
system.l2c.overall_misses::total 406830 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst 800348000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 11682390000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 34833000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 14789000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 12532360000 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 1038000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 229000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 1267000 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 22500 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 115000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 137500 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 5536684000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 338210000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 5874894000 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst 800348000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 17219074000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 34833000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 352999000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 18407254000 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst 800348000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 17219074000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 34833000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 352999000 # number of overall miss cycles
system.l2c.overall_miss_latency::total 18407254000 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst 915925 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 1045102 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 86915 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 33956 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2081898 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 820435 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 820435 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 2605 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 539 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 3144 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 48 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 92 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 140 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 287456 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 18776 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 306232 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst 915925 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 1332558 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 86915 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 52732 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2388130 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 915925 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 1332558 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 86915 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 52732 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2388130 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.014149 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.259875 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.006270 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.005566 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.137033 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.937428 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.896104 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.930344 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.562500 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.793478 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.714286 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.402229 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.315190 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.396892 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst 0.014149 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.290583 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.006270 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.115812 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.170355 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.014149 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.290583 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.006270 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.115812 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.170355 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 61760.012347 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 43013.851456 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 63913.761468 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 78248.677249 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 43928.647792 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 425.061425 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 474.120083 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 433.162393 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 833.333333 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1575.342466 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 1375 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 47885.662887 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 57149.374789 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 48336.725879 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 61760.012347 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 44468.566883 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 63913.761468 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 57802.357950 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 45245.566944 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 61760.012347 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 44468.566883 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 63913.761468 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 57802.357950 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 45245.566944 # average overall miss latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.writebacks::writebacks 78433 # number of writebacks
system.l2c.writebacks::total 78433 # number of writebacks
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_mshr_hits::cpu1.inst 11 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.ReadReq_mshr_misses::cpu0.inst 12959 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 271596 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst 534 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 189 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 285278 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 2442 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 483 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 2925 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 27 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 73 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 100 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 115623 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 5918 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 121541 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 12959 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 387219 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 534 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 6107 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 406819 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 12959 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 387219 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 534 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 6107 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 406819 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 637272201 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 8347679089 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 27561783 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 12429436 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 9024942509 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 24585937 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4830483 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 29416420 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 270027 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 730073 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 1000100 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4108844602 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 263408851 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 4372253453 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 637272201 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 12456523691 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 27561783 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 275838287 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 13397195962 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 637272201 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 12456523691 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 27561783 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 275838287 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 13397195962 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1373082000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 18171000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 1391253000 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1972248000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 500755000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 2473003000 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3345330000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 518926000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 3864256000 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014149 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.259875 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.006144 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.005566 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.137028 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.937428 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.896104 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.930344 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.562500 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.793478 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.714286 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.402229 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.315190 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.396892 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014149 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.290583 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.006144 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.115812 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.170350 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014149 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.290583 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.006144 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.115812 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.170350 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 49176.032178 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 30735.648128 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 51613.825843 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65764.211640 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 31635.606352 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10067.951269 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10056.895726 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 35536.568001 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 44509.775431 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 35973.485927 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 49176.032178 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32169.195445 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 51613.825843 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 45167.559686 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 32931.588648 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 49176.032178 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32169.195445 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 51613.825843 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 45167.559686 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 32931.588648 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.replacements 41694 # number of replacements
system.iocache.tagsinuse 0.572561 # Cycle average of tags in use
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.iocache.total_refs 0 # Total number of references to valid blocks.
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.sampled_refs 41710 # Sample count of references to valid blocks.
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.iocache.avg_refs 0 # Average number of references to valid blocks.
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.warmup_cycle 1746701282000 # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide 0.572561 # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide 0.035785 # Average percentage of cache occupancy
system.iocache.occ_percent::total 0.035785 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses
system.iocache.demand_misses::total 41726 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses
system.iocache.overall_misses::total 41726 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 21042998 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 21042998 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::tsunami.ide 10674900806 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 10674900806 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 10695943804 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 10695943804 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 10695943804 # number of overall miss cycles
system.iocache.overall_miss_latency::total 10695943804 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120936.770115 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 120936.770115 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256904.620861 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 256904.620861 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 256337.626516 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 256337.626516 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 256337.626516 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 256337.626516 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 286340 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.blocked::no_mshrs 27291 # number of cycles access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.avg_blocked_cycles::no_mshrs 10.492104 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.iocache.writebacks::writebacks 41520 # number of writebacks
system.iocache.writebacks::total 41520 # number of writebacks
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11994249 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 11994249 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8512910554 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 8512910554 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 8524904803 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 8524904803 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 8524904803 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 8524904803 # number of overall MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68932.465517 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 68932.465517 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204873.665624 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 204873.665624 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 204306.782414 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 204306.782414 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 204306.782414 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 204306.782414 # average overall mshr miss latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.dtb.read_hits 8631552 # DTB read hits
system.cpu0.dtb.read_misses 7447 # DTB read misses
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu0.dtb.read_acv 210 # DTB read access violations
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.dtb.read_accesses 490676 # DTB read accesses
system.cpu0.dtb.write_hits 6044616 # DTB write hits
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu0.dtb.write_misses 813 # DTB write misses
system.cpu0.dtb.write_acv 134 # DTB write access violations
system.cpu0.dtb.write_accesses 187452 # DTB write accesses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.dtb.data_hits 14676168 # DTB hits
system.cpu0.dtb.data_misses 8260 # DTB misses
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu0.dtb.data_acv 344 # DTB access violations
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.dtb.data_accesses 678128 # DTB accesses
system.cpu0.itb.fetch_hits 3853435 # ITB hits
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu0.itb.fetch_misses 3871 # ITB misses
system.cpu0.itb.fetch_acv 184 # ITB acv
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.itb.fetch_accesses 3857306 # ITB accesses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.write_acv 0 # DTB write access violations
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.data_hits 0 # DTB hits
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.numCycles 3908211536 # number of cpu cycles simulated
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.committedInsts 54061829 # Number of instructions committed
system.cpu0.committedOps 54061829 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 50032862 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 294101 # Number of float alu accesses
system.cpu0.num_func_calls 1426501 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 6236445 # number of instructions that are conditional controls
system.cpu0.num_int_insts 50032862 # number of integer instructions
system.cpu0.num_fp_insts 294101 # number of float instructions
system.cpu0.num_int_register_reads 68513770 # number of times the integer registers were read
system.cpu0.num_int_register_writes 37070851 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 143419 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 146520 # number of times the floating registers were written
system.cpu0.num_mem_refs 14722187 # number of memory refs
system.cpu0.num_load_insts 8662865 # Number of load instructions
system.cpu0.num_store_insts 6059322 # Number of store instructions
system.cpu0.num_idle_cycles 3679287399.643625 # Number of idle cycles
system.cpu0.num_busy_cycles 228924136.356375 # Number of busy cycles
system.cpu0.not_idle_fraction 0.058575 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.941425 # Percentage of idle cycles
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.kern.inst.quiesce 6369 # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei 202997 # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0 72749 40.62% 40.62% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21 131 0.07% 40.70% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22 1975 1.10% 41.80% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30 6 0.00% 41.80% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31 104220 58.20% 100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total 179081 # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0 71382 49.27% 49.27% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22 1975 1.36% 50.73% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31 71376 49.27% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total 144870 # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0 1898301273000 97.14% 97.14% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21 93023500 0.00% 97.15% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22 762236500 0.04% 97.19% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30 5235500 0.00% 97.19% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31 54943969500 2.81% 100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total 1954105738000 # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0 0.981209 # fraction of swpipl calls that actually changed the ipl
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.kern.ipl_used::31 0.684859 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total 0.808964 # fraction of swpipl calls that actually changed the ipl
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed
system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed
system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed
system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed
system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed
system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed
system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed
system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed
system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed
system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed
system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed
system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed
system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed
system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed
system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed
system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed
system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed
system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed
system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed
system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed
system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed
system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed
system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed
system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed
system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed
system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed
system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed
system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed
system.cpu0.kern.syscall::total 222 # number of syscalls executed
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.kern.callpal::wripir 88 0.05% 0.05% # number of callpals executed
system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed
system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed
system.cpu0.kern.callpal::swpctx 3896 2.07% 2.12% # number of callpals executed
system.cpu0.kern.callpal::tbi 51 0.03% 2.15% # number of callpals executed
system.cpu0.kern.callpal::wrent 7 0.00% 2.15% # number of callpals executed
system.cpu0.kern.callpal::swpipl 172217 91.50% 93.65% # number of callpals executed
system.cpu0.kern.callpal::rdps 6678 3.55% 97.19% # number of callpals executed
system.cpu0.kern.callpal::wrkgp 1 0.00% 97.19% # number of callpals executed
system.cpu0.kern.callpal::wrusp 3 0.00% 97.20% # number of callpals executed
system.cpu0.kern.callpal::rdusp 9 0.00% 97.20% # number of callpals executed
system.cpu0.kern.callpal::whami 2 0.00% 97.20% # number of callpals executed
system.cpu0.kern.callpal::rti 4751 2.52% 99.73% # number of callpals executed
system.cpu0.kern.callpal::callsys 381 0.20% 99.93% # number of callpals executed
system.cpu0.kern.callpal::imb 136 0.07% 100.00% # number of callpals executed
system.cpu0.kern.callpal::total 188224 # number of callpals executed
system.cpu0.kern.mode_switch::kernel 7304 # number of protection mode switches
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu0.kern.mode_good::kernel 1283
system.cpu0.kern.mode_good::user 1283
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.kern.mode_good::idle 0
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.kern.mode_switch_good::kernel 0.175657 # fraction of useful protection mode switches
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.kern.mode_switch_good::total 0.298824 # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel 1950347295500 99.82% 99.82% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user 3454635500 0.18% 100.00% # number of ticks spent at the given mode
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.kern.swap_context 3897 # number of times the context was actually changed
Update ref stats. tests/test1/ref/alpha/atomic/stdout: tests/test1/ref/alpha/detailed/stderr: tests/test1/ref/alpha/detailed/stdout: tests/test1/ref/alpha/timing/stdout: Updated output. --HG-- extra : convert_revision : 3189564725ac4d2b3d63e6a71151a52326f8d416
2006-07-27 23:47:43 +02:00
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
Update ref stats. tests/test1/ref/alpha/atomic/stdout: tests/test1/ref/alpha/detailed/stderr: tests/test1/ref/alpha/detailed/stdout: tests/test1/ref/alpha/timing/stdout: Updated output. --HG-- extra : convert_revision : 3189564725ac4d2b3d63e6a71151a52326f8d416
2006-07-27 23:47:43 +02:00
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
Update ref stats. tests/test1/ref/alpha/atomic/stdout: tests/test1/ref/alpha/detailed/stderr: tests/test1/ref/alpha/detailed/stdout: tests/test1/ref/alpha/timing/stdout: Updated output. --HG-- extra : convert_revision : 3189564725ac4d2b3d63e6a71151a52326f8d416
2006-07-27 23:47:43 +02:00
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
Update ref stats. tests/test1/ref/alpha/atomic/stdout: tests/test1/ref/alpha/detailed/stderr: tests/test1/ref/alpha/detailed/stdout: tests/test1/ref/alpha/timing/stdout: Updated output. --HG-- extra : convert_revision : 3189564725ac4d2b3d63e6a71151a52326f8d416
2006-07-27 23:47:43 +02:00
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.icache.replacements 915312 # number of replacements
system.cpu0.icache.tagsinuse 509.170565 # Cycle average of tags in use
system.cpu0.icache.total_refs 53154487 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 915824 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 58.040068 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 32594703000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst 509.170565 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.994474 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.994474 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 53154487 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 53154487 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 53154487 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 53154487 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 53154487 # number of overall hits
system.cpu0.icache.overall_hits::total 53154487 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 915946 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 915946 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 915946 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 915946 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 915946 # number of overall misses
system.cpu0.icache.overall_misses::total 915946 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12645153500 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 12645153500 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 12645153500 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 12645153500 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 12645153500 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 12645153500 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 54070433 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 54070433 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 54070433 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 54070433 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 54070433 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 54070433 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016940 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.016940 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016940 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.016940 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016940 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.016940 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13805.566595 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13805.566595 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13805.566595 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13805.566595 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13805.566595 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13805.566595 # average overall miss latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915946 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 915946 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 915946 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 915946 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 915946 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 915946 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10813261500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 10813261500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10813261500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 10813261500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10813261500 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 10813261500 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016940 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016940 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016940 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.016940 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016940 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.016940 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11805.566595 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11805.566595 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11805.566595 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11805.566595 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11805.566595 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11805.566595 # average overall mshr miss latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.dcache.replacements 1337909 # number of replacements
system.cpu0.dcache.tagsinuse 506.537579 # Cycle average of tags in use
system.cpu0.dcache.total_refs 13346950 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 1338324 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 9.972884 # Average number of references to valid blocks.
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu0.dcache.warmup_cycle 93616000 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.dcache.occ_blocks::cpu0.data 506.537579 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.989331 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.989331 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 7419116 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 7419116 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 5560491 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 5560491 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 176356 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 176356 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191669 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 191669 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 12979607 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 12979607 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 12979607 # number of overall hits
system.cpu0.dcache.overall_hits::total 12979607 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 1035921 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 1035921 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 291041 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 291041 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16710 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 16710 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 430 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 430 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 1326962 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 1326962 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 1326962 # number of overall misses
system.cpu0.dcache.overall_misses::total 1326962 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 22391252000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 22391252000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8190685500 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 8190685500 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 219165000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 219165000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 2509000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 2509000 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 30581937500 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 30581937500 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 30581937500 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 30581937500 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 8455037 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 8455037 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5851532 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 5851532 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 193066 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 193066 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192099 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 192099 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 14306569 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 14306569 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 14306569 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 14306569 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122521 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.122521 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049738 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.049738 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086551 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086551 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002238 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002238 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092752 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.092752 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092752 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.092752 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21614.825841 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 21614.825841 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 28142.720441 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 28142.720441 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13115.798923 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13115.798923 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5834.883721 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5834.883721 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23046.581213 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 23046.581213 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23046.581213 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 23046.581213 # average overall miss latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.dcache.writebacks::writebacks 789805 # number of writebacks
system.cpu0.dcache.writebacks::total 789805 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1035921 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 1035921 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 291041 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 291041 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16710 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16710 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 430 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 430 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 1326962 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 1326962 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 1326962 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 1326962 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 20319410000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 20319410000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7608603500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7608603500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 185745000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 185745000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1649000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1649000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 27928013500 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 27928013500 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 27928013500 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 27928013500 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465455500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465455500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2092162000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2092162000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3557617500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3557617500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122521 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122521 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049738 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049738 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086551 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086551 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002238 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002238 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092752 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.092752 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092752 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.092752 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 19614.825841 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19614.825841 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26142.720441 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26142.720441 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11115.798923 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11115.798923 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3834.883721 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3834.883721 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21046.581213 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21046.581213 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21046.581213 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21046.581213 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.dtb.read_hits 1047086 # DTB read hits
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu1.dtb.read_misses 2992 # DTB read misses
system.cpu1.dtb.read_acv 0 # DTB read access violations
system.cpu1.dtb.read_accesses 239363 # DTB read accesses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.dtb.write_hits 650181 # DTB write hits
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu1.dtb.write_misses 341 # DTB write misses
system.cpu1.dtb.write_acv 29 # DTB write access violations
system.cpu1.dtb.write_accesses 105247 # DTB write accesses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.dtb.data_hits 1697267 # DTB hits
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu1.dtb.data_misses 3333 # DTB misses
system.cpu1.dtb.data_acv 29 # DTB access violations
system.cpu1.dtb.data_accesses 344610 # DTB accesses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.itb.fetch_hits 1487534 # ITB hits
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu1.itb.fetch_misses 1216 # ITB misses
system.cpu1.itb.fetch_acv 0 # ITB acv
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.itb.fetch_accesses 1488750 # ITB accesses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.write_acv 0 # DTB write access violations
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.data_hits 0 # DTB hits
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.numCycles 3909382743 # number of cpu cycles simulated
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.committedInsts 5259785 # Number of instructions committed
system.cpu1.committedOps 5259785 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 4928462 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 34031 # Number of float alu accesses
system.cpu1.num_func_calls 156703 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 508760 # number of instructions that are conditional controls
system.cpu1.num_int_insts 4928462 # number of integer instructions
system.cpu1.num_fp_insts 34031 # number of float instructions
system.cpu1.num_int_register_reads 6858583 # number of times the integer registers were read
system.cpu1.num_int_register_writes 3715950 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 22062 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 21862 # number of times the floating registers were written
system.cpu1.num_mem_refs 1706720 # number of memory refs
system.cpu1.num_load_insts 1053093 # Number of load instructions
system.cpu1.num_store_insts 653627 # Number of store instructions
system.cpu1.num_idle_cycles 3890042761.998010 # Number of idle cycles
system.cpu1.num_busy_cycles 19339981.001990 # Number of busy cycles
system.cpu1.not_idle_fraction 0.004947 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.995053 # Percentage of idle cycles
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.kern.inst.quiesce 2297 # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei 35535 # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0 8961 31.73% 31.73% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22 1969 6.97% 38.70% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30 88 0.31% 39.01% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31 17223 60.99% 100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total 28241 # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0 8951 45.05% 45.05% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22 1969 9.91% 54.95% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30 88 0.44% 55.40% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31 8863 44.60% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total 19871 # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0 1917858613000 98.12% 98.12% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22 705516000 0.04% 98.15% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30 59546500 0.00% 98.15% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31 36066938000 1.85% 100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total 1954690613500 # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0 0.998884 # fraction of swpipl calls that actually changed the ipl
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.kern.ipl_used::31 0.514603 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total 0.703622 # fraction of swpipl calls that actually changed the ipl
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed
system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed
system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed
system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed
system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed
system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed
system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed
system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed
system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed
system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed
system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed
system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed
system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed
system.cpu1.kern.syscall::total 104 # number of syscalls executed
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed
system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed
system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed
system.cpu1.kern.callpal::swpctx 337 1.17% 1.20% # number of callpals executed
system.cpu1.kern.callpal::tbi 3 0.01% 1.21% # number of callpals executed
system.cpu1.kern.callpal::wrent 7 0.02% 1.23% # number of callpals executed
system.cpu1.kern.callpal::swpipl 23653 81.85% 83.08% # number of callpals executed
system.cpu1.kern.callpal::rdps 2170 7.51% 90.59% # number of callpals executed
system.cpu1.kern.callpal::wrkgp 1 0.00% 90.59% # number of callpals executed
system.cpu1.kern.callpal::wrusp 4 0.01% 90.61% # number of callpals executed
system.cpu1.kern.callpal::whami 3 0.01% 90.62% # number of callpals executed
system.cpu1.kern.callpal::rti 2530 8.75% 99.37% # number of callpals executed
system.cpu1.kern.callpal::callsys 136 0.47% 99.84% # number of callpals executed
system.cpu1.kern.callpal::imb 44 0.15% 100.00% # number of callpals executed
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.kern.callpal::total 28898 # number of callpals executed
system.cpu1.kern.mode_switch::kernel 803 # number of protection mode switches
system.cpu1.kern.mode_switch::user 464 # number of protection mode switches
system.cpu1.kern.mode_switch::idle 2065 # number of protection mode switches
system.cpu1.kern.mode_good::kernel 477
system.cpu1.kern.mode_good::user 464
system.cpu1.kern.mode_good::idle 13
system.cpu1.kern.mode_switch_good::kernel 0.594022 # fraction of useful protection mode switches
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.kern.mode_switch_good::idle 0.006295 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total 0.286315 # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel 3558805000 0.18% 0.18% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user 1714794500 0.09% 0.27% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 1949417010500 99.73% 100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context 338 # number of times the context was actually changed
system.cpu1.icache.replacements 86368 # number of replacements
system.cpu1.icache.tagsinuse 420.702382 # Cycle average of tags in use
system.cpu1.icache.total_refs 5176232 # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs 86880 # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs 59.579098 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 1938927920500 # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst 420.702382 # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst 0.821684 # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total 0.821684 # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst 5176232 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 5176232 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 5176232 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 5176232 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 5176232 # number of overall hits
system.cpu1.icache.overall_hits::total 5176232 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 86916 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 86916 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 86916 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 86916 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 86916 # number of overall misses
system.cpu1.icache.overall_misses::total 86916 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1175951500 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 1175951500 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 1175951500 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 1175951500 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 1175951500 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 1175951500 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 5263148 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 5263148 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 5263148 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 5263148 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 5263148 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 5263148 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016514 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.016514 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016514 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.016514 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016514 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.016514 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13529.747112 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13529.747112 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13529.747112 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13529.747112 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13529.747112 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13529.747112 # average overall miss latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 86916 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 86916 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 86916 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 86916 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 86916 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 86916 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1002119500 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 1002119500 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1002119500 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 1002119500 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1002119500 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 1002119500 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016514 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016514 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016514 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.016514 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016514 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.016514 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11529.747112 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11529.747112 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11529.747112 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11529.747112 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11529.747112 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11529.747112 # average overall mshr miss latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.dcache.replacements 52807 # number of replacements
system.cpu1.dcache.tagsinuse 417.673106 # Cycle average of tags in use
system.cpu1.dcache.total_refs 1641018 # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs 53319 # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs 30.777359 # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 1938580812000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data 417.673106 # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data 0.815768 # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total 0.815768 # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data 1001238 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 1001238 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 616220 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 616220 # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 10806 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 10806 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 11203 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 11203 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 1617458 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 1617458 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 1617458 # number of overall hits
system.cpu1.dcache.overall_hits::total 1617458 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 37008 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 37008 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 20401 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 20401 # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 956 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 956 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 500 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 500 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 57409 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 57409 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 57409 # number of overall misses
system.cpu1.dcache.overall_misses::total 57409 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 463706500 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 463706500 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 540901000 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 540901000 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 10601500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 10601500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3694000 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 3694000 # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 1004607500 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 1004607500 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 1004607500 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 1004607500 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 1038246 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 1038246 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 636621 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 636621 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 11762 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 11762 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 11703 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 11703 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 1674867 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 1674867 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 1674867 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 1674867 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035645 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.035645 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032046 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.032046 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.081279 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.081279 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.042724 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.042724 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034277 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.034277 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034277 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.034277 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12529.898941 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 12529.898941 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26513.455223 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 26513.455223 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11089.435146 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11089.435146 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7388 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7388 # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17499.129056 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 17499.129056 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17499.129056 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 17499.129056 # average overall miss latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.dcache.writebacks::writebacks 30630 # number of writebacks
system.cpu1.dcache.writebacks::total 30630 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 37008 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 37008 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 20401 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 20401 # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 956 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 956 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 500 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 500 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 57409 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 57409 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 57409 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 57409 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 389690500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 389690500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 500099000 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 500099000 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8689500 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 8689500 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 2694000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 2694000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 889789500 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 889789500 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 889789500 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 889789500 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19380000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19380000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 529600000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 529600000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 548980000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 548980000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035645 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035645 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032046 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032046 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.081279 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.081279 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.042724 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.042724 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034277 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.034277 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034277 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.034277 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10529.898941 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10529.898941 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24513.455223 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24513.455223 # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9089.435146 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9089.435146 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5388 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5388 # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15499.129056 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15499.129056 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15499.129056 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15499.129056 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
Update ref stats. tests/test1/ref/alpha/atomic/stdout: tests/test1/ref/alpha/detailed/stderr: tests/test1/ref/alpha/detailed/stdout: tests/test1/ref/alpha/timing/stdout: Updated output. --HG-- extra : convert_revision : 3189564725ac4d2b3d63e6a71151a52326f8d416
2006-07-27 23:47:43 +02:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink