2006-01-31 18:12:49 +01:00
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/*
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2012-05-30 11:30:24 +02:00
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* Copyright (c) 2011-2012 ARM Limited
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2012-01-17 19:55:09 +01:00
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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2006-01-31 18:12:49 +01:00
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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2006-06-01 01:26:56 +02:00
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*
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* Authors: Ron Dreslinski
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2006-06-18 00:40:40 +02:00
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* Ali Saidi
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2012-01-17 19:55:09 +01:00
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* Andreas Hansson
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MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
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* William Wang
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2006-01-31 18:12:49 +01:00
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*/
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/**
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2006-08-15 01:25:07 +02:00
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* @file
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Bus: Split the bus into a non-coherent and coherent bus
This patch introduces a class hierarchy of buses, a non-coherent one,
and a coherent one, splitting the existing bus functionality. By doing
so it also enables further specialisation of the two types of buses.
A non-coherent bus connects a number of non-snooping masters and
slaves, and routes the request and response packets based on the
address. The request packets issued by the master connected to a
non-coherent bus could still snoop in caches attached to a coherent
bus, as is the case with the I/O bus and memory bus in most system
configurations. No snoops will, however, reach any master on the
non-coherent bus itself. The non-coherent bus can be used as a
template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses,
and is typically used for the I/O buses.
A coherent bus connects a number of (potentially) snooping masters and
slaves, and routes the request and response packets based on the
address, and also forwards all requests to the snoopers and deals with
the snoop responses. The coherent bus can be used as a template for
modelling QPI, HyperTransport, ACE and coherent OCP buses, and is
typically used for the L1-to-L2 buses and as the main system
interconnect.
The configuration scripts are updated to use a NoncoherentBus for all
peripheral and I/O buses.
A bit of minor tidying up has also been done.
--HG--
rename : src/mem/bus.cc => src/mem/coherent_bus.cc
rename : src/mem/bus.hh => src/mem/coherent_bus.hh
rename : src/mem/bus.cc => src/mem/noncoherent_bus.cc
rename : src/mem/bus.hh => src/mem/noncoherent_bus.hh
2012-05-31 19:30:04 +02:00
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* Declaration of an abstract bus base class.
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2006-01-31 18:12:49 +01:00
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*/
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#ifndef __MEM_BUS_HH__
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#define __MEM_BUS_HH__
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#include <list>
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2011-04-15 19:44:06 +02:00
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#include <set>
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2006-01-31 18:12:49 +01:00
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2009-05-17 23:34:52 +02:00
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#include "base/range.hh"
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2006-12-15 07:49:41 +01:00
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#include "base/range_map.hh"
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2009-05-17 23:34:51 +02:00
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#include "base/types.hh"
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2006-01-31 18:12:49 +01:00
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#include "mem/mem_object.hh"
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Bus: Split the bus into a non-coherent and coherent bus
This patch introduces a class hierarchy of buses, a non-coherent one,
and a coherent one, splitting the existing bus functionality. By doing
so it also enables further specialisation of the two types of buses.
A non-coherent bus connects a number of non-snooping masters and
slaves, and routes the request and response packets based on the
address. The request packets issued by the master connected to a
non-coherent bus could still snoop in caches attached to a coherent
bus, as is the case with the I/O bus and memory bus in most system
configurations. No snoops will, however, reach any master on the
non-coherent bus itself. The non-coherent bus can be used as a
template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses,
and is typically used for the I/O buses.
A coherent bus connects a number of (potentially) snooping masters and
slaves, and routes the request and response packets based on the
address, and also forwards all requests to the snoopers and deals with
the snoop responses. The coherent bus can be used as a template for
modelling QPI, HyperTransport, ACE and coherent OCP buses, and is
typically used for the L1-to-L2 buses and as the main system
interconnect.
The configuration scripts are updated to use a NoncoherentBus for all
peripheral and I/O buses.
A bit of minor tidying up has also been done.
--HG--
rename : src/mem/bus.cc => src/mem/coherent_bus.cc
rename : src/mem/bus.hh => src/mem/coherent_bus.hh
rename : src/mem/bus.cc => src/mem/noncoherent_bus.cc
rename : src/mem/bus.hh => src/mem/noncoherent_bus.hh
2012-05-31 19:30:04 +02:00
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#include "params/BaseBus.hh"
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2006-01-31 18:12:49 +01:00
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Bus: Split the bus into a non-coherent and coherent bus
This patch introduces a class hierarchy of buses, a non-coherent one,
and a coherent one, splitting the existing bus functionality. By doing
so it also enables further specialisation of the two types of buses.
A non-coherent bus connects a number of non-snooping masters and
slaves, and routes the request and response packets based on the
address. The request packets issued by the master connected to a
non-coherent bus could still snoop in caches attached to a coherent
bus, as is the case with the I/O bus and memory bus in most system
configurations. No snoops will, however, reach any master on the
non-coherent bus itself. The non-coherent bus can be used as a
template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses,
and is typically used for the I/O buses.
A coherent bus connects a number of (potentially) snooping masters and
slaves, and routes the request and response packets based on the
address, and also forwards all requests to the snoopers and deals with
the snoop responses. The coherent bus can be used as a template for
modelling QPI, HyperTransport, ACE and coherent OCP buses, and is
typically used for the L1-to-L2 buses and as the main system
interconnect.
The configuration scripts are updated to use a NoncoherentBus for all
peripheral and I/O buses.
A bit of minor tidying up has also been done.
--HG--
rename : src/mem/bus.cc => src/mem/coherent_bus.cc
rename : src/mem/bus.hh => src/mem/coherent_bus.hh
rename : src/mem/bus.cc => src/mem/noncoherent_bus.cc
rename : src/mem/bus.hh => src/mem/noncoherent_bus.hh
2012-05-31 19:30:04 +02:00
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/**
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* The base bus contains the common elements of the non-coherent and
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* coherent bus. It is an abstract class that does not have any of the
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* functionality relating to the actual reception and transmission of
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* packets, as this is left for the subclasses.
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*
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* The BaseBus is responsible for the basic flow control (busy or
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* not), the administration of retries, and the address decoding.
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*/
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class BaseBus : public MemObject
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2006-01-31 18:12:49 +01:00
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{
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2012-05-30 11:29:42 +02:00
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|
Bus: Split the bus into a non-coherent and coherent bus
This patch introduces a class hierarchy of buses, a non-coherent one,
and a coherent one, splitting the existing bus functionality. By doing
so it also enables further specialisation of the two types of buses.
A non-coherent bus connects a number of non-snooping masters and
slaves, and routes the request and response packets based on the
address. The request packets issued by the master connected to a
non-coherent bus could still snoop in caches attached to a coherent
bus, as is the case with the I/O bus and memory bus in most system
configurations. No snoops will, however, reach any master on the
non-coherent bus itself. The non-coherent bus can be used as a
template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses,
and is typically used for the I/O buses.
A coherent bus connects a number of (potentially) snooping masters and
slaves, and routes the request and response packets based on the
address, and also forwards all requests to the snoopers and deals with
the snoop responses. The coherent bus can be used as a template for
modelling QPI, HyperTransport, ACE and coherent OCP buses, and is
typically used for the L1-to-L2 buses and as the main system
interconnect.
The configuration scripts are updated to use a NoncoherentBus for all
peripheral and I/O buses.
A bit of minor tidying up has also been done.
--HG--
rename : src/mem/bus.cc => src/mem/coherent_bus.cc
rename : src/mem/bus.hh => src/mem/coherent_bus.hh
rename : src/mem/bus.cc => src/mem/noncoherent_bus.cc
rename : src/mem/bus.hh => src/mem/noncoherent_bus.hh
2012-05-31 19:30:04 +02:00
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protected:
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2006-01-31 18:12:49 +01:00
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2007-05-22 08:36:09 +02:00
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/** the clock speed for the bus */
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int clock;
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2008-02-26 08:20:08 +01:00
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/** cycles of overhead per transaction */
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int headerCycles;
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2007-05-22 08:36:09 +02:00
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/** the width of the bus in bytes */
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int width;
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/** the next tick at which the bus will be idle */
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Tick tickNextIdle;
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Event * drainEvent;
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2012-07-09 18:35:34 +02:00
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typedef range_map<Addr, PortID>::iterator PortMapIter;
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typedef range_map<Addr, PortID>::const_iterator PortMapConstIter;
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2012-05-30 11:29:42 +02:00
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range_map<Addr, PortID> portMap;
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2007-05-22 08:36:09 +02:00
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AddrRangeList defaultRange;
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MEM: Separate snoops and normal memory requests/responses
This patch introduces port access methods that separates snoop
request/responses from normal memory request/responses. The
differentiation is made for functional, atomic and timing accesses and
builds on the introduction of master and slave ports.
Before the introduction of this patch, the packets belonging to the
different phases of the protocol (request -> [forwarded snoop request
-> snoop response]* -> response) all use the same port access
functions, even though the snoop packets flow in the opposite
direction to the normal packet. That is, a coherent master sends
normal request and receives responses, but receives snoop requests and
sends snoop responses (vice versa for the slave). These two distinct
phases now use different access functions, as described below.
Starting with the functional access, a master sends a request to a
slave through sendFunctional, and the request packet is turned into a
response before the call returns. In a system without cache coherence,
this is all that is needed from the functional interface. For the
cache-coherent scenario, a slave also sends snoop requests to coherent
masters through sendFunctionalSnoop, with responses returned within
the same packet pointer. This is currently used by the bus and caches,
and the LSQ of the O3 CPU. The send/recvFunctional and
send/recvFunctionalSnoop are moved from the Port super class to the
appropriate subclass.
Atomic accesses follow the same flow as functional accesses, with
request being sent from master to slave through sendAtomic. In the
case of cache-coherent ports, a slave can send snoop requests to a
master through sendAtomicSnoop. Just as for the functional access
methods, the atomic send and receive member functions are moved to the
appropriate subclasses.
The timing access methods are different from the functional and atomic
in that requests and responses are separated in time and
send/recvTiming are used for both directions. Hence, a master uses
sendTiming to send a request to a slave, and a slave uses sendTiming
to send a response back to a master, at a later point in time. Snoop
requests and responses travel in the opposite direction, similar to
what happens in functional and atomic accesses. With the introduction
of this patch, it is possible to determine the direction of packets in
the bus, and no longer necessary to look for both a master and a slave
port with the requested port id.
In contrast to the normal recvFunctional, recvAtomic and recvTiming
that are pure virtual functions, the recvFunctionalSnoop,
recvAtomicSnoop and recvTimingSnoop have a default implementation that
calls panic. This is to allow non-coherent master and slave ports to
not implement these functions.
2012-04-14 11:45:07 +02:00
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/**
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* Determine if the bus is to be considered occupied when being
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* presented with a packet from a specific port. If so, the port
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* in question is also added to the retry list.
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*
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* @param port Source port on the bus presenting the packet
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*
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* @return True if the bus is to be considered occupied
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*/
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2012-05-30 11:31:11 +02:00
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bool isOccupied(Port* port);
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MEM: Separate snoops and normal memory requests/responses
This patch introduces port access methods that separates snoop
request/responses from normal memory request/responses. The
differentiation is made for functional, atomic and timing accesses and
builds on the introduction of master and slave ports.
Before the introduction of this patch, the packets belonging to the
different phases of the protocol (request -> [forwarded snoop request
-> snoop response]* -> response) all use the same port access
functions, even though the snoop packets flow in the opposite
direction to the normal packet. That is, a coherent master sends
normal request and receives responses, but receives snoop requests and
sends snoop responses (vice versa for the slave). These two distinct
phases now use different access functions, as described below.
Starting with the functional access, a master sends a request to a
slave through sendFunctional, and the request packet is turned into a
response before the call returns. In a system without cache coherence,
this is all that is needed from the functional interface. For the
cache-coherent scenario, a slave also sends snoop requests to coherent
masters through sendFunctionalSnoop, with responses returned within
the same packet pointer. This is currently used by the bus and caches,
and the LSQ of the O3 CPU. The send/recvFunctional and
send/recvFunctionalSnoop are moved from the Port super class to the
appropriate subclass.
Atomic accesses follow the same flow as functional accesses, with
request being sent from master to slave through sendAtomic. In the
case of cache-coherent ports, a slave can send snoop requests to a
master through sendAtomicSnoop. Just as for the functional access
methods, the atomic send and receive member functions are moved to the
appropriate subclasses.
The timing access methods are different from the functional and atomic
in that requests and responses are separated in time and
send/recvTiming are used for both directions. Hence, a master uses
sendTiming to send a request to a slave, and a slave uses sendTiming
to send a response back to a master, at a later point in time. Snoop
requests and responses travel in the opposite direction, similar to
what happens in functional and atomic accesses. With the introduction
of this patch, it is possible to determine the direction of packets in
the bus, and no longer necessary to look for both a master and a slave
port with the requested port id.
In contrast to the normal recvFunctional, recvAtomic and recvTiming
that are pure virtual functions, the recvFunctionalSnoop,
recvAtomicSnoop and recvTimingSnoop have a default implementation that
calls panic. This is to allow non-coherent master and slave ports to
not implement these functions.
2012-04-14 11:45:07 +02:00
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/**
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* Deal with a destination port accepting a packet by potentially
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* removing the source port from the retry list (if retrying) and
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* occupying the bus accordingly.
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*
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* @param busy_time Time to spend as a result of a successful send
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*/
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void succeededTiming(Tick busy_time);
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2007-05-22 08:36:09 +02:00
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/** Timing function called by port when it is once again able to process
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* requests. */
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2012-05-30 11:30:24 +02:00
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void recvRetry();
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2007-05-22 08:36:09 +02:00
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2012-05-30 11:30:24 +02:00
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/**
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* Function called by the port when the bus is recieving a range change.
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*
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* @param master_port_id id of the port that received the change
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*/
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void recvRangeChange(PortID master_port_id);
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2007-05-22 08:36:09 +02:00
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/** Find which port connected to this bus (if any) should be given a packet
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* with this address.
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* @param addr Address to find port for.
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2007-07-16 05:09:03 +02:00
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* @return id of port that the packet should be sent out of.
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2007-05-22 08:36:09 +02:00
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*/
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2012-05-30 11:29:42 +02:00
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PortID findPort(Addr addr);
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2007-05-22 08:36:09 +02:00
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2007-08-04 22:05:55 +02:00
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// Cache for the findPort function storing recently used ports from portMap
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struct PortCache {
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bool valid;
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2012-05-30 11:29:42 +02:00
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PortID id;
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2007-08-04 22:05:55 +02:00
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Addr start;
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Addr end;
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};
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PortCache portCache[3];
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// Checks the cache and returns the id of the port that has the requested
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// address within its range
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2012-05-30 11:29:42 +02:00
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inline PortID checkPortCache(Addr addr) {
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2007-08-08 20:54:02 +02:00
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if (portCache[0].valid && addr >= portCache[0].start &&
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addr < portCache[0].end) {
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return portCache[0].id;
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}
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if (portCache[1].valid && addr >= portCache[1].start &&
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addr < portCache[1].end) {
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return portCache[1].id;
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}
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if (portCache[2].valid && addr >= portCache[2].start &&
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addr < portCache[2].end) {
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return portCache[2].id;
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2007-08-04 22:05:55 +02:00
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}
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2012-05-30 11:29:42 +02:00
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return InvalidPortID;
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2007-08-04 22:05:55 +02:00
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}
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// Clears the earliest entry of the cache and inserts a new port entry
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inline void updatePortCache(short id, Addr start, Addr end) {
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portCache[2].valid = portCache[1].valid;
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portCache[2].id = portCache[1].id;
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portCache[2].start = portCache[1].start;
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portCache[2].end = portCache[1].end;
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portCache[1].valid = portCache[0].valid;
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portCache[1].id = portCache[0].id;
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portCache[1].start = portCache[0].start;
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portCache[1].end = portCache[0].end;
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portCache[0].valid = true;
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portCache[0].id = id;
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portCache[0].start = start;
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portCache[0].end = end;
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}
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// Clears the cache. Needs to be called in constructor.
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|
|
|
inline void clearPortCache() {
|
|
|
|
portCache[2].valid = false;
|
|
|
|
portCache[1].valid = false;
|
|
|
|
portCache[0].valid = false;
|
|
|
|
}
|
|
|
|
|
2012-01-17 19:55:09 +01:00
|
|
|
/**
|
2012-05-30 11:30:24 +02:00
|
|
|
* Return the address ranges the bus is responsible for.
|
2012-01-17 19:55:09 +01:00
|
|
|
*
|
|
|
|
* @return a list of non-overlapping address ranges
|
|
|
|
*/
|
2012-07-09 18:35:34 +02:00
|
|
|
AddrRangeList getAddrRanges() const;
|
2012-01-17 19:55:09 +01:00
|
|
|
|
2008-03-17 08:07:38 +01:00
|
|
|
/** Calculate the timing parameters for the packet. Updates the
|
|
|
|
* firstWordTime and finishTime fields of the packet object.
|
|
|
|
* Returns the tick at which the packet header is completed (which
|
|
|
|
* will be all that is sent if the target rejects the packet).
|
2008-02-26 08:20:08 +01:00
|
|
|
*/
|
2008-03-17 08:07:38 +01:00
|
|
|
Tick calcPacketTiming(PacketPtr pkt);
|
2008-02-26 08:20:08 +01:00
|
|
|
|
|
|
|
/** Occupy the bus until until */
|
|
|
|
void occupyBus(Tick until);
|
2007-05-22 08:36:09 +02:00
|
|
|
|
2012-03-22 11:37:21 +01:00
|
|
|
/**
|
|
|
|
* Release the bus after being occupied and return to an idle
|
|
|
|
* state where we proceed to send a retry to any potential waiting
|
|
|
|
* port, or drain if asked to do so.
|
|
|
|
*/
|
|
|
|
void releaseBus();
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Send a retry to the port at the head of the retryList. The
|
|
|
|
* caller must ensure that the list is not empty.
|
|
|
|
*/
|
|
|
|
void retryWaiting();
|
|
|
|
|
2012-05-30 11:30:24 +02:00
|
|
|
/**
|
|
|
|
* Ask everyone on the bus what their size is
|
|
|
|
*
|
2007-05-22 08:36:09 +02:00
|
|
|
* @return the max of all the sizes
|
|
|
|
*/
|
2012-05-30 11:30:24 +02:00
|
|
|
unsigned findBlockSize();
|
2007-05-22 08:36:09 +02:00
|
|
|
|
2012-03-22 11:37:21 +01:00
|
|
|
// event used to schedule a release of the bus
|
Bus: Split the bus into a non-coherent and coherent bus
This patch introduces a class hierarchy of buses, a non-coherent one,
and a coherent one, splitting the existing bus functionality. By doing
so it also enables further specialisation of the two types of buses.
A non-coherent bus connects a number of non-snooping masters and
slaves, and routes the request and response packets based on the
address. The request packets issued by the master connected to a
non-coherent bus could still snoop in caches attached to a coherent
bus, as is the case with the I/O bus and memory bus in most system
configurations. No snoops will, however, reach any master on the
non-coherent bus itself. The non-coherent bus can be used as a
template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses,
and is typically used for the I/O buses.
A coherent bus connects a number of (potentially) snooping masters and
slaves, and routes the request and response packets based on the
address, and also forwards all requests to the snoopers and deals with
the snoop responses. The coherent bus can be used as a template for
modelling QPI, HyperTransport, ACE and coherent OCP buses, and is
typically used for the L1-to-L2 buses and as the main system
interconnect.
The configuration scripts are updated to use a NoncoherentBus for all
peripheral and I/O buses.
A bit of minor tidying up has also been done.
--HG--
rename : src/mem/bus.cc => src/mem/coherent_bus.cc
rename : src/mem/bus.hh => src/mem/coherent_bus.hh
rename : src/mem/bus.cc => src/mem/noncoherent_bus.cc
rename : src/mem/bus.hh => src/mem/noncoherent_bus.hh
2012-05-31 19:30:04 +02:00
|
|
|
EventWrapper<BaseBus, &BaseBus::releaseBus> busIdleEvent;
|
2006-10-08 20:08:58 +02:00
|
|
|
|
2006-10-10 23:24:03 +02:00
|
|
|
bool inRetry;
|
2012-05-30 11:29:42 +02:00
|
|
|
std::set<PortID> inRecvRangeChange;
|
2006-10-08 20:08:58 +02:00
|
|
|
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
/** The master and slave ports of the bus */
|
2012-04-25 16:45:23 +02:00
|
|
|
std::vector<SlavePort*> slavePorts;
|
|
|
|
std::vector<MasterPort*> masterPorts;
|
|
|
|
|
Bus: Split the bus into a non-coherent and coherent bus
This patch introduces a class hierarchy of buses, a non-coherent one,
and a coherent one, splitting the existing bus functionality. By doing
so it also enables further specialisation of the two types of buses.
A non-coherent bus connects a number of non-snooping masters and
slaves, and routes the request and response packets based on the
address. The request packets issued by the master connected to a
non-coherent bus could still snoop in caches attached to a coherent
bus, as is the case with the I/O bus and memory bus in most system
configurations. No snoops will, however, reach any master on the
non-coherent bus itself. The non-coherent bus can be used as a
template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses,
and is typically used for the I/O buses.
A coherent bus connects a number of (potentially) snooping masters and
slaves, and routes the request and response packets based on the
address, and also forwards all requests to the snoopers and deals with
the snoop responses. The coherent bus can be used as a template for
modelling QPI, HyperTransport, ACE and coherent OCP buses, and is
typically used for the L1-to-L2 buses and as the main system
interconnect.
The configuration scripts are updated to use a NoncoherentBus for all
peripheral and I/O buses.
A bit of minor tidying up has also been done.
--HG--
rename : src/mem/bus.cc => src/mem/coherent_bus.cc
rename : src/mem/bus.hh => src/mem/coherent_bus.hh
rename : src/mem/bus.cc => src/mem/noncoherent_bus.cc
rename : src/mem/bus.hh => src/mem/noncoherent_bus.hh
2012-05-31 19:30:04 +02:00
|
|
|
/** Convenience typedefs. */
|
2012-04-25 16:45:23 +02:00
|
|
|
typedef std::vector<SlavePort*>::iterator SlavePortIter;
|
Bus: Split the bus into a non-coherent and coherent bus
This patch introduces a class hierarchy of buses, a non-coherent one,
and a coherent one, splitting the existing bus functionality. By doing
so it also enables further specialisation of the two types of buses.
A non-coherent bus connects a number of non-snooping masters and
slaves, and routes the request and response packets based on the
address. The request packets issued by the master connected to a
non-coherent bus could still snoop in caches attached to a coherent
bus, as is the case with the I/O bus and memory bus in most system
configurations. No snoops will, however, reach any master on the
non-coherent bus itself. The non-coherent bus can be used as a
template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses,
and is typically used for the I/O buses.
A coherent bus connects a number of (potentially) snooping masters and
slaves, and routes the request and response packets based on the
address, and also forwards all requests to the snoopers and deals with
the snoop responses. The coherent bus can be used as a template for
modelling QPI, HyperTransport, ACE and coherent OCP buses, and is
typically used for the L1-to-L2 buses and as the main system
interconnect.
The configuration scripts are updated to use a NoncoherentBus for all
peripheral and I/O buses.
A bit of minor tidying up has also been done.
--HG--
rename : src/mem/bus.cc => src/mem/coherent_bus.cc
rename : src/mem/bus.hh => src/mem/coherent_bus.hh
rename : src/mem/bus.cc => src/mem/noncoherent_bus.cc
rename : src/mem/bus.hh => src/mem/noncoherent_bus.hh
2012-05-31 19:30:04 +02:00
|
|
|
typedef std::vector<MasterPort*>::iterator MasterPortIter;
|
2012-04-25 16:45:23 +02:00
|
|
|
typedef std::vector<SlavePort*>::const_iterator SlavePortConstIter;
|
Bus: Split the bus into a non-coherent and coherent bus
This patch introduces a class hierarchy of buses, a non-coherent one,
and a coherent one, splitting the existing bus functionality. By doing
so it also enables further specialisation of the two types of buses.
A non-coherent bus connects a number of non-snooping masters and
slaves, and routes the request and response packets based on the
address. The request packets issued by the master connected to a
non-coherent bus could still snoop in caches attached to a coherent
bus, as is the case with the I/O bus and memory bus in most system
configurations. No snoops will, however, reach any master on the
non-coherent bus itself. The non-coherent bus can be used as a
template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses,
and is typically used for the I/O buses.
A coherent bus connects a number of (potentially) snooping masters and
slaves, and routes the request and response packets based on the
address, and also forwards all requests to the snoopers and deals with
the snoop responses. The coherent bus can be used as a template for
modelling QPI, HyperTransport, ACE and coherent OCP buses, and is
typically used for the L1-to-L2 buses and as the main system
interconnect.
The configuration scripts are updated to use a NoncoherentBus for all
peripheral and I/O buses.
A bit of minor tidying up has also been done.
--HG--
rename : src/mem/bus.cc => src/mem/coherent_bus.cc
rename : src/mem/bus.hh => src/mem/coherent_bus.hh
rename : src/mem/bus.cc => src/mem/noncoherent_bus.cc
rename : src/mem/bus.hh => src/mem/noncoherent_bus.hh
2012-05-31 19:30:04 +02:00
|
|
|
typedef std::vector<MasterPort*>::const_iterator MasterPortConstIter;
|
2006-01-31 18:12:49 +01:00
|
|
|
|
2006-05-31 00:57:42 +02:00
|
|
|
/** An array of pointers to ports that retry should be called on because the
|
|
|
|
* original send failed for whatever reason.*/
|
2012-02-09 19:06:27 +01:00
|
|
|
std::list<Port*> retryList;
|
2006-05-31 00:57:42 +02:00
|
|
|
|
2012-02-09 19:06:27 +01:00
|
|
|
void addToRetryList(Port* port)
|
2006-10-08 20:08:58 +02:00
|
|
|
{
|
2006-10-10 23:24:03 +02:00
|
|
|
if (!inRetry) {
|
2012-02-09 19:06:27 +01:00
|
|
|
// The device wasn't retrying a packet, or wasn't at an
|
|
|
|
// appropriate time.
|
2006-10-08 20:08:58 +02:00
|
|
|
retryList.push_back(port);
|
|
|
|
} else {
|
2012-02-09 19:06:27 +01:00
|
|
|
if (!retryList.empty() && port == retryList.front()) {
|
|
|
|
// The device was retrying a packet. It didn't work,
|
|
|
|
// so we'll leave it at the head of the retry list.
|
2006-10-12 01:25:48 +02:00
|
|
|
inRetry = false;
|
2012-02-09 19:06:27 +01:00
|
|
|
} else {
|
|
|
|
// We are in retry, but not for this port, put it at
|
|
|
|
// the end.
|
2006-10-12 01:25:48 +02:00
|
|
|
retryList.push_back(port);
|
|
|
|
}
|
2006-10-08 20:08:58 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-07-06 20:41:01 +02:00
|
|
|
/** Port that handles requests that don't match any of the interfaces.*/
|
2012-05-30 11:29:42 +02:00
|
|
|
PortID defaultPortID;
|
2006-07-06 20:41:01 +02:00
|
|
|
|
2010-08-17 14:06:21 +02:00
|
|
|
/** If true, use address range provided by default device. Any
|
|
|
|
address not handled by another port and not in default device's
|
|
|
|
range will cause a fatal error. If false, just send all
|
|
|
|
addresses not handled by another port to default device. */
|
|
|
|
bool useDefaultRange;
|
2006-11-02 21:20:37 +01:00
|
|
|
|
2009-06-05 08:21:12 +02:00
|
|
|
unsigned defaultBlockSize;
|
|
|
|
unsigned cachedBlockSize;
|
2007-05-07 20:42:03 +02:00
|
|
|
bool cachedBlockSizeValid;
|
|
|
|
|
Bus: Split the bus into a non-coherent and coherent bus
This patch introduces a class hierarchy of buses, a non-coherent one,
and a coherent one, splitting the existing bus functionality. By doing
so it also enables further specialisation of the two types of buses.
A non-coherent bus connects a number of non-snooping masters and
slaves, and routes the request and response packets based on the
address. The request packets issued by the master connected to a
non-coherent bus could still snoop in caches attached to a coherent
bus, as is the case with the I/O bus and memory bus in most system
configurations. No snoops will, however, reach any master on the
non-coherent bus itself. The non-coherent bus can be used as a
template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses,
and is typically used for the I/O buses.
A coherent bus connects a number of (potentially) snooping masters and
slaves, and routes the request and response packets based on the
address, and also forwards all requests to the snoopers and deals with
the snoop responses. The coherent bus can be used as a template for
modelling QPI, HyperTransport, ACE and coherent OCP buses, and is
typically used for the L1-to-L2 buses and as the main system
interconnect.
The configuration scripts are updated to use a NoncoherentBus for all
peripheral and I/O buses.
A bit of minor tidying up has also been done.
--HG--
rename : src/mem/bus.cc => src/mem/coherent_bus.cc
rename : src/mem/bus.hh => src/mem/coherent_bus.hh
rename : src/mem/bus.cc => src/mem/noncoherent_bus.cc
rename : src/mem/bus.hh => src/mem/noncoherent_bus.hh
2012-05-31 19:30:04 +02:00
|
|
|
BaseBus(const BaseBusParams *p);
|
|
|
|
|
|
|
|
virtual ~BaseBus();
|
|
|
|
|
2006-01-31 18:12:49 +01:00
|
|
|
public:
|
|
|
|
|
|
|
|
/** A function used to return the port associated with this bus object. */
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
virtual MasterPort& getMasterPort(const std::string& if_name, int idx = -1);
|
|
|
|
virtual SlavePort& getSlavePort(const std::string& if_name, int idx = -1);
|
2006-04-28 21:37:48 +02:00
|
|
|
|
2007-06-10 08:01:47 +02:00
|
|
|
virtual void startup();
|
2006-04-28 21:37:48 +02:00
|
|
|
|
2006-11-02 01:00:49 +01:00
|
|
|
unsigned int drain(Event *de);
|
|
|
|
|
2006-01-31 18:12:49 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
#endif //__MEM_BUS_HH__
|