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gem5/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout

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Update ref stats. tests/test1/ref/alpha/atomic/stdout: tests/test1/ref/alpha/detailed/stderr: tests/test1/ref/alpha/detailed/stdout: tests/test1/ref/alpha/timing/stdout: Updated output. --HG-- extra : convert_revision : 3189564725ac4d2b3d63e6a71151a52326f8d416
2006-07-27 23:47:43 +02:00
M5 Simulator System
Bus: Update the stats for the recent bus fix. --HG-- extra : convert_revision : dc29f7b5e6fa30a50305193cb0e5aed942f7e407
2008-02-26 08:20:40 +01:00
Copyright (c) 2001-2008
Update ref stats. tests/test1/ref/alpha/atomic/stdout: tests/test1/ref/alpha/detailed/stderr: tests/test1/ref/alpha/detailed/stdout: tests/test1/ref/alpha/timing/stdout: Updated output. --HG-- extra : convert_revision : 3189564725ac4d2b3d63e6a71151a52326f8d416
2006-07-27 23:47:43 +02:00
The Regents of The University of Michigan
All Rights Reserved
regress: Regression Tester output updates
2011-02-07 07:14:23 +01:00
M5 compiled Feb 6 2011 15:18:06
M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
M5 started Feb 6 2011 20:44:52
M5 executing on SC2B0617
ARM/Alpha/Cpu: Stats change for prefetchs to be more like normal loads.
2010-11-08 20:58:24 +01:00
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
update all the regresstion tests for release --HG-- extra : convert_revision : 47e420b5b27e196a6e7a6424540923623bb3c4d2
2007-05-16 01:25:35 +02:00
Global frequency set at 1000000000000 ticks per second
regress: Regression Tester output updates
2011-02-07 07:14:23 +01:00
info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
Reference updates. Since split cache is gone, a lot of config.ini changes, and minor changes to stats that are likely due to the decoupling of insertions/evictions in the cache.
2008-11-06 17:11:42 +01:00
info: Entering event queue @ 0. Starting simulation...
stats: update stats for previous cset Coherence protocol change basically got rid of UpgradeReqs in L2 caches, other minor related cache stat changes.
2010-09-22 08:07:35 +02:00
info: Launching CPU 1 @ 562628000
Exiting @ tick 1958647095000 because m5_exit instruction encountered
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