2014-10-30 05:50:15 +01:00
---------- Begin Simulation Statistics ----------
2015-12-05 01:11:25 +01:00
sim_seconds 51.811415 # Number of seconds simulated
sim_ticks 51811415265500 # Number of ticks simulated
final_tick 51811415265500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2014-10-30 05:50:15 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2015-12-05 01:11:25 +01:00
host_inst_rate 625298 # Simulator instruction rate (inst/s)
host_op_rate 734839 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 39084409400 # Simulator tick rate (ticks/s)
host_mem_usage 677180 # Number of bytes of host memory used
host_seconds 1325.63 # Real time elapsed on the host
sim_insts 828913449 # Number of instructions simulated
sim_ops 974124045 # Number of ops (including micro ops) simulated
2014-10-30 05:50:15 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2015-12-05 01:11:25 +01:00
system.physmem.bytes_read::cpu.dtb.walker 133696 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 141376 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 4656308 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 65123848 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 401856 # Number of bytes read from this memory
system.physmem.bytes_read::total 70457084 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 4656308 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 4656308 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 61286080 # Number of bytes written to this memory
2014-12-02 12:08:25 +01:00
system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
2015-12-05 01:11:25 +01:00
system.physmem.bytes_written::total 61306660 # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker 2089 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 2209 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 113162 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1017573 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6279 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1141312 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 957595 # Number of write requests responded to by this memory
2014-12-02 12:08:25 +01:00
system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
2015-12-05 01:11:25 +01:00
system.physmem.num_writes::total 960168 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker 2580 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 2729 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 89870 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1256940 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 7756 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1359876 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 89870 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 89870 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1182868 # Write bandwidth from this memory (bytes/s)
2014-12-02 12:08:25 +01:00
system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s)
2015-12-05 01:11:25 +01:00
system.physmem.bw_write::total 1183265 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1182868 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 2580 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 2729 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 89870 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1257337 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 7756 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2543141 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1141312 # Number of read requests accepted
system.physmem.writeReqs 960168 # Number of write requests accepted
system.physmem.readBursts 1141312 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 960168 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 72995200 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 48768 # Total number of bytes read from write queue
system.physmem.bytesWritten 61305216 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 70457084 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 61306660 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 762 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 2248 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 295918 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 70676 # Per bank write bursts
system.physmem.perBankRdBursts::1 76921 # Per bank write bursts
system.physmem.perBankRdBursts::2 71652 # Per bank write bursts
system.physmem.perBankRdBursts::3 67938 # Per bank write bursts
system.physmem.perBankRdBursts::4 64385 # Per bank write bursts
system.physmem.perBankRdBursts::5 70205 # Per bank write bursts
system.physmem.perBankRdBursts::6 66024 # Per bank write bursts
system.physmem.perBankRdBursts::7 63727 # Per bank write bursts
system.physmem.perBankRdBursts::8 65795 # Per bank write bursts
system.physmem.perBankRdBursts::9 109889 # Per bank write bursts
system.physmem.perBankRdBursts::10 68785 # Per bank write bursts
system.physmem.perBankRdBursts::11 70022 # Per bank write bursts
system.physmem.perBankRdBursts::12 67859 # Per bank write bursts
system.physmem.perBankRdBursts::13 71968 # Per bank write bursts
system.physmem.perBankRdBursts::14 68874 # Per bank write bursts
system.physmem.perBankRdBursts::15 65830 # Per bank write bursts
system.physmem.perBankWrBursts::0 58715 # Per bank write bursts
system.physmem.perBankWrBursts::1 63168 # Per bank write bursts
system.physmem.perBankWrBursts::2 61317 # Per bank write bursts
system.physmem.perBankWrBursts::3 60411 # Per bank write bursts
system.physmem.perBankWrBursts::4 56741 # Per bank write bursts
system.physmem.perBankWrBursts::5 60657 # Per bank write bursts
system.physmem.perBankWrBursts::6 57878 # Per bank write bursts
system.physmem.perBankWrBursts::7 57357 # Per bank write bursts
system.physmem.perBankWrBursts::8 58434 # Per bank write bursts
system.physmem.perBankWrBursts::9 60882 # Per bank write bursts
system.physmem.perBankWrBursts::10 59842 # Per bank write bursts
system.physmem.perBankWrBursts::11 61839 # Per bank write bursts
system.physmem.perBankWrBursts::12 59187 # Per bank write bursts
system.physmem.perBankWrBursts::13 62791 # Per bank write bursts
system.physmem.perBankWrBursts::14 60690 # Per bank write bursts
system.physmem.perBankWrBursts::15 57985 # Per bank write bursts
2014-10-30 05:50:15 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
2015-12-05 01:11:25 +01:00
system.physmem.numWrRetry 35 # Number of times write queue was full causing retry
system.physmem.totGap 51811412436500 # Total gap between requests
2014-10-30 05:50:15 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 43101 # Read request sizes (log2)
system.physmem.readPktSize::3 13 # Read request sizes (log2)
system.physmem.readPktSize::4 2 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2015-12-05 01:11:25 +01:00
system.physmem.readPktSize::6 1098196 # Read request sizes (log2)
2014-10-30 05:50:15 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 1 # Write request sizes (log2)
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2015-12-05 01:11:25 +01:00
system.physmem.writePktSize::6 957595 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 1113641 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 21217 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 401 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 327 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 463 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 549 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 543 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1170 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 660 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 297 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 334 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 161 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 148 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 115 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 113 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 105 # What read queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.rdQLenPdf::16 95 # What read queue length does an incoming req see
2015-09-25 13:27:03 +02:00
system.physmem.rdQLenPdf::17 91 # What read queue length does an incoming req see
2015-12-05 01:11:25 +01:00
system.physmem.rdQLenPdf::18 69 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 50 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see
2014-10-30 05:50:15 +01:00
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
2015-12-05 01:11:25 +01:00
system.physmem.wrQLenPdf::15 13676 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 16408 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 54291 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 55219 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 56988 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 56655 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 57800 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 58177 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 59164 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 58681 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 59112 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 63114 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 58508 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 57267 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 57924 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 55949 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 55254 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 54682 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 853 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 691 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 579 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 493 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 420 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 342 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 370 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 312 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 372 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 283 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 357 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 218 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 286 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 296 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 299 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 317 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 183 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 201 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 212 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 178 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 187 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 176 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 150 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 129 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 100 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 112 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 88 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 113 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 451440 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 297.492681 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 171.675079 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 329.019607 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 180783 40.05% 40.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 110069 24.38% 64.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 39371 8.72% 73.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 22726 5.03% 78.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 15993 3.54% 81.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 11772 2.61% 84.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 9986 2.21% 86.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 8783 1.95% 88.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 51957 11.51% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 451440 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 53917 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 21.153458 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 336.779025 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-4095 53915 100.00% 100.00% # Reads before turning the bus around for writes
2015-07-03 16:15:03 +02:00
system.physmem.rdPerTurnAround::20480-24575 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::73728-77823 1 0.00% 100.00% # Reads before turning the bus around for writes
2015-12-05 01:11:25 +01:00
system.physmem.rdPerTurnAround::total 53917 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 53917 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 17.766085 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.131013 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 7.603955 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 51657 95.81% 95.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 251 0.47% 96.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 85 0.16% 96.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 305 0.57% 97.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 61 0.11% 97.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 347 0.64% 97.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 210 0.39% 98.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 16 0.03% 98.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 56 0.10% 98.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 148 0.27% 98.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 29 0.05% 98.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 23 0.04% 98.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 456 0.85% 99.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 29 0.05% 99.55% # Writes before turning the bus around for reads
2015-11-06 09:26:50 +01:00
system.physmem.wrPerTurnAround::72-75 32 0.06% 99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 152 0.28% 99.89% # Writes before turning the bus around for reads
2015-12-05 01:11:25 +01:00
system.physmem.wrPerTurnAround::80-83 7 0.01% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 3 0.01% 99.91% # Writes before turning the bus around for reads
2015-11-06 09:26:50 +01:00
system.physmem.wrPerTurnAround::88-91 2 0.00% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 2 0.00% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 4 0.01% 99.92% # Writes before turning the bus around for reads
2015-12-05 01:11:25 +01:00
system.physmem.wrPerTurnAround::112-115 4 0.01% 99.93% # Writes before turning the bus around for reads
2015-11-06 09:26:50 +01:00
system.physmem.wrPerTurnAround::120-123 1 0.00% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 26 0.05% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 3 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 4 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167 1 0.00% 100.00% # Writes before turning the bus around for reads
2015-12-05 01:11:25 +01:00
system.physmem.wrPerTurnAround::total 53917 # Writes before turning the bus around for reads
system.physmem.totQLat 14358242809 # Total ticks spent queuing
system.physmem.totMemAccLat 35743555309 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 5702750000 # Total ticks spent in databus transfers
system.physmem.avgQLat 12588.88 # Average queueing delay per DRAM burst
2014-10-30 05:50:15 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2015-12-05 01:11:25 +01:00
system.physmem.avgMemAccLat 31338.88 # Average memory access latency per DRAM burst
2015-09-25 13:27:03 +02:00
system.physmem.avgRdBW 1.41 # Average DRAM read bandwidth in MiByte/s
2015-11-06 09:26:50 +01:00
system.physmem.avgWrBW 1.18 # Average achieved write bandwidth in MiByte/s
2015-09-25 13:27:03 +02:00
system.physmem.avgRdBWSys 1.36 # Average system read bandwidth in MiByte/s
2015-11-06 09:26:50 +01:00
system.physmem.avgWrBWSys 1.18 # Average system write bandwidth in MiByte/s
2014-10-30 05:50:15 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2015-07-03 16:15:03 +02:00
system.physmem.busUtil 0.02 # Data bus utilization in percentage
2014-10-30 05:50:15 +01:00
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
2015-07-03 16:15:03 +02:00
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
2014-10-30 05:50:15 +01:00
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
2015-12-05 01:11:25 +01:00
system.physmem.avgWrQLen 25.21 # Average write queue length when enqueuing
system.physmem.readRowHits 919470 # Number of row buffer hits during reads
system.physmem.writeRowHits 727533 # Number of row buffer hits during writes
system.physmem.readRowHitRate 80.62 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 75.95 # Row buffer hit rate for writes
system.physmem.avgGap 24654725.45 # Average gap between requests
system.physmem.pageHitRate 78.49 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 1712392920 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 934341375 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 4301879400 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 3086061120 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3384069614640 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1295992039365 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 29950012638750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 34640108967570 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.580666 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 49823953491004 # Time in different power states
system.physmem_0.memoryStateTime::REF 1730096940000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-12-05 01:11:25 +01:00
system.physmem_0.memoryStateTime::ACT 257364177996 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-12-05 01:11:25 +01:00
system.physmem_1.actEnergy 1700493480 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 927848625 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 4594371600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 3121092000 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3384069614640 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 1294725453480 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 29951123679000 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 34640262552825 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.583630 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 49825763906946 # Time in different power states
system.physmem_1.memoryStateTime::REF 1730096940000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-12-05 01:11:25 +01:00
system.physmem_1.memoryStateTime::ACT 255552101804 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
2014-12-23 15:31:20 +01:00
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2015-12-05 01:11:25 +01:00
system.cpu.dtb.walker.walks 185222 # Table walker walks requested
system.cpu.dtb.walker.walksLong 185222 # Table walker walks initiated with long descriptors
system.cpu.dtb.walker.walksLongTerminationLevel::Level2 12899 # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksLongTerminationLevel::Level3 144060 # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksSquashedBefore 17 # Table walks squashed before starting
system.cpu.dtb.walker.walkWaitTime::samples 185205 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::mean 0.215977 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::stdev 70.785904 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0-2047 185203 100.00% 100.00% # Table walker wait (enqueue to first request) latency
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
2015-09-25 13:27:03 +02:00
system.cpu.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
2015-12-05 01:11:25 +01:00
system.cpu.dtb.walker.walkWaitTime::total 185205 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples 156976 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 24757.998038 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 20851.674753 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 17681.260030 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-65535 155823 99.27% 99.27% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::65536-131071 3 0.00% 99.27% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-196607 1006 0.64% 99.91% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::196608-262143 12 0.01% 99.92% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::262144-327679 72 0.05% 99.96% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::327680-393215 20 0.01% 99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::393216-458751 30 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total 156976 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples 3935879148 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::mean 0.602257 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::stdev 0.489432 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0 1565466704 39.77% 39.77% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::1 2370412444 60.23% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total 3935879148 # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K 144061 91.78% 91.78% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::2M 12899 8.22% 100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total 156960 # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 185222 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2015-12-05 01:11:25 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 185222 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 156960 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2015-12-05 01:11:25 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 156960 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 342182 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
2015-12-05 01:11:25 +01:00
system.cpu.dtb.read_hits 156096920 # DTB read hits
system.cpu.dtb.read_misses 137670 # DTB read misses
system.cpu.dtb.write_hits 141678029 # DTB write hits
system.cpu.dtb.write_misses 47552 # DTB write misses
2014-10-30 05:50:15 +01:00
system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2015-11-06 09:26:50 +01:00
system.cpu.dtb.flush_tlb_mva_asid 37806 # Number of times TLB was flushed by MVA & ASID
2015-09-25 13:27:03 +02:00
system.cpu.dtb.flush_tlb_asid 999 # Number of times TLB was flushed by ASID
2015-12-05 01:11:25 +01:00
system.cpu.dtb.flush_entries 70722 # Number of entries that have been flushed from TLB
2014-10-30 05:50:15 +01:00
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
2015-12-05 01:11:25 +01:00
system.cpu.dtb.prefetch_faults 6709 # Number of TLB faults due to prefetch
2014-10-30 05:50:15 +01:00
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2015-11-06 09:26:50 +01:00
system.cpu.dtb.perms_faults 18565 # Number of TLB faults due to permissions restrictions
2015-12-05 01:11:25 +01:00
system.cpu.dtb.read_accesses 156234590 # DTB read accesses
system.cpu.dtb.write_accesses 141725581 # DTB write accesses
2014-10-30 05:50:15 +01:00
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
2015-12-05 01:11:25 +01:00
system.cpu.dtb.hits 297774949 # DTB hits
system.cpu.dtb.misses 185222 # DTB misses
system.cpu.dtb.accesses 297960171 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2015-12-05 01:11:25 +01:00
system.cpu.itb.walker.walks 118503 # Table walker walks requested
system.cpu.itb.walker.walksLong 118503 # Table walker walks initiated with long descriptors
2015-09-25 13:27:03 +02:00
system.cpu.itb.walker.walksLongTerminationLevel::Level2 1110 # Level at which table walker walks with long descriptors terminate
2015-12-05 01:11:25 +01:00
system.cpu.itb.walker.walksLongTerminationLevel::Level3 107075 # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walkWaitTime::samples 118503 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0 118503 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total 118503 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples 108185 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 28674.682257 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 24804.583165 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 21241.542539 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-65535 106795 98.72% 98.72% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-196607 1213 1.12% 99.84% # Table walker service (enqueue to completion) latency
2015-11-06 09:26:50 +01:00
system.cpu.itb.walker.walkCompletionTime::196608-262143 32 0.03% 99.87% # Table walker service (enqueue to completion) latency
2015-12-05 01:11:25 +01:00
system.cpu.itb.walker.walkCompletionTime::262144-327679 69 0.06% 99.93% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::327680-393215 26 0.02% 99.95% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::393216-458751 33 0.03% 99.98% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::458752-524287 6 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::524288-589823 5 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::589824-655359 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total 108185 # Table walker service (enqueue to completion) latency
2015-11-06 09:26:50 +01:00
system.cpu.itb.walker.walksPending::samples 1449611704 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0 1449611704 100.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total 1449611704 # Table walker pending requests distribution
2015-12-05 01:11:25 +01:00
system.cpu.itb.walker.walkPageSizes::4K 107075 98.97% 98.97% # Table walker page sizes translated
2015-11-06 09:26:50 +01:00
system.cpu.itb.walker.walkPageSizes::2M 1110 1.03% 100.00% # Table walker page sizes translated
2015-12-05 01:11:25 +01:00
system.cpu.itb.walker.walkPageSizes::total 108185 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2015-12-05 01:11:25 +01:00
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 118503 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 118503 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2015-12-05 01:11:25 +01:00
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 108185 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 108185 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 226688 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 829424054 # ITB inst hits
system.cpu.itb.inst_misses 118503 # ITB inst misses
2014-10-30 05:50:15 +01:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2015-11-06 09:26:50 +01:00
system.cpu.itb.flush_tlb_mva_asid 37806 # Number of times TLB was flushed by MVA & ASID
2015-09-25 13:27:03 +02:00
system.cpu.itb.flush_tlb_asid 999 # Number of times TLB was flushed by ASID
2015-11-06 09:26:50 +01:00
system.cpu.itb.flush_entries 50494 # Number of entries that have been flushed from TLB
2014-10-30 05:50:15 +01:00
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
2015-12-05 01:11:25 +01:00
system.cpu.itb.inst_accesses 829542557 # ITB inst accesses
system.cpu.itb.hits 829424054 # DTB hits
system.cpu.itb.misses 118503 # DTB misses
system.cpu.itb.accesses 829542557 # DTB accesses
system.cpu.numCycles 103622830531 # number of cpu cycles simulated
2014-10-30 05:50:15 +01:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2015-10-10 23:45:41 +02:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 15973 # number of quiesce instructions executed
2015-12-05 01:11:25 +01:00
system.cpu.committedInsts 828913449 # Number of instructions committed
system.cpu.committedOps 974124045 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 895594684 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 899411 # Number of float alu accesses
system.cpu.num_func_calls 49818288 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 125653589 # number of instructions that are conditional controls
system.cpu.num_int_insts 895594684 # number of integer instructions
system.cpu.num_fp_insts 899411 # number of float instructions
system.cpu.num_int_register_reads 1295586183 # number of times the integer registers were read
system.cpu.num_int_register_writes 709722189 # number of times the integer registers were written
system.cpu.num_fp_register_reads 1452745 # number of times the floating registers were read
system.cpu.num_fp_register_writes 757584 # number of times the floating registers were written
system.cpu.num_cc_register_reads 214510161 # number of times the CC registers were read
system.cpu.num_cc_register_writes 213901888 # number of times the CC registers were written
system.cpu.num_mem_refs 297752944 # number of memory refs
system.cpu.num_load_insts 156086585 # Number of load instructions
system.cpu.num_store_insts 141666359 # Number of store instructions
system.cpu.num_idle_cycles 100538909625.142059 # Number of idle cycles
system.cpu.num_busy_cycles 3083920905.857941 # Number of busy cycles
system.cpu.not_idle_fraction 0.029761 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.970239 # Percentage of idle cycles
system.cpu.Branches 184946450 # Number of branches fetched
2014-10-30 05:50:15 +01:00
system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
2015-12-05 01:11:25 +01:00
system.cpu.op_class::IntAlu 674595310 69.21% 69.21% # Class of executed instruction
system.cpu.op_class::IntMult 2119774 0.22% 69.43% # Class of executed instruction
system.cpu.op_class::IntDiv 97321 0.01% 69.44% # Class of executed instruction
2015-09-25 13:27:03 +02:00
system.cpu.op_class::FloatAdd 0 0.00% 69.44% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 69.44% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 69.44% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 69.44% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 69.44% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 69.44% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 69.44% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 69.44% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 69.44% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 69.44% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 69.44% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 69.44% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 69.44% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 69.44% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 69.44% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 69.44% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 69.44% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 8 0.00% 69.44% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 69.44% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 13 0.00% 69.44% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 21 0.00% 69.44% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 69.44% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 112382 0.01% 69.45% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 69.45% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.45% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.45% # Class of executed instruction
2015-12-05 01:11:25 +01:00
system.cpu.op_class::MemRead 156086585 16.01% 85.47% # Class of executed instruction
system.cpu.op_class::MemWrite 141666359 14.53% 100.00% # Class of executed instruction
2014-10-30 05:50:15 +01:00
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
2015-12-05 01:11:25 +01:00
system.cpu.op_class::total 974677774 # Class of executed instruction
system.cpu.dcache.tags.replacements 9257096 # number of replacements
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.tagsinuse 511.942792 # Cycle average of tags in use
2015-12-05 01:11:25 +01:00
system.cpu.dcache.tags.total_refs 288320002 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 9257608 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 31.144114 # Average number of references to valid blocks.
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.warmup_cycle 5830299500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.942792 # Average occupied blocks per requestor
2015-09-25 13:27:03 +02:00
system.cpu.dcache.tags.occ_percent::cpu.data 0.999888 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999888 # Average percentage of cache occupancy
2014-12-02 12:08:25 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2015-12-05 01:11:25 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 400 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id
2015-07-03 16:15:03 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
2014-12-02 12:08:25 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2015-12-05 01:11:25 +01:00
system.cpu.dcache.tags.tag_accesses 1200023494 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1200023494 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 146178724 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 146178724 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 134536913 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 134536913 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 373150 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 373150 # number of SoftPFReq hits
system.cpu.dcache.WriteLineReq_hits::cpu.data 333652 # number of WriteLineReq hits
system.cpu.dcache.WriteLineReq_hits::total 333652 # number of WriteLineReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3286715 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 3286715 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 3569347 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 3569347 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 280715637 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 280715637 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 281088787 # number of overall hits
system.cpu.dcache.overall_hits::total 281088787 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 4832437 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 4832437 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1969504 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1969504 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 1107960 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 1107960 # number of SoftPFReq misses
system.cpu.dcache.WriteLineReq_misses::cpu.data 1218811 # number of WriteLineReq misses
system.cpu.dcache.WriteLineReq_misses::total 1218811 # number of WriteLineReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 284252 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 284252 # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data 3 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data 6801941 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 6801941 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 7909901 # number of overall misses
system.cpu.dcache.overall_misses::total 7909901 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 82966383500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 82966383500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 66911897500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 66911897500 # number of WriteReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 73402202000 # number of WriteLineReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::total 73402202000 # number of WriteLineReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4352844000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 4352844000 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 248500 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 248500 # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 149878281000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 149878281000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 149878281000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 149878281000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 151011161 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 151011161 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 136506417 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 136506417 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 1481110 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 1481110 # number of SoftPFReq accesses(hits+misses)
2015-11-06 09:26:50 +01:00
system.cpu.dcache.WriteLineReq_accesses::cpu.data 1552463 # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::total 1552463 # number of WriteLineReq accesses(hits+misses)
2015-12-05 01:11:25 +01:00
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3570967 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 3570967 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3569350 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 3569350 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 287517578 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 287517578 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 288998688 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 288998688 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032001 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.032001 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014428 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.014428 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.748061 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.748061 # miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.785082 # miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::total 0.785082 # miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.079601 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.079601 # miss rate for LoadLockedReq accesses
2015-09-25 13:27:03 +02:00
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses
2015-12-05 01:11:25 +01:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.023657 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.023657 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.027370 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.027370 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17168.642550 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 17168.642550 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33973.984059 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 33973.984059 # average WriteReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 60224.433485 # average WriteLineReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::total 60224.433485 # average WriteLineReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15313.327611 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15313.327611 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82833.333333 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82833.333333 # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22034.634085 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 22034.634085 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 18948.186709 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 18948.186709 # average overall miss latency
2014-12-02 12:08:25 +01:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
2015-12-05 01:11:25 +01:00
system.cpu.dcache.writebacks::writebacks 7253164 # number of writebacks
system.cpu.dcache.writebacks::total 7253164 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 23327 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 23327 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21303 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 21303 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 67434 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 67434 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 44630 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 44630 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 44630 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 44630 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 4809110 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 4809110 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1948201 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1948201 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1106180 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 1106180 # number of SoftPFReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1218811 # number of WriteLineReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::total 1218811 # number of WriteLineReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 216818 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 216818 # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 3 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 6757311 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 6757311 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 7863491 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 7863491 # number of overall MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33702 # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total 33702 # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33708 # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total 33708 # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67410 # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total 67410 # number of overall MSHR uncacheable misses
2015-12-05 01:11:25 +01:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 76783212500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 76783212500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 63978351000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 63978351000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 20966645000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 20966645000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 72183391000 # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 72183391000 # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2984919500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2984919500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 245500 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 245500 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 140761563500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 140761563500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161728208500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 161728208500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6199745000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6199745000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6217608000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6217608000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12417353000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 12417353000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.031846 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031846 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014272 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014272 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.746859 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.746859 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.785082 # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.785082 # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060717 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060717 # mshr miss rate for LoadLockedReq accesses
2015-09-25 13:27:03 +02:00
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
2015-12-05 01:11:25 +01:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.023502 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.023502 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027209 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.027209 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15966.200087 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15966.200087 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32839.707505 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32839.707505 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18954.098790 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18954.098790 # average SoftPFReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 59224.433485 # average WriteLineReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 59224.433485 # average WriteLineReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13766.935863 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13766.935863 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81833.333333 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81833.333333 # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20831.002673 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20831.002673 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20566.973180 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20566.973180 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183957.776987 # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183957.776987 # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184454.966180 # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184454.966180 # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184206.393710 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184206.393710 # average overall mshr uncacheable latency
2014-12-02 12:08:25 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-12-05 01:11:25 +01:00
system.cpu.icache.tags.replacements 13398086 # number of replacements
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.tagsinuse 511.782420 # Cycle average of tags in use
2015-12-05 01:11:25 +01:00
system.cpu.icache.tags.total_refs 816025451 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 13398598 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 60.903794 # Average number of references to valid blocks.
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.warmup_cycle 61704805500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 511.782420 # Average occupied blocks per requestor
2015-09-25 13:27:03 +02:00
system.cpu.icache.tags.occ_percent::cpu.inst 0.999575 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.999575 # Average percentage of cache occupancy
2014-10-30 05:50:15 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id
2015-12-05 01:11:25 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 185 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
2014-10-30 05:50:15 +01:00
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2015-12-05 01:11:25 +01:00
system.cpu.icache.tags.tag_accesses 842822657 # Number of tag accesses
system.cpu.icache.tags.data_accesses 842822657 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 816025451 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 816025451 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 816025451 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 816025451 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 816025451 # number of overall hits
system.cpu.icache.overall_hits::total 816025451 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 13398603 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 13398603 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 13398603 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 13398603 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 13398603 # number of overall misses
system.cpu.icache.overall_misses::total 13398603 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 182979269500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 182979269500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 182979269500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 182979269500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 182979269500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 182979269500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 829424054 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 829424054 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 829424054 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 829424054 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 829424054 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 829424054 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016154 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.016154 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.016154 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.016154 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.016154 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.016154 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13656.593116 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13656.593116 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13656.593116 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13656.593116 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13656.593116 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13656.593116 # average overall miss latency
2014-10-30 05:50:15 +01:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
2015-12-05 01:11:25 +01:00
system.cpu.icache.writebacks::writebacks 13398086 # number of writebacks
system.cpu.icache.writebacks::total 13398086 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13398603 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 13398603 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 13398603 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 13398603 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 13398603 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 13398603 # number of overall MSHR misses
2015-05-05 09:22:39 +02:00
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses
2015-12-05 01:11:25 +01:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 169580666500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 169580666500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 169580666500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 169580666500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 169580666500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 169580666500 # number of overall MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 5436787000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 5436787000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 5436787000 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 5436787000 # number of overall MSHR uncacheable cycles
2015-12-05 01:11:25 +01:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016154 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016154 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016154 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.016154 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016154 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.016154 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12656.593116 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12656.593116 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12656.593116 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12656.593116 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12656.593116 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12656.593116 # average overall mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.423188 # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126070.423188 # average overall mshr uncacheable latency
2014-10-30 05:50:15 +01:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.tags.replacements 1001888 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65194.742933 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 41566827 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 1063831 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 39.072773 # Average number of references to valid blocks.
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.warmup_cycle 56076472500 # Cycle when the warmup percentage was hit.
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.tags.occ_blocks::writebacks 37699.189777 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 214.416551 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 325.189859 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 8460.753962 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 18495.192784 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.575244 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.003272 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.004962 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.129101 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.282214 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.994793 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023 190 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 61753 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 189 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 410 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2436 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5535 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53334 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.002899 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.942276 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 371499011 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 371499011 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 309547 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 241826 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 551373 # number of ReadReq hits
system.cpu.l2cache.WritebackDirty_hits::writebacks 7253164 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 7253164 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 13396481 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 13396481 # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 8798 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 8798 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1589285 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1589285 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 13328529 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 13328529 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5911348 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 5911348 # number of ReadSharedReq hits
system.cpu.l2cache.InvalidateReq_hits::cpu.data 738219 # number of InvalidateReq hits
system.cpu.l2cache.InvalidateReq_hits::total 738219 # number of InvalidateReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 309547 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 241826 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 13328529 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 7500633 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 21380535 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 309547 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 241826 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 13328529 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 7500633 # number of overall hits
system.cpu.l2cache.overall_hits::total 21380535 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2089 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2209 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 4298 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 32700 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 32700 # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 317418 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 317418 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 70074 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 70074 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 220760 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 220760 # number of ReadSharedReq misses
system.cpu.l2cache.InvalidateReq_misses::cpu.data 480592 # number of InvalidateReq misses
system.cpu.l2cache.InvalidateReq_misses::total 480592 # number of InvalidateReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 2089 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 2209 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 70074 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 538178 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 612550 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 2089 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 2209 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 70074 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 538178 # number of overall misses
system.cpu.l2cache.overall_misses::total 612550 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 284038500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 305600500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 589639000 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1356174500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 1356174500 # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 241000 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 241000 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41587725000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 41587725000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 9268798000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 9268798000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 29392491500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 29392491500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 62603868500 # number of InvalidateReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::total 62603868500 # number of InvalidateReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 284038500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 305600500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 9268798000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 70980216500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 80838653500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 284038500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 305600500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 9268798000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 70980216500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 80838653500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 311636 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 244035 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 555671 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::writebacks 7253164 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 7253164 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 13396481 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 13396481 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 41498 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 41498 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 3 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 3 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1906703 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1906703 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 13398603 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 13398603 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6132108 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 6132108 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1218811 # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::total 1218811 # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 311636 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 244035 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 13398603 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 8038811 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 21993085 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 311636 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 244035 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 13398603 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 8038811 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 21993085 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006703 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.009052 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.007735 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.787990 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.787990 # miss rate for UpgradeReq accesses
2014-10-30 05:50:15 +01:00
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.166475 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.166475 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005230 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005230 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.036001 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.036001 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.394312 # miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::total 0.394312 # miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006703 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.009052 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005230 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.066947 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.027852 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006703 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.009052 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005230 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.066947 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.027852 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 135968.645285 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 138343.368040 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 137189.157748 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 41473.226300 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 41473.226300 # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80333.333333 # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80333.333333 # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 131018.798556 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 131018.798556 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132271.570055 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132271.570055 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 133142.288005 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 133142.288005 # average ReadSharedReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 130264.067026 # average InvalidateReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 130264.067026 # average InvalidateReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 135968.645285 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 138343.368040 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132271.570055 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 131889.851499 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 131970.701984 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 135968.645285 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 138343.368040 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132271.570055 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 131889.851499 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 131970.701984 # average overall miss latency
2014-10-30 05:50:15 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.writebacks::writebacks 850965 # number of writebacks
system.cpu.l2cache.writebacks::total 850965 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 2089 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2209 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 4298 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 32700 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 32700 # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 317418 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 317418 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 70074 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 70074 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 220760 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 220760 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 480592 # number of InvalidateReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::total 480592 # number of InvalidateReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 2089 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2209 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 70074 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 538178 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 612550 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 2089 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2209 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 70074 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 538178 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 612550 # number of overall MSHR misses
2015-05-05 09:22:39 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33702 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 76827 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33708 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33708 # number of WriteReq MSHR uncacheable
2015-05-05 09:22:39 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67410 # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 110535 # number of overall MSHR uncacheable misses
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 263148500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 283510500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 546659000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2311356000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2311356000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 211000 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 211000 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38413545000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38413545000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8568058000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8568058000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 27184891500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 27184891500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 57797948500 # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 57797948500 # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 263148500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 283510500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8568058000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 65598436500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 74713153500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 263148500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 283510500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8568058000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 65598436500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 74713153500 # number of overall MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 4897724500 # number of ReadReq MSHR uncacheable cycles
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5777666500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 10675391000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5829955000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5829955000 # number of WriteReq MSHR uncacheable cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 4897724500 # number of overall MSHR uncacheable cycles
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11607621500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 16505346000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006703 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.009052 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.007735 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.787990 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.787990 # mshr miss rate for UpgradeReq accesses
2014-10-30 05:50:15 +01:00
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.166475 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.166475 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005230 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005230 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.036001 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.036001 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.394312 # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.394312 # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006703 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.009052 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005230 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.066947 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.027852 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006703 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.009052 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005230 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.066947 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.027852 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 125968.645285 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 128343.368040 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127189.157748 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70683.669725 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70683.669725 # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70333.333333 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70333.333333 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 121018.798556 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 121018.798556 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122271.570055 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122271.570055 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 123142.288005 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 123142.288005 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 120264.067026 # average InvalidateReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 120264.067026 # average InvalidateReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 125968.645285 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 128343.368040 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122271.570055 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 121889.851499 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 121970.701984 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 125968.645285 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 128343.368040 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122271.570055 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 121889.851499 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 121970.701984 # average overall mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average ReadReq mshr uncacheable latency
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171433.935671 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138953.636091 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172954.639848 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172954.639848 # average WriteReq mshr uncacheable latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average overall mshr uncacheable latency
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172194.355437 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149322.350387 # average overall mshr uncacheable latency
2014-10-30 05:50:15 +01:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.snoop_filter.tot_requests 45828995 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 23172776 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1754 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 2709 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2709 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.trans_dist::ReadReq 972528 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 20504109 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.trans_dist::WriteReq 33708 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 33708 # Transaction distribution
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.trans_dist::WritebackDirty 8210793 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 13396481 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 2163559 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 41501 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 41504 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1906703 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1906703 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 13398603 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 6140983 # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq 1325475 # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateResp 1218811 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40279937 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27990886 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 598158 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 853214 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 69722195 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1715057876 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 978932526 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1952280 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2493088 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 2698435770 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 1573850 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 24936909 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.019271 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.137475 # Request fanout histogram
2014-10-30 05:50:15 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.snoop_fanout::0 24456353 98.07% 98.07% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 480556 1.93% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2014-10-30 05:50:15 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.snoop_fanout::total 24936909 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 43847676000 # Layer occupancy (ticks)
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.snoopLayer0.occupancy 1611389 # Layer occupancy (ticks)
2014-10-30 05:50:15 +01:00
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.respLayer0.occupancy 20141029500 # Layer occupancy (ticks)
2014-10-30 05:50:15 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 12738944468 # Layer occupancy (ticks)
2014-10-30 05:50:15 +01:00
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.respLayer2.occupancy 354123000 # Layer occupancy (ticks)
2014-10-30 05:50:15 +01:00
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.respLayer3.occupancy 541578000 # Layer occupancy (ticks)
2014-10-30 05:50:15 +01:00
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.trans_dist::ReadReq 40323 # Transaction distribution
system.iobus.trans_dist::ReadResp 40323 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231004 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 231004 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count::total 353788 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334448 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7334448 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size::total 7492368 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 42147000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer2.occupancy 321500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer4.occupancy 11500 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer10.occupancy 11000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer16.occupancy 16500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer23.occupancy 25743500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer24.occupancy 38603500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer25.occupancy 565463411 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2015-03-02 11:04:20 +01:00
system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.respLayer3.occupancy 147764000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-07-03 16:15:03 +02:00
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iocache.tags.replacements 115483 # number of replacements
system.iocache.tags.tagsinuse 10.446937 # Cycle average of tags in use
2014-10-30 05:50:15 +01:00
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
2015-12-05 01:11:25 +01:00
system.iocache.tags.sampled_refs 115499 # Sample count of references to valid blocks.
2014-10-30 05:50:15 +01:00
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
2015-11-06 09:26:50 +01:00
system.iocache.tags.warmup_cycle 13183709784000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 3.511467 # Average occupied blocks per requestor
2015-12-05 01:11:25 +01:00
system.iocache.tags.occ_blocks::realview.ide 6.935470 # Average occupied blocks per requestor
2015-11-06 09:26:50 +01:00
system.iocache.tags.occ_percent::realview.ethernet 0.219467 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.433467 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.652934 # Average percentage of cache occupancy
2014-10-30 05:50:15 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2015-12-05 01:11:25 +01:00
system.iocache.tags.tag_accesses 1039875 # Number of tag accesses
system.iocache.tags.data_accesses 1039875 # Number of data accesses
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
2015-12-05 01:11:25 +01:00
system.iocache.ReadReq_misses::realview.ide 8838 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8875 # number of ReadReq misses
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
2014-10-30 05:50:15 +01:00
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
2015-12-05 01:11:25 +01:00
system.iocache.demand_misses::realview.ide 8838 # number of demand (read+write) misses
system.iocache.demand_misses::total 8878 # number of demand (read+write) misses
2014-10-30 05:50:15 +01:00
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
2015-12-05 01:11:25 +01:00
system.iocache.overall_misses::realview.ide 8838 # number of overall misses
system.iocache.overall_misses::total 8878 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet 5070500 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide 1645846130 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 1650916630 # number of ReadReq miss cycles
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles
2015-12-05 01:11:25 +01:00
system.iocache.WriteLineReq_miss_latency::realview.ide 13863091781 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 13863091781 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet 5421500 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide 1645846130 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 1651267630 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet 5421500 # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide 1645846130 # number of overall miss cycles
system.iocache.overall_miss_latency::total 1651267630 # number of overall miss cycles
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
2015-12-05 01:11:25 +01:00
system.iocache.ReadReq_accesses::realview.ide 8838 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8875 # number of ReadReq accesses(hits+misses)
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
2014-10-30 05:50:15 +01:00
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
2015-12-05 01:11:25 +01:00
system.iocache.demand_accesses::realview.ide 8838 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 8878 # number of demand (read+write) accesses
2014-10-30 05:50:15 +01:00
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
2015-12-05 01:11:25 +01:00
system.iocache.overall_accesses::realview.ide 8838 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 8878 # number of overall (read+write) accesses
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2014-10-30 05:50:15 +01:00
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2015-12-05 01:11:25 +01:00
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137040.540541 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 186223.821000 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 186018.775211 # average ReadReq miss latency
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency
2015-12-05 01:11:25 +01:00
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129969.734690 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 129969.734690 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 186223.821000 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 185995.452805 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 186223.821000 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 185995.452805 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 33963 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-12-05 01:11:25 +01:00
system.iocache.blocked::no_mshrs 3509 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2015-12-05 01:11:25 +01:00
system.iocache.avg_blocked_cycles::no_mshrs 9.678826 # average number of cycles each access was blocked
2014-10-30 05:50:15 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
2014-10-30 05:50:15 +01:00
system.iocache.cache_copies 0 # number of cache copies performed
2015-09-25 13:27:03 +02:00
system.iocache.writebacks::writebacks 106630 # number of writebacks
system.iocache.writebacks::total 106630 # number of writebacks
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
2015-12-05 01:11:25 +01:00
system.iocache.ReadReq_mshr_misses::realview.ide 8838 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 8875 # number of ReadReq MSHR misses
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
2015-12-05 01:11:25 +01:00
system.iocache.demand_mshr_misses::realview.ide 8838 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 8878 # number of demand (read+write) MSHR misses
2014-10-30 05:50:15 +01:00
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
2015-12-05 01:11:25 +01:00
system.iocache.overall_mshr_misses::realview.ide 8838 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 8878 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220500 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1203946130 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 1207166630 # number of ReadReq MSHR miss cycles
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles
2015-12-05 01:11:25 +01:00
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8529891781 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 8529891781 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet 3421500 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 1203946130 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 1207367630 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet 3421500 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 1203946130 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 1207367630 # number of overall MSHR miss cycles
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2015-12-05 01:11:25 +01:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87040.540541 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136223.821000 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 136018.775211 # average ReadReq mshr miss latency
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
2015-12-05 01:11:25 +01:00
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79969.734690 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79969.734690 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 136223.821000 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 135995.452805 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 136223.821000 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 135995.452805 # average overall mshr miss latency
2014-10-30 05:50:15 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::ReadReq 76827 # Transaction distribution
2015-12-05 01:11:25 +01:00
system.membus.trans_dist::ReadResp 380834 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::WriteReq 33708 # Transaction distribution
system.membus.trans_dist::WriteResp 33708 # Transaction distribution
2015-12-05 01:11:25 +01:00
system.membus.trans_dist::WritebackDirty 957595 # Transaction distribution
system.membus.trans_dist::CleanEvict 155985 # Transaction distribution
system.membus.trans_dist::UpgradeReq 33274 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
system.membus.trans_dist::UpgradeResp 33277 # Transaction distribution
system.membus.trans_dist::ReadExReq 797439 # Transaction distribution
system.membus.trans_dist::ReadExResp 797439 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 304007 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution
system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6930 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3343278 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3472970 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341196 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 341196 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 3814166 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13860 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 124537568 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 124707394 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7226176 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7226176 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 131933570 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 3258 # Total snoops (count)
system.membus.snoop_fanout::samples 2468309 # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2015-12-05 01:11:25 +01:00
system.membus.snoop_fanout::1 2468309 100.00% 100.00% # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2015-12-05 01:11:25 +01:00
system.membus.snoop_fanout::total 2468309 # Request fanout histogram
system.membus.reqLayer0.occupancy 106920500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-03-02 11:04:20 +01:00
system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.membus.reqLayer2.occupancy 5785500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.membus.reqLayer5.occupancy 6298398949 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.membus.respLayer2.occupancy 6051404500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.membus.respLayer3.occupancy 227572547 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-12-04 01:19:05 +01:00
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
2014-12-02 12:08:25 +01:00
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
2015-12-04 01:19:05 +01:00
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
2014-10-30 05:50:15 +01:00
---------- End Simulation Statistics ----------
