2014-10-30 05:50:15 +01:00
---------- Begin Simulation Statistics ----------
2015-12-05 01:11:25 +01:00
sim_seconds 51.291806 # Number of seconds simulated
sim_ticks 51291805611000 # Number of ticks simulated
final_tick 51291805611000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2014-10-30 05:50:15 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2015-12-05 01:11:25 +01:00
host_inst_rate 109804 # Simulator instruction rate (inst/s)
host_op_rate 129027 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 6627600062 # Simulator tick rate (ticks/s)
host_mem_usage 686384 # Number of bytes of host memory used
host_seconds 7739.12 # Real time elapsed on the host
sim_insts 849784302 # Number of instructions simulated
sim_ops 998554740 # Number of ops (including micro ops) simulated
2014-10-30 05:50:15 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2015-12-05 01:11:25 +01:00
system.physmem.bytes_read::cpu.dtb.walker 234176 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 229184 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 5702880 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 74235720 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 438720 # Number of bytes read from this memory
system.physmem.bytes_read::total 80840680 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 5702880 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 5702880 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 69030592 # Number of bytes written to this memory
2014-12-02 12:08:25 +01:00
system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
2015-12-05 01:11:25 +01:00
system.physmem.bytes_written::total 69051172 # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker 3659 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 3581 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 105060 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1159946 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6855 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1279101 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1078603 # Number of write requests responded to by this memory
2014-12-02 12:08:25 +01:00
system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
2015-12-05 01:11:25 +01:00
system.physmem.num_writes::total 1081176 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker 4566 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 4468 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 111185 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1447321 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 8553 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1576093 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 111185 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 111185 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1345841 # Write bandwidth from this memory (bytes/s)
2015-09-25 13:27:03 +02:00
system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s)
2015-12-05 01:11:25 +01:00
system.physmem.bw_write::total 1346242 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1345841 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 4566 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 4468 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 111185 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1447722 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 8553 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2922335 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1279101 # Number of read requests accepted
system.physmem.writeReqs 1081176 # Number of write requests accepted
system.physmem.readBursts 1279101 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1081176 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 81811968 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 50496 # Total number of bytes read from write queue
system.physmem.bytesWritten 69050112 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 80840680 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 69051172 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 789 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 2248 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 335568 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 76700 # Per bank write bursts
system.physmem.perBankRdBursts::1 81593 # Per bank write bursts
system.physmem.perBankRdBursts::2 83146 # Per bank write bursts
system.physmem.perBankRdBursts::3 75940 # Per bank write bursts
system.physmem.perBankRdBursts::4 76984 # Per bank write bursts
system.physmem.perBankRdBursts::5 83084 # Per bank write bursts
system.physmem.perBankRdBursts::6 76647 # Per bank write bursts
system.physmem.perBankRdBursts::7 76510 # Per bank write bursts
system.physmem.perBankRdBursts::8 74528 # Per bank write bursts
system.physmem.perBankRdBursts::9 104951 # Per bank write bursts
system.physmem.perBankRdBursts::10 78345 # Per bank write bursts
system.physmem.perBankRdBursts::11 82619 # Per bank write bursts
system.physmem.perBankRdBursts::12 77692 # Per bank write bursts
system.physmem.perBankRdBursts::13 79270 # Per bank write bursts
system.physmem.perBankRdBursts::14 75132 # Per bank write bursts
system.physmem.perBankRdBursts::15 75171 # Per bank write bursts
system.physmem.perBankWrBursts::0 64170 # Per bank write bursts
system.physmem.perBankWrBursts::1 68321 # Per bank write bursts
system.physmem.perBankWrBursts::2 70316 # Per bank write bursts
system.physmem.perBankWrBursts::3 66616 # Per bank write bursts
system.physmem.perBankWrBursts::4 66722 # Per bank write bursts
system.physmem.perBankWrBursts::5 70167 # Per bank write bursts
system.physmem.perBankWrBursts::6 65460 # Per bank write bursts
system.physmem.perBankWrBursts::7 67223 # Per bank write bursts
system.physmem.perBankWrBursts::8 64606 # Per bank write bursts
system.physmem.perBankWrBursts::9 72209 # Per bank write bursts
system.physmem.perBankWrBursts::10 66721 # Per bank write bursts
system.physmem.perBankWrBursts::11 70434 # Per bank write bursts
system.physmem.perBankWrBursts::12 67362 # Per bank write bursts
system.physmem.perBankWrBursts::13 68403 # Per bank write bursts
system.physmem.perBankWrBursts::14 65406 # Per bank write bursts
system.physmem.perBankWrBursts::15 64772 # Per bank write bursts
2014-10-30 05:50:15 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
2015-12-05 01:11:25 +01:00
system.physmem.numWrRetry 27 # Number of times write queue was full causing retry
system.physmem.totGap 51291804197000 # Total gap between requests
2014-10-30 05:50:15 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 13 # Read request sizes (log2)
system.physmem.readPktSize::4 21272 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2015-12-05 01:11:25 +01:00
system.physmem.readPktSize::6 1257816 # Read request sizes (log2)
2014-10-30 05:50:15 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 1 # Write request sizes (log2)
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2015-12-05 01:11:25 +01:00
system.physmem.writePktSize::6 1078603 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 653601 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 337199 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 152943 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 128864 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 660 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 562 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 565 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1243 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 728 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 380 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 369 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 207 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 186 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 145 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 141 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 128 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 119 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 112 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 83 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 65 # What read queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see
2015-12-05 01:11:25 +01:00
system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
2014-10-30 05:50:15 +01:00
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
2015-12-05 01:11:25 +01:00
system.physmem.wrQLenPdf::15 12300 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 14327 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 32136 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 45674 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 55967 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 64595 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 66041 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 66802 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 68184 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 67465 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 67712 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 73018 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 67891 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 82006 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 85825 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 66342 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 70369 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 63013 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 1359 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 851 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 628 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 528 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 476 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 460 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 358 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 386 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 314 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 377 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 286 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 289 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 262 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 236 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 209 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 215 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 303 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 200 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 170 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 170 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 205 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 172 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 108 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 120 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 108 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 67 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 82 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 85 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 98 # What write queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.wrQLenPdf::62 55 # What write queue length does an incoming req see
2015-12-05 01:11:25 +01:00
system.physmem.wrQLenPdf::63 69 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 496985 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 303.554208 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 174.944807 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 333.108749 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 196641 39.57% 39.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 117090 23.56% 63.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 47261 9.51% 72.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 24196 4.87% 77.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 18882 3.80% 81.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 11863 2.39% 83.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 10943 2.20% 85.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 8246 1.66% 87.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 61863 12.45% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 496985 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 61535 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 20.773365 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 265.981989 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 61532 100.00% 100.00% # Reads before turning the bus around for writes
2015-07-03 16:15:03 +02:00
system.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::63488-65535 1 0.00% 100.00% # Reads before turning the bus around for writes
2015-12-05 01:11:25 +01:00
system.physmem.rdPerTurnAround::total 61535 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 61535 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 17.533241 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.977663 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 7.054277 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 58637 95.29% 95.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 877 1.43% 96.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 68 0.11% 96.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 330 0.54% 97.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 47 0.08% 97.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 368 0.60% 98.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 228 0.37% 98.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 20 0.03% 98.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 53 0.09% 98.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 138 0.22% 98.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 26 0.04% 98.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 33 0.05% 98.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 471 0.77% 99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 36 0.06% 99.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 24 0.04% 99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 129 0.21% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 1 0.00% 99.92% # Writes before turning the bus around for reads
2015-11-06 09:26:50 +01:00
system.physmem.wrPerTurnAround::84-87 1 0.00% 99.92% # Writes before turning the bus around for reads
2015-12-05 01:11:25 +01:00
system.physmem.wrPerTurnAround::92-95 2 0.00% 99.93% # Writes before turning the bus around for reads
2015-11-06 09:26:50 +01:00
system.physmem.wrPerTurnAround::100-103 2 0.00% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 2 0.00% 99.93% # Writes before turning the bus around for reads
2015-12-05 01:11:25 +01:00
system.physmem.wrPerTurnAround::108-111 2 0.00% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 1 0.00% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 1 0.00% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 3 0.00% 99.94% # Writes before turning the bus around for reads
2015-11-06 09:26:50 +01:00
system.physmem.wrPerTurnAround::128-131 25 0.04% 99.98% # Writes before turning the bus around for reads
2015-12-05 01:11:25 +01:00
system.physmem.wrPerTurnAround::132-135 2 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 2 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 3 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 2 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 61535 # Writes before turning the bus around for reads
system.physmem.totQLat 32791506957 # Total ticks spent queuing
system.physmem.totMemAccLat 56759856957 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 6391560000 # Total ticks spent in databus transfers
system.physmem.avgQLat 25652.19 # Average queueing delay per DRAM burst
2014-10-30 05:50:15 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2015-12-05 01:11:25 +01:00
system.physmem.avgMemAccLat 44402.19 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.60 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.35 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.58 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.35 # Average system write bandwidth in MiByte/s
2014-10-30 05:50:15 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2015-09-25 13:27:03 +02:00
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
2015-11-06 09:26:50 +01:00
system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
2015-12-05 01:11:25 +01:00
system.physmem.avgWrQLen 25.36 # Average write queue length when enqueuing
system.physmem.readRowHits 1048127 # Number of row buffer hits during reads
system.physmem.writeRowHits 812106 # Number of row buffer hits during writes
system.physmem.readRowHitRate 81.99 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 75.27 # Row buffer hit rate for writes
system.physmem.avgGap 21731264.68 # Average gap between requests
system.physmem.pageHitRate 78.92 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 1887739560 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 1030016625 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 4918711200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 3492687600 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3350131371600 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1239587078895 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 29687726109750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 34288773715230 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.503935 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 49388003607661 # Time in different power states
system.physmem_0.memoryStateTime::REF 1712746100000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-12-05 01:11:25 +01:00
system.physmem_0.memoryStateTime::ACT 191055633589 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-12-05 01:11:25 +01:00
system.physmem_1.actEnergy 1869467040 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 1020046500 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 5052099000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 3498636240 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3350131371600 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 1240740741510 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 29686714133250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 34289026495140 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.508863 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 49386297692325 # Time in different power states
system.physmem_1.memoryStateTime::REF 1712746100000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-12-05 01:11:25 +01:00
system.physmem_1.memoryStateTime::ACT 192761562675 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-11-06 09:26:50 +01:00
system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
2015-11-06 09:26:50 +01:00
system.realview.nvmem.bytes_read::total 420 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 384 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 384 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
2014-10-30 05:50:15 +01:00
system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
2015-11-06 09:26:50 +01:00
system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s)
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
2015-10-10 23:45:41 +02:00
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
2015-11-06 09:26:50 +01:00
system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
2015-10-10 23:45:41 +02:00
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
2014-10-30 05:50:15 +01:00
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
2015-12-05 01:11:25 +01:00
system.cpu.branchPred.lookups 224688792 # Number of BP lookups
system.cpu.branchPred.condPredicted 150206770 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 12191755 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 158635537 # Number of BTB lookups
system.cpu.branchPred.BTBHits 103690237 # Number of BTB hits
2014-10-30 05:50:15 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2015-12-05 01:11:25 +01:00
system.cpu.branchPred.BTBHitPct 65.363814 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 30864801 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 343432 # Number of incorrect RAS predictions.
2014-12-02 12:08:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2014-12-23 15:31:20 +01:00
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2015-12-05 01:11:25 +01:00
system.cpu.checker.dtb.walker.walks 198718 # Table walker walks requested
system.cpu.checker.dtb.walker.walksLong 198718 # Table walker walks initiated with long descriptors
system.cpu.checker.dtb.walker.walkWaitTime::samples 198718 # Table walker wait (enqueue to first request) latency
system.cpu.checker.dtb.walker.walkWaitTime::0 198718 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.checker.dtb.walker.walkWaitTime::total 198718 # Table walker wait (enqueue to first request) latency
2015-11-06 09:26:50 +01:00
system.cpu.checker.dtb.walker.walksPending::samples -1584953796 # Table walker pending requests distribution
system.cpu.checker.dtb.walker.walksPending::0 -1584953796 100.00% 100.00% # Table walker pending requests distribution
system.cpu.checker.dtb.walker.walksPending::total -1584953796 # Table walker pending requests distribution
2015-12-05 01:11:25 +01:00
system.cpu.checker.dtb.walker.walkPageSizes::4K 154432 91.32% 91.32% # Table walker page sizes translated
system.cpu.checker.dtb.walker.walkPageSizes::2M 14687 8.68% 100.00% # Table walker page sizes translated
system.cpu.checker.dtb.walker.walkPageSizes::total 169119 # Table walker page sizes translated
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 198718 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2015-12-05 01:11:25 +01:00
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 198718 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 169119 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2015-12-05 01:11:25 +01:00
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 169119 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin::total 367837 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
2015-12-05 01:11:25 +01:00
system.cpu.checker.dtb.read_hits 159761932 # DTB read hits
system.cpu.checker.dtb.read_misses 147725 # DTB read misses
system.cpu.checker.dtb.write_hits 145062914 # DTB write hits
system.cpu.checker.dtb.write_misses 50993 # DTB write misses
2015-09-25 13:27:03 +02:00
system.cpu.checker.dtb.flush_tlb 20 # Number of times complete TLB was flushed
2014-10-30 05:50:15 +01:00
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2015-12-05 01:11:25 +01:00
system.cpu.checker.dtb.flush_tlb_mva_asid 79146 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid 2042 # Number of times TLB was flushed by ASID
system.cpu.checker.dtb.flush_entries 72161 # Number of entries that have been flushed from TLB
2014-10-30 05:50:15 +01:00
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
2015-12-05 01:11:25 +01:00
system.cpu.checker.dtb.prefetch_faults 6829 # Number of TLB faults due to prefetch
2014-10-30 05:50:15 +01:00
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2015-12-05 01:11:25 +01:00
system.cpu.checker.dtb.perms_faults 19116 # Number of TLB faults due to permissions restrictions
system.cpu.checker.dtb.read_accesses 159909657 # DTB read accesses
system.cpu.checker.dtb.write_accesses 145113907 # DTB write accesses
2014-10-30 05:50:15 +01:00
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
2015-12-05 01:11:25 +01:00
system.cpu.checker.dtb.hits 304824846 # DTB hits
system.cpu.checker.dtb.misses 198718 # DTB misses
system.cpu.checker.dtb.accesses 305023564 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2015-12-05 01:11:25 +01:00
system.cpu.checker.itb.walker.walks 119115 # Table walker walks requested
system.cpu.checker.itb.walker.walksLong 119115 # Table walker walks initiated with long descriptors
system.cpu.checker.itb.walker.walkWaitTime::samples 119115 # Table walker wait (enqueue to first request) latency
system.cpu.checker.itb.walker.walkWaitTime::0 119115 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.checker.itb.walker.walkWaitTime::total 119115 # Table walker wait (enqueue to first request) latency
2015-11-06 09:26:50 +01:00
system.cpu.checker.itb.walker.walksPending::samples -1586149296 # Table walker pending requests distribution
system.cpu.checker.itb.walker.walksPending::0 -1586149296 100.00% 100.00% # Table walker pending requests distribution
system.cpu.checker.itb.walker.walksPending::total -1586149296 # Table walker pending requests distribution
2015-12-05 01:11:25 +01:00
system.cpu.checker.itb.walker.walkPageSizes::4K 107231 98.82% 98.82% # Table walker page sizes translated
system.cpu.checker.itb.walker.walkPageSizes::2M 1280 1.18% 100.00% # Table walker page sizes translated
system.cpu.checker.itb.walker.walkPageSizes::total 108511 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2015-12-05 01:11:25 +01:00
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 119115 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 119115 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2015-12-05 01:11:25 +01:00
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 108511 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 108511 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin::total 227626 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.inst_hits 850192533 # ITB inst hits
system.cpu.checker.itb.inst_misses 119115 # ITB inst misses
2014-10-30 05:50:15 +01:00
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.write_hits 0 # DTB write hits
system.cpu.checker.itb.write_misses 0 # DTB write misses
2015-09-25 13:27:03 +02:00
system.cpu.checker.itb.flush_tlb 20 # Number of times complete TLB was flushed
2014-10-30 05:50:15 +01:00
system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2015-12-05 01:11:25 +01:00
system.cpu.checker.itb.flush_tlb_mva_asid 79146 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.itb.flush_tlb_asid 2042 # Number of times TLB was flushed by ASID
system.cpu.checker.itb.flush_entries 51914 # Number of entries that have been flushed from TLB
2014-10-30 05:50:15 +01:00
system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
2015-12-05 01:11:25 +01:00
system.cpu.checker.itb.inst_accesses 850311648 # ITB inst accesses
system.cpu.checker.itb.hits 850192533 # DTB hits
system.cpu.checker.itb.misses 119115 # DTB misses
system.cpu.checker.itb.accesses 850311648 # DTB accesses
system.cpu.checker.numCycles 999125211 # number of cpu cycles simulated
2014-10-30 05:50:15 +01:00
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
2014-12-23 15:31:20 +01:00
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2015-12-05 01:11:25 +01:00
system.cpu.dtb.walker.walks 949667 # Table walker walks requested
system.cpu.dtb.walker.walksLong 949667 # Table walker walks initiated with long descriptors
system.cpu.dtb.walker.walksLongTerminationLevel::Level2 16250 # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksLongTerminationLevel::Level3 155668 # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksSquashedBefore 435817 # Table walks squashed before starting
system.cpu.dtb.walker.walkWaitTime::samples 513850 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::mean 2276.559307 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::stdev 14912.808509 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0-65535 510335 99.32% 99.32% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::65536-131071 1958 0.38% 99.70% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::131072-196607 1047 0.20% 99.90% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::196608-262143 218 0.04% 99.94% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::262144-327679 154 0.03% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::327680-393215 27 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::393216-458751 51 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::458752-524287 54 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total 513850 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples 485169 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 23149.084134 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 18057.598080 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 21275.722761 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-65535 473369 97.57% 97.57% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::65536-131071 7953 1.64% 99.21% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-196607 2827 0.58% 99.79% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::196608-262143 192 0.04% 99.83% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::262144-327679 567 0.12% 99.95% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::327680-393215 106 0.02% 99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::393216-458751 98 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::458752-524287 42 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::524288-589823 12 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total 485169 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples 791579212632 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::mean 0.715441 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::stdev 0.525649 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0-1 789339278132 99.72% 99.72% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::2-3 1195712000 0.15% 99.87% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::4-5 474046500 0.06% 99.93% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::6-7 207567500 0.03% 99.95% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::8-9 154449500 0.02% 99.97% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::10-11 121794500 0.02% 99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::12-13 29070000 0.00% 99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::14-15 54831500 0.01% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::16-17 2463000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total 791579212632 # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K 155669 90.55% 90.55% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::2M 16250 9.45% 100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total 171919 # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 949667 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2015-12-05 01:11:25 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 949667 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 171919 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2015-12-05 01:11:25 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 171919 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 1121586 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
2015-12-05 01:11:25 +01:00
system.cpu.dtb.read_hits 169633674 # DTB read hits
system.cpu.dtb.read_misses 671728 # DTB read misses
system.cpu.dtb.write_hits 147819857 # DTB write hits
system.cpu.dtb.write_misses 277939 # DTB write misses
2015-09-25 13:27:03 +02:00
system.cpu.dtb.flush_tlb 20 # Number of times complete TLB was flushed
2014-10-30 05:50:15 +01:00
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2015-12-05 01:11:25 +01:00
system.cpu.dtb.flush_tlb_mva_asid 79146 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 2042 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 72392 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 97 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 9958 # Number of TLB faults due to prefetch
2014-10-30 05:50:15 +01:00
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2015-12-05 01:11:25 +01:00
system.cpu.dtb.perms_faults 70151 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 170305402 # DTB read accesses
system.cpu.dtb.write_accesses 148097796 # DTB write accesses
2014-10-30 05:50:15 +01:00
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
2015-12-05 01:11:25 +01:00
system.cpu.dtb.hits 317453531 # DTB hits
system.cpu.dtb.misses 949667 # DTB misses
system.cpu.dtb.accesses 318403198 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2015-12-05 01:11:25 +01:00
system.cpu.itb.walker.walks 160444 # Table walker walks requested
system.cpu.itb.walker.walksLong 160444 # Table walker walks initiated with long descriptors
system.cpu.itb.walker.walksLongTerminationLevel::Level2 1424 # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksLongTerminationLevel::Level3 120836 # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksSquashedBefore 17536 # Table walks squashed before starting
system.cpu.itb.walker.walkWaitTime::samples 142908 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::mean 1360.753072 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::stdev 10149.850878 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0-32767 141808 99.23% 99.23% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::32768-65535 585 0.41% 99.64% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::65536-98303 64 0.04% 99.68% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::98304-131071 103 0.07% 99.76% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::131072-163839 274 0.19% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::163840-196607 31 0.02% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::196608-229375 7 0.00% 99.97% # Table walker wait (enqueue to first request) latency
2015-10-10 23:45:41 +02:00
system.cpu.itb.walker.walkWaitTime::229376-262143 8 0.01% 99.98% # Table walker wait (enqueue to first request) latency
2015-12-05 01:11:25 +01:00
system.cpu.itb.walker.walkWaitTime::262144-294911 17 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::294912-327679 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
2015-10-10 23:45:41 +02:00
system.cpu.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
2015-12-05 01:11:25 +01:00
system.cpu.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::393216-425983 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total 142908 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples 139796 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 29385.243498 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 24234.240486 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 24521.703817 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-65535 136348 97.53% 97.53% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::65536-131071 877 0.63% 98.16% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-196607 2201 1.57% 99.74% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::196608-262143 135 0.10% 99.83% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::262144-327679 151 0.11% 99.94% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::327680-393215 29 0.02% 99.96% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::393216-458751 40 0.03% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::458752-524287 7 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::589824-655359 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total 139796 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples 671317017344 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::mean 0.945059 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::stdev 0.228245 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0 36939918060 5.50% 5.50% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::1 634320646784 94.49% 99.99% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::2 55500500 0.01% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::3 942000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::4 10000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total 671317017344 # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K 120836 98.84% 98.84% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::2M 1424 1.16% 100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total 122260 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2015-12-05 01:11:25 +01:00
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 160444 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 160444 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2015-12-05 01:11:25 +01:00
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 122260 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 122260 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 282704 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 357283873 # ITB inst hits
system.cpu.itb.inst_misses 160444 # ITB inst misses
2014-10-30 05:50:15 +01:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
2015-09-25 13:27:03 +02:00
system.cpu.itb.flush_tlb 20 # Number of times complete TLB was flushed
2014-10-30 05:50:15 +01:00
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2015-12-05 01:11:25 +01:00
system.cpu.itb.flush_tlb_mva_asid 79146 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 2042 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 53225 # Number of entries that have been flushed from TLB
2014-10-30 05:50:15 +01:00
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
2015-12-05 01:11:25 +01:00
system.cpu.itb.perms_faults 370647 # Number of TLB faults due to permissions restrictions
2014-10-30 05:50:15 +01:00
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
2015-12-05 01:11:25 +01:00
system.cpu.itb.inst_accesses 357444317 # ITB inst accesses
system.cpu.itb.hits 357283873 # DTB hits
system.cpu.itb.misses 160444 # DTB misses
system.cpu.itb.accesses 357444317 # DTB accesses
system.cpu.numCycles 1651928956 # number of cpu cycles simulated
2014-10-30 05:50:15 +01:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2015-12-05 01:11:25 +01:00
system.cpu.fetch.icacheStallCycles 644904840 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1002675339 # Number of instructions fetch has processed
system.cpu.fetch.Branches 224688792 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 134555038 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 920067624 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 26040080 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 3808104 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles 29772 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 9331769 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 1037128 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 949 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 356896495 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 6093203 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 48590 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 1592200226 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.737909 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.145097 # Number of instructions fetched each cycle (Total)
2014-10-30 05:50:15 +01:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2015-12-05 01:11:25 +01:00
system.cpu.fetch.rateDist::0 1034156168 64.95% 64.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 214254104 13.46% 78.41% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 70725246 4.44% 82.85% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 273064708 17.15% 100.00% # Number of instructions fetched each cycle (Total)
2014-10-30 05:50:15 +01:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
2015-12-05 01:11:25 +01:00
system.cpu.fetch.rateDist::total 1592200226 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.136016 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.606972 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 524217376 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 575207225 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 433339906 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 50215792 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 9219927 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 33654884 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 3860028 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 1086626232 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 28988785 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 9219927 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 568973528 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 70181306 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 374019312 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 438766207 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 131039946 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 1066849636 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 6780403 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 5130065 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 345924 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 553258 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 79683463 # Number of times rename has blocked due to SQ full
system.cpu.rename.FullRegisterEvents 20375 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 1014727198 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 1644037540 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1261867774 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 1469696 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 949117253 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 65609942 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 27037743 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 23369810 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 103057716 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 173655780 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 151390357 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 9897841 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 9017927 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 1031708315 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 27333559 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1047312719 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 3286243 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 60487130 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 33695071 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 315067 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1592200226 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.657777 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 0.917314 # Number of insts issued each cycle
2014-10-30 05:50:15 +01:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2015-12-05 01:11:25 +01:00
system.cpu.iq.issued_per_cycle::0 943790813 59.28% 59.28% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 334741898 21.02% 80.30% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 234957148 14.76% 95.06% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 72204170 4.53% 99.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 6486970 0.41% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 19227 0.00% 100.00% # Number of insts issued each cycle
2014-10-30 05:50:15 +01:00
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
2015-12-05 01:11:25 +01:00
system.cpu.iq.issued_per_cycle::total 1592200226 # Number of insts issued each cycle
2014-10-30 05:50:15 +01:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2015-12-05 01:11:25 +01:00
system.cpu.iq.fu_full::IntAlu 57844214 35.03% 35.03% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 99575 0.06% 35.09% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 26721 0.02% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 685 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 44353632 26.86% 61.97% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 62797684 38.03% 100.00% # attempts to use FU when none available
2014-10-30 05:50:15 +01:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2015-12-05 01:11:25 +01:00
system.cpu.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 721297441 68.87% 68.87% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 2539668 0.24% 69.11% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 122649 0.01% 69.13% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 69.13% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.13% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.13% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.13% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.13% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 121234 0.01% 69.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.14% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 173513888 16.57% 85.70% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 149717789 14.30% 100.00% # Type of FU issued
2014-10-30 05:50:15 +01:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2015-12-05 01:11:25 +01:00
system.cpu.iq.FU_type_0::total 1047312719 # Type of FU issued
system.cpu.iq.rate 0.633994 # Inst issue rate
system.cpu.iq.fu_busy_cnt 165122511 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.157663 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 3852756863 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 1118723028 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1029355100 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 2477554 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 946947 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 909717 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1210878214 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 1557015 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 4319350 # Number of loads that had data forwarded from stores
2014-10-30 05:50:15 +01:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2015-12-05 01:11:25 +01:00
system.cpu.iew.lsq.thread0.squashedLoads 13798077 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 14626 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 142237 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 6323389 # Number of stores squashed
2014-10-30 05:50:15 +01:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2015-12-05 01:11:25 +01:00
system.cpu.iew.lsq.thread0.rescheduledLoads 2533948 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 1563961 # Number of times an access to memory failed due to the cache being blocked
2014-10-30 05:50:15 +01:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2015-12-05 01:11:25 +01:00
system.cpu.iew.iewSquashCycles 9219927 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 7084785 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 9314562 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 1059264038 # Number of instructions dispatched to IQ
2014-10-30 05:50:15 +01:00
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2015-12-05 01:11:25 +01:00
system.cpu.iew.iewDispLoadInsts 173655780 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 151390357 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 22943670 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 58438 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 9182367 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 142237 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 3657929 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 5098518 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 8756447 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1036137894 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 169621625 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 10236296 # Number of squashed instructions skipped in execute
2014-10-30 05:50:15 +01:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
2015-12-05 01:11:25 +01:00
system.cpu.iew.exec_nop 222164 # number of nop insts executed
system.cpu.iew.exec_refs 317437095 # number of memory reference insts executed
system.cpu.iew.exec_branches 196547238 # Number of branches executed
system.cpu.iew.exec_stores 147815470 # Number of stores executed
system.cpu.iew.exec_rate 0.627229 # Inst execution rate
system.cpu.iew.wb_sent 1031075002 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1030264817 # cumulative count of insts written-back
system.cpu.iew.wb_producers 438532269 # num instructions producing a value
system.cpu.iew.wb_consumers 709380763 # num instructions consuming a value
system.cpu.iew.wb_rate 0.623674 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.618190 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 51390718 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 27018492 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 8391642 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1580228062 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.631905 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.268654 # Number of insts commited each cycle
2014-10-30 05:50:15 +01:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2015-12-05 01:11:25 +01:00
system.cpu.commit.committed_per_cycle::0 1067496193 67.55% 67.55% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 288499411 18.26% 85.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 120593665 7.63% 93.44% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 36542296 2.31% 95.75% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 28489830 1.80% 97.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 14035785 0.89% 98.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 8641720 0.55% 98.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 4180750 0.26% 99.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 11748412 0.74% 100.00% # Number of insts commited each cycle
2014-10-30 05:50:15 +01:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2015-12-05 01:11:25 +01:00
system.cpu.commit.committed_per_cycle::total 1580228062 # Number of insts commited each cycle
system.cpu.commit.committedInsts 849784302 # Number of instructions committed
system.cpu.commit.committedOps 998554740 # Number of ops (including micro ops) committed
2014-10-30 05:50:15 +01:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
2015-12-05 01:11:25 +01:00
system.cpu.commit.refs 304924670 # Number of memory references committed
system.cpu.commit.loads 159857702 # Number of loads committed
system.cpu.commit.membars 6942890 # Number of memory barriers committed
system.cpu.commit.branches 189641559 # Number of branches committed
system.cpu.commit.fp_insts 896155 # Number of committed floating point instructions.
system.cpu.commit.int_insts 917432780 # Number of committed integer instructions.
system.cpu.commit.function_calls 25317062 # Number of function calls committed.
2014-10-30 05:50:15 +01:00
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2015-12-05 01:11:25 +01:00
system.cpu.commit.op_class_0::IntAlu 691266097 69.23% 69.23% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 2154064 0.22% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 98002 0.01% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 111865 0.01% 69.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 159857702 16.01% 85.47% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 145066968 14.53% 100.00% # Class of committed instruction
2014-10-30 05:50:15 +01:00
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2015-12-05 01:11:25 +01:00
system.cpu.commit.op_class_0::total 998554740 # Class of committed instruction
system.cpu.commit.bw_lim_events 11748412 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 2610868733 # The number of ROB reads
system.cpu.rob.rob_writes 2111769063 # The number of ROB writes
system.cpu.timesIdled 8146861 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 59728730 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 100931682357 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 849784302 # Number of Instructions Simulated
system.cpu.committedOps 998554740 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 1.943939 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.943939 # CPI: Total CPI of All Threads
system.cpu.ipc 0.514419 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.514419 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 1226658290 # number of integer regfile reads
system.cpu.int_regfile_writes 732482520 # number of integer regfile writes
system.cpu.fp_regfile_reads 1461367 # number of floating regfile reads
system.cpu.fp_regfile_writes 784012 # number of floating regfile writes
system.cpu.cc_regfile_reads 225710355 # number of cc regfile reads
system.cpu.cc_regfile_writes 226370154 # number of cc regfile writes
system.cpu.misc_regfile_reads 2581410543 # number of misc regfile reads
system.cpu.misc_regfile_writes 27063260 # number of misc regfile writes
system.cpu.dcache.tags.replacements 9708370 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.972782 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 283529628 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 9708882 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 29.203118 # Average number of references to valid blocks.
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.warmup_cycle 2743199500 # Cycle when the warmup percentage was hit.
2015-12-05 01:11:25 +01:00
system.cpu.dcache.tags.occ_blocks::cpu.data 511.972782 # Average occupied blocks per requestor
2015-09-25 13:27:03 +02:00
system.cpu.dcache.tags.occ_percent::cpu.data 0.999947 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999947 # Average percentage of cache occupancy
2014-12-02 12:08:25 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
2015-12-05 01:11:25 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::1 379 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
2014-12-02 12:08:25 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2015-12-05 01:11:25 +01:00
system.cpu.dcache.tags.tag_accesses 1238524544 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1238524544 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 147275132 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 147275132 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 128498890 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 128498890 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 378449 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 378449 # number of SoftPFReq hits
system.cpu.dcache.WriteLineReq_hits::cpu.data 323156 # number of WriteLineReq hits
system.cpu.dcache.WriteLineReq_hits::total 323156 # number of WriteLineReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3306743 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 3306743 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 3702780 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 3702780 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 275774022 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 275774022 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 276152471 # number of overall hits
system.cpu.dcache.overall_hits::total 276152471 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 9562571 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 9562571 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 11295910 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 11295910 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 1177323 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 1177323 # number of SoftPFReq misses
system.cpu.dcache.WriteLineReq_misses::cpu.data 1234379 # number of WriteLineReq misses
system.cpu.dcache.WriteLineReq_misses::total 1234379 # number of WriteLineReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 448575 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 448575 # number of LoadLockedReq misses
2015-09-25 13:27:03 +02:00
system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses
2015-12-05 01:11:25 +01:00
system.cpu.dcache.demand_misses::cpu.data 20858481 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 20858481 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 22035804 # number of overall misses
system.cpu.dcache.overall_misses::total 22035804 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 169032232500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 169032232500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 449840740248 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 449840740248 # number of WriteReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 90036958042 # number of WriteLineReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::total 90036958042 # number of WriteLineReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6928434500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 6928434500 # number of LoadLockedReq miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 275500 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 275500 # number of StoreCondReq miss cycles
2015-12-05 01:11:25 +01:00
system.cpu.dcache.demand_miss_latency::cpu.data 618872972748 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 618872972748 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 618872972748 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 618872972748 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 156837703 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 156837703 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 139794800 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 139794800 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 1555772 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 1555772 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::cpu.data 1557535 # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::total 1557535 # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3755318 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 3755318 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3702785 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 3702785 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 296632503 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 296632503 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 298188275 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 298188275 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060971 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.060971 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080804 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.080804 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.756745 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.756745 # miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.792521 # miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::total 0.792521 # miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119451 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119451 # miss rate for LoadLockedReq accesses
2015-09-15 15:14:09 +02:00
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses
2015-12-05 01:11:25 +01:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.070318 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.070318 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.073899 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.073899 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17676.442089 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 17676.442089 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39823.328997 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 39823.328997 # average WriteReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 72941.096731 # average WriteLineReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::total 72941.096731 # average WriteLineReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15445.431645 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15445.431645 # average LoadLockedReq miss latency
2015-11-06 09:26:50 +01:00
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 55100 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 55100 # average StoreCondReq miss latency
2015-12-05 01:11:25 +01:00
system.cpu.dcache.demand_avg_miss_latency::cpu.data 29670.088284 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 29670.088284 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 28084.882800 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 28084.882800 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 50470132 # number of cycles access was blocked
2014-12-02 12:08:25 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-12-05 01:11:25 +01:00
system.cpu.dcache.blocked::no_mshrs 1604709 # number of cycles access was blocked
2014-12-02 12:08:25 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
2015-12-05 01:11:25 +01:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.451267 # average number of cycles each access was blocked
2014-12-02 12:08:25 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
2015-12-05 01:11:25 +01:00
system.cpu.dcache.writebacks::writebacks 7520985 # number of writebacks
system.cpu.dcache.writebacks::total 7520985 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4446912 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 4446912 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9285751 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 9285751 # number of WriteReq MSHR hits
system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7178 # number of WriteLineReq MSHR hits
system.cpu.dcache.WriteLineReq_mshr_hits::total 7178 # number of WriteLineReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 219380 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 219380 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 13732663 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 13732663 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 13732663 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 13732663 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5115659 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 5115659 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2010159 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 2010159 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1170514 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 1170514 # number of SoftPFReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1227201 # number of WriteLineReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::total 1227201 # number of WriteLineReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 229195 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 229195 # number of LoadLockedReq MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses
2015-12-05 01:11:25 +01:00
system.cpu.dcache.demand_mshr_misses::cpu.data 7125818 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 7125818 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 8296332 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 8296332 # number of overall MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total 33678 # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67374 # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total 67374 # number of overall MSHR uncacheable misses
2015-12-05 01:11:25 +01:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 85157095500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 85157095500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 78478155174 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 78478155174 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 23792891000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 23792891000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 88415534042 # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 88415534042 # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3234901000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3234901000 # number of LoadLockedReq MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 270500 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 270500 # number of StoreCondReq MSHR miss cycles
2015-12-05 01:11:25 +01:00
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 163635250674 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 163635250674 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187428141674 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 187428141674 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6191802000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6191802000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6228377464 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6228377464 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12420179464 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 12420179464 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032618 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032618 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014379 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014379 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.752369 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.752369 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787912 # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787912 # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.061032 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.061032 # mshr miss rate for LoadLockedReq accesses
2015-09-15 15:14:09 +02:00
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
2015-12-05 01:11:25 +01:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024022 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.024022 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027822 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.027822 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16646.358856 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16646.358856 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39040.769996 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39040.769996 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 20326.874348 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 20326.874348 # average SoftPFReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 72046.497715 # average WriteLineReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 72046.497715 # average WriteLineReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14114.186610 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14114.186610 # average LoadLockedReq mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 54100 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 54100 # average StoreCondReq mshr miss latency
2015-12-05 01:11:25 +01:00
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22963.714576 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22963.714576 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22591.687709 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22591.687709 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183853.019776 # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183853.019776 # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184840.261871 # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184840.261871 # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184346.772702 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184346.772702 # average overall mshr uncacheable latency
2014-12-02 12:08:25 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-12-05 01:11:25 +01:00
system.cpu.icache.tags.replacements 15025014 # number of replacements
system.cpu.icache.tags.tagsinuse 511.916800 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 341084146 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 15025526 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 22.700313 # Average number of references to valid blocks.
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.warmup_cycle 24730722500 # Cycle when the warmup percentage was hit.
2015-12-05 01:11:25 +01:00
system.cpu.icache.tags.occ_blocks::cpu.inst 511.916800 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.999837 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.999837 # Average percentage of cache occupancy
2014-10-30 05:50:15 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2015-12-05 01:11:25 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 97 # Occupied blocks per task id
2014-10-30 05:50:15 +01:00
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2015-12-05 01:11:25 +01:00
system.cpu.icache.tags.tag_accesses 371900940 # Number of tag accesses
system.cpu.icache.tags.data_accesses 371900940 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 341084146 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 341084146 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 341084146 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 341084146 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 341084146 # number of overall hits
system.cpu.icache.overall_hits::total 341084146 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 15791051 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 15791051 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 15791051 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 15791051 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 15791051 # number of overall misses
system.cpu.icache.overall_misses::total 15791051 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 213656099879 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 213656099879 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 213656099879 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 213656099879 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 213656099879 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 213656099879 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 356875197 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 356875197 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 356875197 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 356875197 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 356875197 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 356875197 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044248 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.044248 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.044248 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.044248 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.044248 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.044248 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13530.201370 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13530.201370 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13530.201370 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13530.201370 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13530.201370 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13530.201370 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 23378 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-12-05 01:11:25 +01:00
system.cpu.icache.blocked::no_mshrs 1447 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
2015-12-05 01:11:25 +01:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 16.156185 # average number of cycles each access was blocked
2014-10-30 05:50:15 +01:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
2015-12-05 01:11:25 +01:00
system.cpu.icache.writebacks::writebacks 15025014 # number of writebacks
system.cpu.icache.writebacks::total 15025014 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 765308 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 765308 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 765308 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 765308 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 765308 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 765308 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15025743 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 15025743 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 15025743 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 15025743 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 15025743 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 15025743 # number of overall MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21294 # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total 21294 # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21294 # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total 21294 # number of overall MSHR uncacheable misses
2015-12-05 01:11:25 +01:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 191350406888 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 191350406888 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 191350406888 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 191350406888 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 191350406888 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 191350406888 # number of overall MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 2684938000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 2684938000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 2684938000 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 2684938000 # number of overall MSHR uncacheable cycles
2015-12-05 01:11:25 +01:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.042104 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.042104 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.042104 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.042104 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.042104 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.042104 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12734.838263 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12734.838263 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12734.838263 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12734.838263 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12734.838263 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12734.838263 # average overall mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126088.945243 # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126088.945243 # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126088.945243 # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126088.945243 # average overall mshr uncacheable latency
2014-10-30 05:50:15 +01:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.tags.replacements 1160032 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65258.923808 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 46054624 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 1222499 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 37.672525 # Average number of references to valid blocks.
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.warmup_cycle 22908442500 # Cycle when the warmup percentage was hit.
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.tags.occ_blocks::writebacks 37170.221016 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 291.467899 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 431.621608 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 7623.970972 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 19741.642313 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.567173 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004447 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006586 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.116333 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.301234 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.995772 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023 293 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 62174 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 293 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 537 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2696 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5137 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53733 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004471 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.948700 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 409232486 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 409232486 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 784138 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 294772 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1078910 # number of ReadReq hits
system.cpu.l2cache.WritebackDirty_hits::writebacks 7520985 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 7520985 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 15022476 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 15022476 # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 9415 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 9415 # number of UpgradeReq hits
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadExReq_hits::cpu.data 1567928 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1567928 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14941736 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 14941736 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6252288 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 6252288 # number of ReadSharedReq hits
system.cpu.l2cache.InvalidateReq_hits::cpu.data 727284 # number of InvalidateReq hits
system.cpu.l2cache.InvalidateReq_hits::total 727284 # number of InvalidateReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 784138 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 294772 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 14941736 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 7820216 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 23840862 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 784138 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 294772 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 14941736 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 7820216 # number of overall hits
system.cpu.l2cache.overall_hits::total 23840862 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3659 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3581 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 7240 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 34429 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 34429 # number of UpgradeReq misses
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 401685 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 401685 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 83804 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 83804 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 259790 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 259790 # number of ReadSharedReq misses
system.cpu.l2cache.InvalidateReq_misses::cpu.data 499917 # number of InvalidateReq misses
system.cpu.l2cache.InvalidateReq_misses::total 499917 # number of InvalidateReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 3659 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 3581 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 83804 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 661475 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 752519 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 3659 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 3581 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 83804 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 661475 # number of overall misses
system.cpu.l2cache.overall_misses::total 752519 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 501202500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 492625000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 993827500 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1425712500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 1425712500 # number of UpgradeReq miss cycles
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 160500 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 160500 # number of SCUpgradeReq miss cycles
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 55829389500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 55829389500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 11292976500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 11292976500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 36167039500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 36167039500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 77475596000 # number of InvalidateReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::total 77475596000 # number of InvalidateReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 501202500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 492625000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 11292976500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 91996429000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 104283233000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 501202500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 492625000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 11292976500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 91996429000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 104283233000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 787797 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 298353 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1086150 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::writebacks 7520985 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 7520985 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 15022476 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 15022476 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 43844 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 43844 # number of UpgradeReq accesses(hits+misses)
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses)
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1969613 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1969613 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15025540 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 15025540 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6512078 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 6512078 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1227201 # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::total 1227201 # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 787797 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 298353 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 15025540 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 8481691 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 24593381 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 787797 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 298353 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 15025540 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 8481691 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 24593381 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.004645 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.012003 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.006666 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.785261 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.785261 # miss rate for UpgradeReq accesses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.600000 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.600000 # miss rate for SCUpgradeReq accesses
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.203941 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.203941 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005577 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005577 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.039894 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.039894 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.407364 # miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::total 0.407364 # miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.004645 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.012003 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005577 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.077989 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.030598 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.004645 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.012003 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005577 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.077989 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.030598 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 136977.999453 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 137566.322256 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 137268.991713 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 41410.221035 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 41410.221035 # average UpgradeReq miss latency
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 53500 # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 53500 # average SCUpgradeReq miss latency
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 138987.986855 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 138987.986855 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134754.623884 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134754.623884 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 139216.442126 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 139216.442126 # average ReadSharedReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 154976.918168 # average InvalidateReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 154976.918168 # average InvalidateReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136977.999453 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 137566.322256 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134754.623884 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 139077.711176 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 138578.870434 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136977.999453 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 137566.322256 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134754.623884 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 139077.711176 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 138578.870434 # average overall miss latency
2014-10-30 05:50:15 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.writebacks::writebacks 971973 # number of writebacks
system.cpu.l2cache.writebacks::total 971973 # number of writebacks
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 19 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 19 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 19 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 19 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 19 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 19 # number of overall MSHR hits
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 3659 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3581 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 7240 # number of ReadReq MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 34429 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 34429 # number of UpgradeReq MSHR misses
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 401685 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 401685 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 83804 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 83804 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 259771 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 259771 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 499917 # number of InvalidateReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::total 499917 # number of InvalidateReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 3659 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3581 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 83804 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 661456 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 752500 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 3659 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3581 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 83804 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 661456 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 752500 # number of overall MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 21294 # number of ReadReq MSHR uncacheable
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 54972 # number of ReadReq MSHR uncacheable
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 21294 # number of overall MSHR uncacheable misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67374 # number of overall MSHR uncacheable misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 88668 # number of overall MSHR uncacheable misses
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 464612500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 456815000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 921427500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2436642500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2436642500 # number of UpgradeReq MSHR miss cycles
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 212000 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 212000 # number of SCUpgradeReq MSHR miss cycles
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 51812539500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 51812539500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10454936500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10454936500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 33566675000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 33566675000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 72476426000 # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 72476426000 # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 464612500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 456815000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10454936500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 85379214500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 96755578500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 464612500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 456815000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10454936500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 85379214500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 96755578500 # number of overall MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 2418763000 # number of ReadReq MSHR uncacheable cycles
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5770632000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8189395000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5836350500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5836350500 # number of WriteReq MSHR uncacheable cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2418763000 # number of overall MSHR uncacheable cycles
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11606982500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 14025745500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004645 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.012003 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.006666 # mshr miss rate for ReadReq accesses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.785261 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.785261 # mshr miss rate for UpgradeReq accesses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for SCUpgradeReq accesses
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.203941 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.203941 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005577 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005577 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.039891 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.039891 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.407364 # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.407364 # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004645 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.012003 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005577 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.077986 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.030598 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004645 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.012003 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005577 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.077986 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.030598 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126977.999453 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 127566.322256 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127268.991713 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70772.967556 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70772.967556 # average UpgradeReq mshr miss latency
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70666.666667 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70666.666667 # average SCUpgradeReq mshr miss latency
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 128987.986855 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 128987.986855 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124754.623884 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124754.623884 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 129216.405988 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 129216.405988 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 144976.918168 # average InvalidateReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 144976.918168 # average InvalidateReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126977.999453 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127566.322256 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124754.623884 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 129077.692998 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128578.841860 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126977.999453 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127566.322256 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124754.623884 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129077.692998 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128578.841860 # average overall mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.945243 # average ReadReq mshr uncacheable latency
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171347.229645 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148973.932184 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173206.033357 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173206.033357 # average WriteReq mshr uncacheable latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.945243 # average overall mshr uncacheable latency
2015-12-05 01:11:25 +01:00
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172276.879805 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158182.720937 # average overall mshr uncacheable latency
2014-10-30 05:50:15 +01:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.snoop_filter.tot_requests 50209605 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 25474994 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3484 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 2120 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2120 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.trans_dist::ReadReq 1623677 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 23162262 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.trans_dist::WritebackDirty 8599615 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 15022476 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 2383518 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 43847 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.trans_dist::UpgradeResp 43852 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1969613 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1969613 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 15025743 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 6520923 # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq 1333865 # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateResp 1227201 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45116347 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29348618 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 723959 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1930896 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 77119820 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1923413728 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1024410462 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2386824 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6302376 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 2956513390 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 1874549 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 27826881 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.025283 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.156985 # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.snoop_fanout::0 27123321 97.47% 97.47% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 703560 2.53% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.snoop_fanout::total 27826881 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 48147469995 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.snoopLayer0.occupancy 1446401 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.respLayer0.occupancy 22568730706 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 13411529968 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.respLayer2.occupancy 425937320 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.cpu.toL2Bus.respLayer3.occupancy 1143472216 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.trans_dist::ReadReq 40293 # Transaction distribution
system.iobus.trans_dist::ReadResp 40293 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230944 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 230944 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count::total 353728 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334208 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7334208 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size::total 7492128 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 41872500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer2.occupancy 342000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer16.occupancy 14500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer23.occupancy 25139500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer24.occupancy 36500500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer25.occupancy 565848565 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2015-07-03 16:15:03 +02:00
system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.respLayer3.occupancy 147704000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-07-03 16:15:03 +02:00
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iocache.tags.replacements 115453 # number of replacements
system.iocache.tags.tagsinuse 10.417914 # Cycle average of tags in use
2014-10-30 05:50:15 +01:00
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
2015-12-05 01:11:25 +01:00
system.iocache.tags.sampled_refs 115469 # Sample count of references to valid blocks.
2014-10-30 05:50:15 +01:00
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
2015-11-06 09:26:50 +01:00
system.iocache.tags.warmup_cycle 13103145499000 # Cycle when the warmup percentage was hit.
2015-12-05 01:11:25 +01:00
system.iocache.tags.occ_blocks::realview.ethernet 3.546638 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 6.871276 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.221665 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.429455 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.651120 # Average percentage of cache occupancy
2014-10-30 05:50:15 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2015-12-05 01:11:25 +01:00
system.iocache.tags.tag_accesses 1039605 # Number of tag accesses
system.iocache.tags.data_accesses 1039605 # Number of data accesses
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
2015-12-05 01:11:25 +01:00
system.iocache.ReadReq_misses::realview.ide 8808 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8845 # number of ReadReq misses
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
2014-10-30 05:50:15 +01:00
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
2015-12-05 01:11:25 +01:00
system.iocache.demand_misses::realview.ide 8808 # number of demand (read+write) misses
system.iocache.demand_misses::total 8848 # number of demand (read+write) misses
2014-10-30 05:50:15 +01:00
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
2015-12-05 01:11:25 +01:00
system.iocache.overall_misses::realview.ide 8808 # number of overall misses
system.iocache.overall_misses::total 8848 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet 5070500 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide 1690818481 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 1695888981 # number of ReadReq miss cycles
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles
2015-12-05 01:11:25 +01:00
system.iocache.WriteLineReq_miss_latency::realview.ide 13865997584 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 13865997584 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet 5421500 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide 1690818481 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 1696239981 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet 5421500 # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide 1690818481 # number of overall miss cycles
system.iocache.overall_miss_latency::total 1696239981 # number of overall miss cycles
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
2015-12-05 01:11:25 +01:00
system.iocache.ReadReq_accesses::realview.ide 8808 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8845 # number of ReadReq accesses(hits+misses)
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
2014-10-30 05:50:15 +01:00
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
2015-12-05 01:11:25 +01:00
system.iocache.demand_accesses::realview.ide 8808 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 8848 # number of demand (read+write) accesses
2014-10-30 05:50:15 +01:00
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
2015-12-05 01:11:25 +01:00
system.iocache.overall_accesses::realview.ide 8808 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 8848 # number of overall (read+write) accesses
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2014-10-30 05:50:15 +01:00
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2015-12-05 01:11:25 +01:00
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137040.540541 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 191963.951067 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 191734.197965 # average ReadReq miss latency
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency
2015-12-05 01:11:25 +01:00
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129996.977274 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 129996.977274 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 191963.951067 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 191708.858612 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 191963.951067 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 191708.858612 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 36185 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-12-05 01:11:25 +01:00
system.iocache.blocked::no_mshrs 3641 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2015-12-05 01:11:25 +01:00
system.iocache.avg_blocked_cycles::no_mshrs 9.938204 # average number of cycles each access was blocked
2014-10-30 05:50:15 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
2014-10-30 05:50:15 +01:00
system.iocache.cache_copies 0 # number of cache copies performed
2015-03-02 11:04:20 +01:00
system.iocache.writebacks::writebacks 106630 # number of writebacks
system.iocache.writebacks::total 106630 # number of writebacks
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
2015-12-05 01:11:25 +01:00
system.iocache.ReadReq_mshr_misses::realview.ide 8808 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 8845 # number of ReadReq MSHR misses
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
2015-12-05 01:11:25 +01:00
system.iocache.demand_mshr_misses::realview.ide 8808 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 8848 # number of demand (read+write) MSHR misses
2014-10-30 05:50:15 +01:00
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
2015-12-05 01:11:25 +01:00
system.iocache.overall_mshr_misses::realview.ide 8808 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 8848 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220500 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1250418481 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 1253638981 # number of ReadReq MSHR miss cycles
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles
2015-12-05 01:11:25 +01:00
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8532797584 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 8532797584 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet 3421500 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 1250418481 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 1253839981 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet 3421500 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 1250418481 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 1253839981 # number of overall MSHR miss cycles
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2015-12-05 01:11:25 +01:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87040.540541 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141963.951067 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 141734.197965 # average ReadReq mshr miss latency
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
2015-12-05 01:11:25 +01:00
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79996.977274 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79996.977274 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 141963.951067 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 141708.858612 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 141963.951067 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 141708.858612 # average overall mshr miss latency
2014-10-30 05:50:15 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-06 09:26:50 +01:00
system.membus.trans_dist::ReadReq 54972 # Transaction distribution
2015-12-05 01:11:25 +01:00
system.membus.trans_dist::ReadResp 414632 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::WriteReq 33696 # Transaction distribution
system.membus.trans_dist::WriteResp 33696 # Transaction distribution
2015-12-05 01:11:25 +01:00
system.membus.trans_dist::WritebackDirty 1078603 # Transaction distribution
system.membus.trans_dist::CleanEvict 193680 # Transaction distribution
system.membus.trans_dist::UpgradeReq 35229 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
2015-12-05 01:11:25 +01:00
system.membus.trans_dist::UpgradeResp 35232 # Transaction distribution
system.membus.trans_dist::ReadExReq 900805 # Transaction distribution
system.membus.trans_dist::ReadExResp 900805 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 359660 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution
system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3779727 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3909347 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342337 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 342337 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 4251684 # Packet count per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 420 # Cumulative packet size per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 142628812 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 142798782 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7263040 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7263040 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 150061822 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 2657 # Total snoops (count)
system.membus.snoop_fanout::samples 2765486 # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2015-12-05 01:11:25 +01:00
system.membus.snoop_fanout::1 2765486 100.00% 100.00% # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2015-12-05 01:11:25 +01:00
system.membus.snoop_fanout::total 2765486 # Request fanout histogram
system.membus.reqLayer0.occupancy 103948000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.membus.reqLayer1.occupancy 32000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.membus.reqLayer2.occupancy 5458000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.membus.reqLayer5.occupancy 7323908114 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.membus.respLayer2.occupancy 6816104590 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.membus.respLayer3.occupancy 227615986 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-12-04 01:19:05 +01:00
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
2014-12-02 12:08:25 +01:00
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
2015-09-25 13:27:03 +02:00
system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
2014-12-02 12:08:25 +01:00
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
2015-09-25 13:27:03 +02:00
system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
2014-12-02 12:08:25 +01:00
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
2015-12-04 01:19:05 +01:00
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
2014-10-30 05:50:15 +01:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
2015-12-05 01:11:25 +01:00
system.cpu.kern.inst.quiesce 16126 # number of quiesce instructions executed
2014-10-30 05:50:15 +01:00
---------- End Simulation Statistics ----------
