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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt

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ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
---------- Begin Simulation Statistics ----------
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
sim_seconds 2.613797 # Number of seconds simulated
sim_ticks 2613796876500 # Number of ticks simulated
final_tick 2613796876500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
host_inst_rate 54493 # Simulator instruction rate (inst/s)
host_op_rate 70162 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2268463215 # Simulator tick rate (ticks/s)
host_mem_usage 404628 # Number of bytes of host memory used
host_seconds 1152.23 # Real time elapsed on the host
sim_insts 62788171 # Number of instructions simulated
sim_ops 80843130 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.physmem.bytes_read::cpu0.dtb.walker 704 # Number of bytes read from this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 395008 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 4352820 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 1152 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 426432 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 5278640 # Number of bytes read from this memory
system.physmem.bytes_read::total 131565412 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 395008 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 426432 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 821440 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4275200 # Number of bytes written to this memory
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory
system.physmem.bytes_written::total 7304336 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.physmem.num_reads::cpu0.dtb.walker 11 # Number of read requests responded to by this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 6172 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 68085 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 18 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 6663 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 82505 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15302272 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66800 # Number of write requests responded to by this memory
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory
system.physmem.num_writes::total 824084 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 46335096 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 269 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 151124 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1665325 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 441 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 163147 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 2019530 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 50334979 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 151124 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 163147 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 314271 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1635628 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6504 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 1152399 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2794531 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1635628 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 46335096 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 269 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 151124 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 1671828 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 441 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 163147 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 3171928 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 53129510 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15302272 # Total number of read requests seen
system.physmem.writeReqs 824084 # Total number of write requests seen
system.physmem.cpureqs 244248 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 979345408 # Total number of bytes read from memory
system.physmem.bytesWritten 52741376 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 131565412 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 7304336 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 446 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 14097 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 956408 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 956129 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 956336 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 956715 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 957144 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 956669 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 956165 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 955908 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 956711 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 956880 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 955935 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 955453 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 956251 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 956326 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 956540 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 956256 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 49946 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 49763 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 51937 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 52171 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 52441 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 51960 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 51720 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 51713 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 51876 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 52086 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 51258 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 50919 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 51540 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 51490 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 51756 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 51508 # Track writes on a per bank basis
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.numWrRetry 32582 # Number of times wr buffer was full causing retry
system.physmem.totGap 2613795718500 # Total gap between requests
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 105 # Categorize read packet sizes
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.readPktSize::3 15138816 # Categorize read packet sizes
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.readPktSize::6 163351 # Categorize read packet sizes
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.writePktSize::2 757284 # Categorize write packet sizes
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.writePktSize::6 66800 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 1071823 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1000587 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 1004460 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 3729147 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2791599 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2788638 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2744704 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 17899 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 15634 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 28056 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 40361 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 27838 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 10343 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 10275 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 13794 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 6509 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 126 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 19 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 6 # What read queue length does an incoming req see
stats: Update stats for ldr_ret_uop (changeset 35198406dd72) This patch merely bumps the stats to match the changes introduced in changeset 35198406dd72.
2013-04-19 15:04:42 +02:00
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.wrQLenPdf::0 2919 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 2991 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 3038 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 3106 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 3132 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 3153 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 3186 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 3211 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 3225 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 35830 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 35830 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 35830 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 35830 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 35830 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 35830 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 35830 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 35830 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 35829 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 35829 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 35829 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 35829 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 35829 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 35829 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 32911 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 32839 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 32792 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 32724 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 32698 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 32677 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 32644 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 32619 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 32605 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 48021 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 21491.760022 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 1412.636943 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 31347.507834 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-95 10706 22.29% 22.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-159 4255 8.86% 31.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-223 2654 5.53% 36.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-287 2034 4.24% 40.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-351 1364 2.84% 43.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-415 1232 2.57% 46.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-479 971 2.02% 48.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-543 916 1.91% 50.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-607 629 1.31% 51.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-671 621 1.29% 52.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-735 497 1.03% 53.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-799 447 0.93% 54.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-863 308 0.64% 55.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-927 288 0.60% 56.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-991 206 0.43% 56.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1055 291 0.61% 57.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1119 124 0.26% 57.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1183 166 0.35% 57.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1247 102 0.21% 57.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1311 142 0.30% 58.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1375 76 0.16% 58.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1439 430 0.90% 59.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1503 2116 4.41% 63.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1567 511 1.06% 64.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1631 96 0.20% 64.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1695 187 0.39% 65.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1759 61 0.13% 65.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1823 129 0.27% 65.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1887 42 0.09% 65.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1951 82 0.17% 65.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-2015 32 0.07% 66.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2079 81 0.17% 66.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2143 30 0.06% 66.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2207 40 0.08% 66.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2271 20 0.04% 66.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2335 38 0.08% 66.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2399 8 0.02% 66.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2463 24 0.05% 66.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2527 13 0.03% 66.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2591 21 0.04% 66.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2655 4 0.01% 66.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2719 15 0.03% 66.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2783 7 0.01% 66.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2847 25 0.05% 66.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2911 10 0.02% 66.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2975 14 0.03% 66.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3039 5 0.01% 66.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3103 16 0.03% 66.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3167 3 0.01% 66.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3231 10 0.02% 66.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3295 6 0.01% 66.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3359 12 0.02% 66.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3423 3 0.01% 66.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3487 12 0.02% 66.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3551 7 0.01% 66.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3615 8 0.02% 66.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3679 5 0.01% 66.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3743 6 0.01% 66.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3807 4 0.01% 66.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3871 10 0.02% 67.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3935 8 0.02% 67.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3999 9 0.02% 67.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4063 7 0.01% 67.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4127 36 0.07% 67.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4191 3 0.01% 67.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4255 8 0.02% 67.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4319 3 0.01% 67.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4383 8 0.02% 67.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4447 1 0.00% 67.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4511 7 0.01% 67.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4575 4 0.01% 67.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4703 1 0.00% 67.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4767 1 0.00% 67.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4831 5 0.01% 67.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4895 4 0.01% 67.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4959 2 0.00% 67.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-5023 3 0.01% 67.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5087 3 0.01% 67.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5151 10 0.02% 67.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5215 3 0.01% 67.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5279 3 0.01% 67.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5343 2 0.00% 67.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5407 1 0.00% 67.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5471 1 0.00% 67.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5535 2 0.00% 67.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5599 3 0.01% 67.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5663 4 0.01% 67.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5791 2 0.00% 67.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5919 5 0.01% 67.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5983 2 0.00% 67.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6047 1 0.00% 67.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6111 1 0.00% 67.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6175 7 0.01% 67.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6239 1 0.00% 67.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6303 4 0.01% 67.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336-6367 2 0.00% 67.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6431 2 0.00% 67.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6495 1 0.00% 67.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6559 3 0.01% 67.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6687 1 0.00% 67.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6751 2 0.00% 67.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6815 13 0.03% 67.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6879 2 0.00% 67.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6943 6 0.01% 67.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-7007 1 0.00% 67.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7071 3 0.01% 67.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7199 5 0.01% 67.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7232-7263 3 0.01% 67.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7455 2 0.00% 67.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7583 6 0.01% 67.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7647 1 0.00% 67.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7711 4 0.01% 67.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7744-7775 1 0.00% 67.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7839 4 0.01% 67.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7903 3 0.01% 67.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7967 6 0.01% 67.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8031 1 0.00% 67.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8095 6 0.01% 67.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8159 4 0.01% 67.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8223 320 0.67% 68.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8448-8479 2 0.00% 68.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8704-8735 3 0.01% 68.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8960-8991 2 0.00% 68.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9408-9439 1 0.00% 68.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9472-9503 3 0.01% 68.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9728-9759 1 0.00% 68.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9920-9951 1 0.00% 68.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10240-10271 16 0.03% 68.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10432-10463 1 0.00% 68.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10752-10783 1 0.00% 68.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11264-11295 4 0.01% 68.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11328-11359 1 0.00% 68.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11520-11551 1 0.00% 68.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11776-11807 1 0.00% 68.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12288-12319 1 0.00% 68.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12544-12575 1 0.00% 68.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12864-12895 1 0.00% 68.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12928-12959 1 0.00% 68.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13056-13087 1 0.00% 68.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13312-13343 2 0.00% 68.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13824-13855 1 0.00% 68.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14080-14111 1 0.00% 68.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14336-14367 1 0.00% 68.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14592-14623 2 0.00% 68.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14848-14879 2 0.00% 68.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15168-15199 1 0.00% 68.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15391 2 0.00% 68.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15424-15455 1 0.00% 68.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16128-16159 2 0.00% 68.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16415 2 0.00% 68.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16640-16671 1 0.00% 68.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16896-16927 2 0.00% 68.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17152-17183 1 0.00% 68.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17216-17247 1 0.00% 68.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17408-17439 1 0.00% 68.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17792-17823 1 0.00% 68.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17856-17887 1 0.00% 68.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17920-17951 1 0.00% 68.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18432-18463 1 0.00% 68.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18688-18719 1 0.00% 68.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19072-19103 1 0.00% 68.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19200-19231 1 0.00% 68.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19456-19487 3 0.01% 68.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19968-19999 1 0.00% 68.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20224-20255 1 0.00% 68.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20480-20511 15 0.03% 68.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20608-20639 1 0.00% 68.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21504-21535 4 0.01% 68.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22272-22303 2 0.00% 68.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22528-22559 1 0.00% 68.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22784-22815 3 0.01% 68.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23040-23071 3 0.01% 68.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23360-23391 1 0.00% 68.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23552-23583 3 0.01% 68.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23872-23903 1 0.00% 68.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24064-24095 2 0.00% 68.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24320-24351 1 0.00% 68.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24576-24607 3 0.01% 68.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24832-24863 2 0.00% 68.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25088-25119 1 0.00% 68.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25600-25631 2 0.00% 68.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25856-25887 1 0.00% 68.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25920-25951 1 0.00% 68.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26112-26143 2 0.00% 68.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26368-26399 2 0.00% 68.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26624-26655 2 0.00% 68.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27136-27167 1 0.00% 68.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27392-27423 2 0.00% 68.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27584-27615 1 0.00% 68.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27648-27679 3 0.01% 68.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27904-27935 1 0.00% 68.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28160-28191 1 0.00% 68.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28416-28447 1 0.00% 68.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28672-28703 2 0.00% 68.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28928-28959 4 0.01% 68.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29184-29215 1 0.00% 68.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29440-29471 2 0.00% 68.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29952-29983 1 0.00% 68.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30208-30239 2 0.00% 68.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30720-30751 7 0.01% 68.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31232-31263 1 0.00% 68.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31488-31519 1 0.00% 68.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31744-31775 3 0.01% 68.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32256-32287 1 0.00% 68.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32512-32543 3 0.01% 68.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33024-33055 3 0.01% 68.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33280-33311 2 0.00% 68.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33728-33759 1 0.00% 68.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33792-33823 55 0.11% 68.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33984-34015 1 0.00% 68.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34048-34079 1 0.00% 68.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34816-34847 2 0.00% 68.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35328-35359 1 0.00% 68.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35840-35871 1 0.00% 68.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35968-35999 1 0.00% 68.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36096-36127 2 0.00% 68.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36480-36511 1 0.00% 68.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36608-36639 1 0.00% 68.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38144-38175 1 0.00% 68.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39168-39199 1 0.00% 68.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39232-39263 1 0.00% 68.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39616-39647 1 0.00% 68.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40384-40415 1 0.00% 68.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41216-41247 2 0.00% 68.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41984-42015 2 0.00% 68.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42240-42271 1 0.00% 68.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42688-42719 1 0.00% 68.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42752-42783 1 0.00% 68.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43008-43039 1 0.00% 68.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44032-44063 3 0.01% 68.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44416-44447 1 0.00% 68.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44672-44703 1 0.00% 68.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46592-46623 1 0.00% 68.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46912-46943 1 0.00% 68.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46976-47007 1 0.00% 68.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48640-48671 1 0.00% 68.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48896-48927 1 0.00% 68.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49408-49439 2 0.00% 68.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50688-50719 1 0.00% 68.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50880-50911 1 0.00% 68.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51200-51231 2 0.00% 68.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::52224-52255 2 0.00% 68.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::52608-52639 1 0.00% 68.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::53248-53279 1 0.00% 68.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::54784-54815 1 0.00% 68.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::55296-55327 1 0.00% 68.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::55616-55647 1 0.00% 68.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::56064-56095 1 0.00% 68.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::56832-56863 1 0.00% 68.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::57088-57119 2 0.00% 68.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::58112-58143 1 0.00% 68.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::59584-59615 1 0.00% 68.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::59648-59679 1 0.00% 68.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::59840-59871 1 0.00% 68.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::60416-60447 1 0.00% 68.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::61184-61215 1 0.00% 68.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::61568-61599 1 0.00% 68.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::61952-61983 1 0.00% 68.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::62976-63007 1 0.00% 68.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::63488-63519 1 0.00% 68.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::64064-64095 1 0.00% 68.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::64512-64543 1 0.00% 68.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65024-65055 25 0.05% 68.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65088-65119 6 0.01% 68.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65152-65183 7 0.01% 68.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65280-65311 19 0.04% 68.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65408-65439 7 0.01% 68.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65472-65503 18 0.04% 68.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65536-65567 14562 30.32% 99.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::97536-97567 1 0.00% 99.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::103680-103711 1 0.00% 99.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::129664-129695 1 0.00% 99.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::130176-130207 1 0.00% 99.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::130624-130655 1 0.00% 99.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::130688-130719 1 0.00% 99.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::131072-131103 321 0.67% 99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::131328-131359 1 0.00% 99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::132096-132127 2 0.00% 99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::140032-140063 1 0.00% 99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::160768-160799 1 0.00% 99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::162560-162591 1 0.00% 99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::169728-169759 1 0.00% 99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::182528-182559 1 0.00% 99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::196608-196639 8 0.02% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 48021 # Bytes accessed per row activation
system.physmem.totQLat 359781455750 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 452374882000 # Sum of mem lat for all requests
system.physmem.totBusLat 76509130000 # Total cycles spent in databus access
system.physmem.totBankLat 16084296250 # Total cycles spent in bank access
system.physmem.avgQLat 23512.32 # Average queueing delay per request
system.physmem.avgBankLat 1051.14 # Average bank access latency per request
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per request
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.avgMemAccLat 29563.46 # Average memory access latency
system.physmem.avgRdBW 374.68 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 20.18 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 50.33 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 2.79 # Average consumed write bandwidth in MB/s
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.busUtil 3.08 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.17 # Average read queue length over time
system.physmem.avgWrQLen 13.40 # Average write queue length over time
system.physmem.readRowHits 15272830 # Number of row buffer hits during reads
system.physmem.writeRowHits 805042 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.81 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 97.69 # Row buffer hit rate for writes
system.physmem.avgGap 162082.23 # Average gap between requests
stats: Update stats for ldr_ret_uop (changeset 35198406dd72) This patch merely bumps the stats to match the changes introduced in changeset 35198406dd72.
2013-04-19 15:04:42 +02:00
system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.realview.nvmem.bw_read::cpu0.inst 24 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 147 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 171 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 24 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 147 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 171 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 24 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 171 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 54057191 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 16352590 # Transaction distribution
system.membus.trans_dist::ReadResp 16352590 # Transaction distribution
system.membus.trans_dist::WriteReq 769166 # Transaction distribution
system.membus.trans_dist::WriteResp 769166 # Transaction distribution
system.membus.trans_dist::Writeback 66800 # Transaction distribution
system.membus.trans_dist::UpgradeReq 35679 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 18283 # Transaction distribution
system.membus.trans_dist::UpgradeResp 14097 # Transaction distribution
system.membus.trans_dist::ReadExReq 138270 # Transaction distribution
system.membus.trans_dist::ReadExResp 137887 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384276 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1976722 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13830 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2050 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 4376896 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.bridge.slave 2384276 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.physmem.port 32254354 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.realview.gic.pio 13830 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.realview.local_cpu_timer.pio 2050 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 34654528 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2392552 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17759220 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 27660 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4100 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total 20183988 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.bridge.slave 2392552 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.physmem.port 138869748 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.realview.gic.pio 27660 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.realview.local_cpu_timer.pio 4100 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 141294516 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 141294516 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 1493240500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 17657749750 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.7 # Layer utilization (%)
system.membus.reqLayer3.occupancy 11792000 # Layer occupancy (ticks)
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 3000 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer6.occupancy 1805500 # Layer occupancy (ticks)
system.membus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 4833822840 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.respLayer2.occupancy 34180950731 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
system.l2c.replacements 73069 # number of replacements
system.l2c.tagsinuse 53059.477869 # Cycle average of tags in use
system.l2c.total_refs 1873536 # Total number of references to valid blocks.
system.l2c.sampled_refs 138222 # Sample count of references to valid blocks.
system.l2c.avg_refs 13.554543 # Average number of references to valid blocks.
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.occ_blocks::writebacks 37743.094868 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker 4.500926 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker 0.000358 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst 4196.922721 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data 2968.415869 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.dtb.walker 13.090066 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 4030.052193 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 4103.400867 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.575914 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker 0.000069 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst 0.064040 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.045294 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.dtb.walker 0.000200 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst 0.061494 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.062613 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.809623 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker 23020 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 4625 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 393598 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 165506 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 32735 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 5728 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 607995 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 201851 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1435058 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 583280 # number of Writeback hits
system.l2c.Writeback_hits::total 583280 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 1128 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 710 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 1838 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 204 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 170 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 374 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 48355 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 58837 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 107192 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 23020 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 4625 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 393598 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 213861 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 32735 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 5728 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 607995 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 260688 # number of demand (read+write) hits
system.l2c.demand_hits::total 1542250 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 23020 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 4625 # number of overall hits
system.l2c.overall_hits::cpu0.inst 393598 # number of overall hits
system.l2c.overall_hits::cpu0.data 213861 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 32735 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 5728 # number of overall hits
system.l2c.overall_hits::cpu1.inst 607995 # number of overall hits
system.l2c.overall_hits::cpu1.data 260688 # number of overall hits
system.l2c.overall_hits::total 1542250 # number of overall hits
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.ReadReq_misses::cpu0.dtb.walker 11 # number of ReadReq misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 6054 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 6310 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 18 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 6631 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 6355 # number of ReadReq misses
system.l2c.ReadReq_misses::total 25381 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 5662 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 4388 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 10050 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 778 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 584 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 1362 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 63189 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 77383 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 140572 # number of ReadExReq misses
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.demand_misses::cpu0.dtb.walker 11 # number of demand (read+write) misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 6054 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 69499 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 18 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 6631 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 83738 # number of demand (read+write) misses
system.l2c.demand_misses::total 165953 # number of demand (read+write) misses
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.overall_misses::cpu0.dtb.walker 11 # number of overall misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
system.l2c.overall_misses::cpu0.inst 6054 # number of overall misses
system.l2c.overall_misses::cpu0.data 69499 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 18 # number of overall misses
system.l2c.overall_misses::cpu1.inst 6631 # number of overall misses
system.l2c.overall_misses::cpu1.data 83738 # number of overall misses
system.l2c.overall_misses::total 165953 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 893500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 130000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst 442819000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 463768995 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1533000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 510371500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 502747498 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 1922263493 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 8736481 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 12073999 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 20810480 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 590500 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2936498 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 3526998 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 4241001492 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 5519329996 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 9760331488 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 893500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 130000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 442819000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 4704770487 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 1533000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 510371500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 6022077494 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 11682594981 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 893500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 130000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 442819000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 4704770487 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 1533000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 510371500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 6022077494 # number of overall miss cycles
system.l2c.overall_miss_latency::total 11682594981 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 23031 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 4627 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 399652 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 171816 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 32753 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 5728 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 614626 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 208206 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1460439 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 583280 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 583280 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 6790 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 5098 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 11888 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 982 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 754 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 1736 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 111544 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 136220 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 247764 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 23031 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 4627 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 399652 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 283360 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 32753 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 5728 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 614626 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 344426 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1708203 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 23031 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 4627 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 399652 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 283360 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 32753 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 5728 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 614626 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 344426 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1708203 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000478 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000432 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.015148 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.036725 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000550 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.010789 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.030523 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.017379 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.833873 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.860730 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.845390 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.792261 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.774536 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.784562 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.566494 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.568074 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.567362 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000478 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000432 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.015148 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.245268 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000550 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.010789 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.243123 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.097151 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000478 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000432 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.015148 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.245268 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000550 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.010789 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.243123 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.097151 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 81227.272727 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 65000 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 73144.862901 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 73497.463550 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 85166.666667 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 76967.501131 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 79110.542565 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 75736.318230 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1543.002649 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2751.595032 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 2070.694527 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 758.997429 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5028.250000 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 2589.572687 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 67116.135593 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71324.838737 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 69432.970207 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 81227.272727 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 65000 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 73144.862901 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 67695.513417 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 85166.666667 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 76967.501131 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 71915.707254 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 70397.009882 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 81227.272727 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 65000 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 73144.862901 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 67695.513417 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 85166.666667 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 76967.501131 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 71915.707254 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 70397.009882 # average overall miss latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.writebacks::writebacks 66800 # number of writebacks
system.l2c.writebacks::total 66800 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst 3 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data 40 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data 27 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data 40 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data 27 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 78 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data 40 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data 27 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 78 # number of overall MSHR hits
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 11 # number of ReadReq MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst 6051 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 6270 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 18 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst 6623 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 6328 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 25303 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 5662 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 4388 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 10050 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 778 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 584 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 1362 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 63189 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 77383 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 140572 # number of ReadExReq MSHR misses
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.demand_mshr_misses::cpu0.dtb.walker 11 # number of demand (read+write) MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 6051 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 69459 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 18 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 6623 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 83711 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 165875 # number of demand (read+write) MSHR misses
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.overall_mshr_misses::cpu0.dtb.walker 11 # number of overall MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 6051 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 69459 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 18 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 6623 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 83711 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 165875 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 756250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 105750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 367361750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 383110245 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1310500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 427493250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 422235748 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 1602373493 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 56779102 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 44007360 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 100786462 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7817273 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 5858578 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 13675851 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3454122942 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4550846228 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 8004969170 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 756250 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 105750 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 367361750 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 3837233187 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1310500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 427493250 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 4973081976 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 9607342663 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 756250 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 105750 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 367361750 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 3837233187 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1310500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 427493250 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 4973081976 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 9607342663 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 7164750 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12331011486 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2446749 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154885786239 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 167226409224 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1118932750 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 25567445102 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 26686377852 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 7164750 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13449944236 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2446749 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 180453231341 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 193912787076 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000478 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000432 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015141 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036493 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000550 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010776 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030393 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.017326 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.833873 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.860730 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.845390 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.792261 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.774536 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.784562 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.566494 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.568074 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.567362 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000478 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000432 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015141 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.245126 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000550 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010776 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.243045 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.097105 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000478 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000432 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015141 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.245126 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000550 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010776 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.243045 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.097105 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 68750 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60710.915551 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61102.112440 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 72805.555556 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64546.768836 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66724.991783 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 63327.411493 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10028.099965 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10029.024613 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10028.503682 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10047.908740 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10031.811644 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10041.006608 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54663.358211 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58809.379683 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 56945.687406 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 68750 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60710.915551 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55244.578629 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 72805.555556 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64546.768836 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59407.747799 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 57919.172045 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 68750 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60710.915551 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55244.578629 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 72805.555556 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64546.768836 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59407.747799 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 57919.172045 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.throughput 58542991 # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq 2739841 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2739840 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 769166 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 769166 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 583280 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 34832 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 18657 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 53489 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 259511 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 259511 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 800088 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 1073172 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 13793 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 57051 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 1229933 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 4820895 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma 15468 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma 74350 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count 8084750 # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 25585472 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 34695904 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 18508 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 92124 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 39339008 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 48266196 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma 22912 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma 131012 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size 148151136 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus 148151136 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 4868352 # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy 4921338984 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 1802175919 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 1506283904 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 9191448 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 34164696 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy 2769642515 # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer5.occupancy 3249270250 # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy 9767440 # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy 41898883 # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.throughput 47250451 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 16322888 # Transaction distribution
system.iobus.trans_dist::ReadResp 16322888 # Transaction distribution
system.iobus.trans_dist::WriteReq 8066 # Transaction distribution
system.iobus.trans_dist::WriteResp 8066 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30842 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8848 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1032 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 736 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 2384276 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart.pio 30842 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.realview_io.pio 8848 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.timer1.pio 1032 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.kmi1.pio 736 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 32661908 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40560 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 17696 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 392 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total 2392552 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart.pio 40560 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.realview_io.pio 17696 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.kmi1.pio 392 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 123503080 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 123503080 # Total data (bytes)
system.iobus.reqLayer0.occupancy 21645000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 4430000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 522000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 440000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
system.iobus.respLayer0.occupancy 2376210000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
system.iobus.respLayer1.occupancy 30277632000 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 1.2 # Layer utilization (%)
system.cpu0.branchPred.lookups 6073314 # Number of BP lookups
system.cpu0.branchPred.condPredicted 4627623 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 295826 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 3795187 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 2949225 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.branchPred.BTBHitPct 77.709610 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 683153 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 28183 # Number of incorrect RAS predictions.
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dtb.read_hits 8970256 # DTB read hits
system.cpu0.dtb.read_misses 29375 # DTB read misses
system.cpu0.dtb.write_hits 5214738 # DTB write hits
system.cpu0.dtb.write_misses 5731 # DTB write misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dtb.flush_entries 1812 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 1038 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 270 # Number of TLB faults due to prefetch
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dtb.perms_faults 591 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 8999631 # DTB read accesses
system.cpu0.dtb.write_accesses 5220469 # DTB write accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dtb.hits 14184994 # DTB hits
system.cpu0.dtb.misses 35106 # DTB misses
system.cpu0.dtb.accesses 14220100 # DTB accesses
system.cpu0.itb.inst_hits 4276462 # ITB inst hits
system.cpu0.itb.inst_misses 5070 # ITB inst misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.itb.flush_entries 1351 # Number of entries that have been flushed from TLB
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.itb.perms_faults 1356 # Number of TLB faults due to permissions restrictions
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.itb.inst_accesses 4281532 # ITB inst accesses
system.cpu0.itb.hits 4276462 # DTB hits
system.cpu0.itb.misses 5070 # DTB misses
system.cpu0.itb.accesses 4281532 # DTB accesses
system.cpu0.numCycles 69613456 # number of cpu cycles simulated
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.fetch.icacheStallCycles 11926468 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 32461716 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 6073314 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 3632378 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 7613392 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 1460130 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 63151 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.BlockedCycles 20074417 # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles 5834 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 46093 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 1371911 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 309 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 4274981 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 157877 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 2111 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 42149460 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 0.995068 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 2.376418 # Number of instructions fetched each cycle (Total)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.fetch.rateDist::0 34543319 81.95% 81.95% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 572779 1.36% 83.31% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 825233 1.96% 85.27% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 684006 1.62% 86.89% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 778589 1.85% 88.74% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5 565339 1.34% 90.08% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 679715 1.61% 91.70% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 356870 0.85% 92.54% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 3143610 7.46% 100.00% # Number of instructions fetched each cycle (Total)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.fetch.rateDist::total 42149460 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.087243 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.466314 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 12452855 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 21284567 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 6905227 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 522550 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 984261 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 948796 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 64785 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 40574738 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 212216 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 984261 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 13028707 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 5941224 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 13201317 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 6800913 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 2193038 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 39456506 # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents 1875 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 442978 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents 1248488 # Number of times rename has blocked due to LSQ full
system.cpu0.rename.FullRegisterEvents 66 # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands 39834265 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 178291734 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 178257443 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 34291 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 31450110 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 8384154 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 420012 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 376763 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 5452877 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 7762434 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 5776236 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 1132872 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 1233884 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 37360552 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 904892 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 37716432 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 82271 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 6323448 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 13282471 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 257104 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 42149460 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.894826 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.507768 # Number of insts issued each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.iq.issued_per_cycle::0 26809075 63.60% 63.60% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 5821539 13.81% 77.42% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 3209963 7.62% 85.03% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 2497911 5.93% 90.96% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 2123670 5.04% 96.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 939017 2.23% 98.22% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 502938 1.19% 99.42% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 188935 0.45% 99.87% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 56412 0.13% 100.00% # Number of insts issued each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.iq.issued_per_cycle::total 42149460 # Number of insts issued each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.iq.fu_full::IntAlu 27471 2.55% 2.55% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 463 0.04% 2.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 839894 78.10% 80.70% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 207538 19.30% 100.00% # attempts to use FU when none available
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.iq.FU_type_0::No_OpClass 52344 0.14% 0.14% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 22648900 60.05% 60.19% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 47937 0.13% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 12 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.32% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 9431477 25.01% 85.32% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 5535066 14.68% 100.00% # Type of FU issued
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.iq.FU_type_0::total 37716432 # Type of FU issued
system.cpu0.iq.rate 0.541798 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 1075366 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.028512 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 118766388 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 44596758 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 34851054 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 8389 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 4662 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 3872 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 38735073 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 4381 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 316422 # Number of loads that had data forwarded from stores
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.iew.lsq.thread0.squashedLoads 1379018 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 2578 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 13049 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 541624 # Number of stores squashed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.iew.lsq.thread0.rescheduledLoads 2149592 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 6129 # Number of times an access to memory failed due to the cache being blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.iew.iewSquashCycles 984261 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 4297602 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 105996 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 38383622 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 87186 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 7762434 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 5776236 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 577553 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 40750 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 2975 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 13049 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 150118 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 117853 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 267971 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 37335026 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 9287293 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 381406 # Number of squashed instructions skipped in execute
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iew.exec_swp 0 # number of swp insts executed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.iew.exec_nop 118178 # number of nop insts executed
system.cpu0.iew.exec_refs 14774953 # number of memory reference insts executed
system.cpu0.iew.exec_branches 4916788 # Number of branches executed
system.cpu0.iew.exec_stores 5487660 # Number of stores executed
system.cpu0.iew.exec_rate 0.536319 # Inst execution rate
system.cpu0.iew.wb_sent 37140556 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 34854926 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 18563816 # num instructions producing a value
system.cpu0.iew.wb_consumers 35689656 # num instructions consuming a value
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.iew.wb_rate 0.500692 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.520146 # average fanout of values written-back
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.commit.commitSquashedInsts 6130188 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 647788 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 232202 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 41165199 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.772263 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.733134 # Number of insts commited each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.commit.committed_per_cycle::0 29286812 71.14% 71.14% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 5810011 14.11% 85.26% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 1968218 4.78% 90.04% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 996844 2.42% 92.46% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 804428 1.95% 94.42% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 515457 1.25% 95.67% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 392582 0.95% 96.62% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 223885 0.54% 97.17% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 1166962 2.83% 100.00% # Number of insts commited each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.commit.committed_per_cycle::total 41165199 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 24069809 # Number of instructions committed
system.cpu0.commit.committedOps 31790359 # Number of ops (including micro ops) committed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.commit.refs 11618028 # Number of memory references committed
system.cpu0.commit.loads 6383416 # Number of loads committed
system.cpu0.commit.membars 231880 # Number of memory barriers committed
system.cpu0.commit.branches 4307208 # Number of branches committed
ARM: update stats for bp and squash fixes.
2012-09-25 18:49:41 +02:00
system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.commit.int_insts 28099612 # Number of committed integer instructions.
system.cpu0.commit.function_calls 498731 # Number of function calls committed.
system.cpu0.commit.bw_lim_events 1166962 # number cycles where commit BW limit reached
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.rob.rob_reads 77052413 # The number of ROB reads
system.cpu0.rob.rob_writes 76827079 # The number of ROB writes
system.cpu0.timesIdled 370271 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 27463996 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 5157937915 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 23989067 # Number of Instructions Simulated
system.cpu0.committedOps 31709617 # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total 23989067 # Number of Instructions Simulated
system.cpu0.cpi 2.901883 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 2.901883 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.344604 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.344604 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 174143996 # number of integer regfile reads
system.cpu0.int_regfile_writes 34604534 # number of integer regfile writes
system.cpu0.fp_regfile_reads 3264 # number of floating regfile reads
system.cpu0.fp_regfile_writes 896 # number of floating regfile writes
system.cpu0.misc_regfile_reads 13203658 # number of misc regfile reads
system.cpu0.misc_regfile_writes 457594 # number of misc regfile writes
system.cpu0.icache.replacements 399659 # number of replacements
system.cpu0.icache.tagsinuse 511.575445 # Cycle average of tags in use
system.cpu0.icache.total_refs 3842942 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 400171 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 9.603250 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 6980726000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst 511.575445 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.999171 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.999171 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 3842942 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 3842942 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 3842942 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 3842942 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 3842942 # number of overall hits
system.cpu0.icache.overall_hits::total 3842942 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 431911 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 431911 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 431911 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 431911 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 431911 # number of overall misses
system.cpu0.icache.overall_misses::total 431911 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5969636493 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 5969636493 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 5969636493 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 5969636493 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 5969636493 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 5969636493 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 4274853 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 4274853 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 4274853 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 4274853 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 4274853 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 4274853 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.101035 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.101035 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.101035 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.101035 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.101035 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.101035 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13821.450468 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13821.450468 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13821.450468 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13821.450468 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13821.450468 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13821.450468 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 3644 # number of cycles access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.icache.blocked::no_mshrs 174 # number of cycles access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.942529 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31718 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 31718 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 31718 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 31718 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 31718 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 31718 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 400193 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 400193 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 400193 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 400193 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 400193 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 400193 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4864756575 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 4864756575 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4864756575 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 4864756575 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4864756575 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 4864756575 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9682500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 9682500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 9682500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 9682500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093616 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093616 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093616 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.093616 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093616 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.093616 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12156.026155 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12156.026155 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12156.026155 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12156.026155 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12156.026155 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12156.026155 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.replacements 275313 # number of replacements
system.cpu0.dcache.tagsinuse 479.702966 # Cycle average of tags in use
system.cpu0.dcache.total_refs 9426114 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 275825 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 34.174255 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 49336000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data 479.702966 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.936920 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.936920 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 5876643 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 5876643 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 3228072 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 3228072 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139641 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 139641 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137200 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 137200 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 9104715 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 9104715 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 9104715 # number of overall hits
system.cpu0.dcache.overall_hits::total 9104715 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 392586 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 392586 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1585207 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 1585207 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8832 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 8832 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7754 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 7754 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 1977793 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 1977793 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 1977793 # number of overall misses
system.cpu0.dcache.overall_misses::total 1977793 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5514730000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 5514730000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 76877974883 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 76877974883 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 89351500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 89351500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 49685500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 49685500 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 82392704883 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 82392704883 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 82392704883 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 82392704883 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 6269229 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 6269229 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 4813279 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 4813279 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 148473 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 148473 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144954 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 144954 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 11082508 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 11082508 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 11082508 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 11082508 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062621 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.062621 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.329340 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.329340 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059486 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059486 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053493 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053493 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178461 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.178461 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178461 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.178461 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14047.189660 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14047.189660 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 48497.120492 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 48497.120492 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10116.791214 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10116.791214 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6407.725045 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6407.725045 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 41658.912173 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 41658.912173 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41658.912173 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 41658.912173 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 10507 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 10018 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 605 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 134 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.366942 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 74.761194 # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.writebacks::writebacks 255296 # number of writebacks
system.cpu0.dcache.writebacks::total 255296 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203565 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 203565 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1454109 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 1454109 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 475 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 475 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657674 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 1657674 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657674 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 1657674 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189021 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 189021 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131098 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 131098 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8357 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8357 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7751 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 7751 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 320119 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 320119 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 320119 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 320119 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2392342380 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2392342380 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5118910660 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5118910660 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 67659513 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 67659513 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34183001 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34183001 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7511253040 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 7511253040 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7511253040 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 7511253040 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13429863028 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13429863028 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1251424879 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1251424879 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14681287907 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14681287907 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030151 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030151 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027237 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027237 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056286 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056286 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053472 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053472 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028885 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.028885 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028885 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.028885 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12656.489914 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12656.489914 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39046.443577 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39046.443577 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8096.148498 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8096.148498 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4410.140756 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4410.140756 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23463.940097 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23463.940097 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23463.940097 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23463.940097 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.branchPred.lookups 9253585 # Number of BP lookups
system.cpu1.branchPred.condPredicted 7592303 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 416171 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 6192388 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 5325484 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.branchPred.BTBHitPct 86.000490 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 798470 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 43798 # Number of incorrect RAS predictions.
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.dtb.read_hits 43179554 # DTB read hits
system.cpu1.dtb.read_misses 37431 # DTB read misses
system.cpu1.dtb.write_hits 6972554 # DTB write hits
system.cpu1.dtb.write_misses 10848 # DTB write misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.dtb.flush_entries 2005 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 2926 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 258 # Number of TLB faults due to prefetch
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.dtb.perms_faults 669 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 43216985 # DTB read accesses
system.cpu1.dtb.write_accesses 6983402 # DTB write accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.dtb.hits 50152108 # DTB hits
system.cpu1.dtb.misses 48279 # DTB misses
system.cpu1.dtb.accesses 50200387 # DTB accesses
system.cpu1.itb.inst_hits 8467709 # ITB inst hits
system.cpu1.itb.inst_misses 5542 # ITB inst misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.itb.flush_entries 1527 # Number of entries that have been flushed from TLB
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.itb.perms_faults 1492 # Number of TLB faults due to permissions restrictions
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.itb.inst_accesses 8473251 # ITB inst accesses
system.cpu1.itb.hits 8467709 # DTB hits
system.cpu1.itb.misses 5542 # DTB misses
system.cpu1.itb.accesses 8473251 # DTB accesses
system.cpu1.numCycles 412553366 # number of cpu cycles simulated
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.fetch.icacheStallCycles 20142179 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 67124404 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 9253585 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 6123954 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 14367636 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 3996679 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 69030 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.BlockedCycles 77666254 # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles 5814 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles 41513 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 1490350 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 198 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 8465907 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 710561 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 2899 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 116503477 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 0.698188 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.043258 # Number of instructions fetched each cycle (Total)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.fetch.rateDist::0 102143196 87.67% 87.67% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 814134 0.70% 88.37% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 962782 0.83% 89.20% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 1912655 1.64% 90.84% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 1508621 1.29% 92.14% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 586161 0.50% 92.64% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 2143967 1.84% 94.48% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 421141 0.36% 94.84% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 6010820 5.16% 100.00% # Number of instructions fetched each cycle (Total)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.fetch.rateDist::total 116503477 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.022430 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.162705 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 21695015 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 78657608 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 12988209 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 540911 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 2621734 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 1137928 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 100371 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 76331637 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 334218 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 2621734 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 23056356 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 33279261 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 41089956 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 12073504 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 4382666 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 71129037 # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents 18835 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 684998 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents 3107715 # Number of times rename has blocked due to LSQ full
system.cpu1.rename.FullRegisterEvents 374 # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands 75211284 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 327489941 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 327430919 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 59022 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 50108296 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 25102988 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 461152 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 401338 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 8025308 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 13414582 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 8304810 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 1056481 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 1432553 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 64611179 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 1174620 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 90302569 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 94169 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 16313013 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 45540722 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 275640 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 116503477 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.775106 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.513735 # Number of insts issued each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.iq.issued_per_cycle::0 85607171 73.48% 73.48% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 8609069 7.39% 80.87% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 4398916 3.78% 84.65% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 3887525 3.34% 87.98% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 10612061 9.11% 97.09% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 1964931 1.69% 98.78% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 1085414 0.93% 99.71% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 259410 0.22% 99.93% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 78980 0.07% 100.00% # Number of insts issued each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.iq.issued_per_cycle::total 116503477 # Number of insts issued each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.iq.fu_full::IntAlu 32357 0.41% 0.41% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 996 0.01% 0.42% # attempts to use FU when none available
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.iq.fu_full::MemRead 7572484 95.70% 96.12% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 307046 3.88% 100.00% # attempts to use FU when none available
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: Update stats to reflect bus retry changes This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
2013-03-26 19:46:49 +01:00
system.cpu1.iq.FU_type_0::No_OpClass 313932 0.35% 0.35% # Type of FU issued
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.iq.FU_type_0::IntAlu 38359652 42.48% 42.83% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 61197 0.07% 42.89% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.89% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.89% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.89% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.89% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.89% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.89% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.89% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.89% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.89% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.89% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.89% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.89% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 14 0.00% 42.89% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.89% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.89% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.89% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 42.89% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.89% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.89% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.89% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.89% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.89% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.89% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 1701 0.00% 42.90% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.90% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 42.90% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.90% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 44223929 48.97% 91.87% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 7342124 8.13% 100.00% # Type of FU issued
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.iq.FU_type_0::total 90302569 # Type of FU issued
system.cpu1.iq.rate 0.218887 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 7912883 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.087626 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 305148356 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 82107584 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 54845197 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 15407 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 8039 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 6808 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 97893314 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 8206 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 355446 # Number of loads that had data forwarded from stores
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.iew.lsq.thread0.squashedLoads 3436601 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 3841 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 17378 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 1303587 # Number of stores squashed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.iew.lsq.thread0.rescheduledLoads 31958921 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 917809 # Number of times an access to memory failed due to the cache being blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.iew.iewSquashCycles 2621734 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 25482277 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 363023 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 65889169 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 115264 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 13414582 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 8304810 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 878172 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 66494 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 3874 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 17378 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 205598 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 157346 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 362944 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 87965313 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 43561744 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 2337256 # Number of squashed instructions skipped in execute
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iew.exec_swp 0 # number of swp insts executed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.iew.exec_nop 103370 # number of nop insts executed
system.cpu1.iew.exec_refs 50840273 # number of memory reference insts executed
system.cpu1.iew.exec_branches 7156944 # Number of branches executed
system.cpu1.iew.exec_stores 7278529 # Number of stores executed
system.cpu1.iew.exec_rate 0.213222 # Inst execution rate
system.cpu1.iew.wb_sent 86983330 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 54852005 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 30529736 # num instructions producing a value
system.cpu1.iew.wb_consumers 54511543 # num instructions consuming a value
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.iew.wb_rate 0.132957 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.560060 # average fanout of values written-back
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.commit.commitSquashedInsts 16208484 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 898980 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 317402 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 113881743 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.432055 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.398122 # Number of insts commited each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.commit.committed_per_cycle::0 96739305 84.95% 84.95% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 8399776 7.38% 92.32% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 2206670 1.94% 94.26% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 1295256 1.14% 95.40% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 1289720 1.13% 96.53% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 586162 0.51% 97.05% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 954092 0.84% 97.88% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 596070 0.52% 98.41% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 1814692 1.59% 100.00% # Number of insts commited each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.commit.committed_per_cycle::total 113881743 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 38868743 # Number of instructions committed
system.cpu1.commit.committedOps 49203152 # Number of ops (including micro ops) committed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.commit.refs 16979204 # Number of memory references committed
system.cpu1.commit.loads 9977981 # Number of loads committed
system.cpu1.commit.membars 195491 # Number of memory barriers committed
system.cpu1.commit.branches 6119212 # Number of branches committed
system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 43616743 # Number of committed integer instructions.
system.cpu1.commit.function_calls 553203 # Number of function calls committed.
system.cpu1.commit.bw_lim_events 1814692 # number cycles where commit BW limit reached
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.rob.rob_reads 176412864 # The number of ROB reads
system.cpu1.rob.rob_writes 133542996 # The number of ROB writes
system.cpu1.timesIdled 1428534 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 296049889 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 4814402067 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 38799104 # Number of Instructions Simulated
system.cpu1.committedOps 49133513 # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total 38799104 # Number of Instructions Simulated
system.cpu1.cpi 10.633064 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 10.633064 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.094046 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.094046 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 393827212 # number of integer regfile reads
system.cpu1.int_regfile_writes 57409312 # number of integer regfile writes
system.cpu1.fp_regfile_reads 5077 # number of floating regfile reads
system.cpu1.fp_regfile_writes 2342 # number of floating regfile writes
system.cpu1.misc_regfile_reads 18946986 # number of misc regfile reads
system.cpu1.misc_regfile_writes 419134 # number of misc regfile writes
system.cpu1.icache.replacements 614670 # number of replacements
system.cpu1.icache.tagsinuse 498.803951 # Cycle average of tags in use
system.cpu1.icache.total_refs 7804426 # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs 615182 # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs 12.686369 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 74831061000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst 498.803951 # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst 0.974226 # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total 0.974226 # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst 7804426 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 7804426 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 7804426 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 7804426 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 7804426 # number of overall hits
system.cpu1.icache.overall_hits::total 7804426 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 661434 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 661434 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 661434 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 661434 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 661434 # number of overall misses
system.cpu1.icache.overall_misses::total 661434 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8993382992 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 8993382992 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 8993382992 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 8993382992 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 8993382992 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 8993382992 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 8465860 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 8465860 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 8465860 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 8465860 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 8465860 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 8465860 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.078130 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.078130 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.078130 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.078130 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.078130 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.078130 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13596.795738 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13596.795738 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13596.795738 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13596.795738 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13596.795738 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13596.795738 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 3054 # number of cycles access was blocked
stats: Update stats for ldr_ret_uop (changeset 35198406dd72) This patch merely bumps the stats to match the changes introduced in changeset 35198406dd72.
2013-04-19 15:04:42 +02:00
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.icache.blocked::no_mshrs 205 # number of cycles access was blocked
stats: Update stats for ldr_ret_uop (changeset 35198406dd72) This patch merely bumps the stats to match the changes introduced in changeset 35198406dd72.
2013-04-19 15:04:42 +02:00
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.897561 # average number of cycles each access was blocked
stats: Update stats for ldr_ret_uop (changeset 35198406dd72) This patch merely bumps the stats to match the changes introduced in changeset 35198406dd72.
2013-04-19 15:04:42 +02:00
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46219 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total 46219 # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst 46219 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total 46219 # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst 46219 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total 46219 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 615215 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 615215 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 615215 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 615215 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 615215 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 615215 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7348125977 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 7348125977 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7348125977 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 7348125977 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7348125977 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 7348125977 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3395500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3395500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3395500 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 3395500 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.072670 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.072670 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.072670 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.072670 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.072670 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.072670 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11943.996777 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11943.996777 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11943.996777 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11943.996777 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11943.996777 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11943.996777 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.dcache.replacements 363541 # number of replacements
system.cpu1.dcache.tagsinuse 487.194544 # Cycle average of tags in use
system.cpu1.dcache.total_refs 13012998 # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs 363907 # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs 35.759131 # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 70879256000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data 487.194544 # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data 0.951552 # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total 0.951552 # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data 8508304 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 8508304 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 4270423 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 4270423 # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 99789 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 99789 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 97069 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 97069 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 12778727 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 12778727 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 12778727 # number of overall hits
system.cpu1.dcache.overall_hits::total 12778727 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 403002 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 403002 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 1564321 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 1564321 # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14195 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 14195 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10908 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 10908 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 1967323 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 1967323 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 1967323 # number of overall misses
system.cpu1.dcache.overall_misses::total 1967323 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6229483500 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 6229483500 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 75673370015 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 75673370015 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131282500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 131282500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 57807000 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 57807000 # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 81902853515 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 81902853515 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 81902853515 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 81902853515 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 8911306 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 8911306 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 5834744 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 5834744 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 113984 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 113984 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 107977 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 107977 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 14746050 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 14746050 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 14746050 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 14746050 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045224 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.045224 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.268104 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.268104 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124535 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124535 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.101022 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.101022 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.133414 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.133414 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.133414 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.133414 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15457.698721 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15457.698721 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 48374.579140 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 48374.579140 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9248.502994 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9248.502994 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5299.504950 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5299.504950 # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 41631.625064 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 41631.625064 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 41631.625064 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 41631.625064 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 31799 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 19293 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 3299 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 180 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.638982 # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets 107.183333 # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.dcache.writebacks::writebacks 327984 # number of writebacks
system.cpu1.dcache.writebacks::total 327984 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171525 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 171525 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1401265 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 1401265 # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1449 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1449 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 1572790 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 1572790 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 1572790 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 1572790 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231477 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 231477 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163056 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 163056 # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12746 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12746 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10906 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 10906 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 394533 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 394533 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 394533 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 394533 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2900781135 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2900781135 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6520340298 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6520340298 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90030007 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90030007 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 35995000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 35995000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9421121433 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 9421121433 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9421121433 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 9421121433 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169236235005 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169236235005 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 34877229187 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 34877229187 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204113464192 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204113464192 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025976 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025976 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027946 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027946 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.111823 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.111823 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101003 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101003 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026755 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.026755 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026755 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.026755 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12531.617115 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12531.617115 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39988.349389 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 39988.349389 # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7063.392986 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7063.392986 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3300.476802 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3300.476802 # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23879.172168 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23879.172168 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23879.172168 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23879.172168 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_refs nan # Average number of references to valid blocks.
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1508067529269 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1508067529269 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1508067529269 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1508067529269 # number of overall MSHR uncacheable cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.kern.inst.quiesce 42383 # number of quiesce instructions executed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.kern.inst.quiesce 50336 # number of quiesce instructions executed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink