sim: Add the notion of clock domains to all ClockedObjects
This patch adds the notion of source- and derived-clock domains to the
ClockedObjects. As such, all clock information is moved to the clock
domain, and the ClockedObjects are grouped into domains.
The clock domains are either source domains, with a specific clock
period, or derived domains that have a parent domain and a divider
(potentially chained). For piece of logic that runs at a derived clock
(a ratio of the clock its parent is running at) the necessary derived
clock domain is created from its corresponding parent clock
domain. For now, the derived clock domain only supports a divider,
thus ensuring a lower speed compared to its parent. Multiplier
functionality implies a PLL logic that has not been modelled yet
(create a separate clock instead).
The clock domains should be used as a mechanism to provide a
controllable clock source that affects clock for every clocked object
lying beneath it. The clock of the domain can (in a future patch) be
controlled by a handler responsible for dynamic frequency scaling of
the respective clock domains.
All the config scripts have been retro-fitted with clock domains. For
the System a default SrcClockDomain is created. For CPUs that run at a
different speed than the system, there is a seperate clock domain
created. This domain incorporates the CPU and the associated
caches. As before, Ruby runs under its own clock domain.
The clock period of all domains are pre-computed, such that no virtual
functions or multiplications are needed when calling
clockPeriod. Instead, the clock period is pre-computed when any
changes occur. For this to be possible, each clock domain tracks its
children.
2013-06-27 11:49:49 +02:00
|
|
|
# Copyright (c) 2012-2013 ARM Limited
|
2012-01-17 19:55:08 +01:00
|
|
|
# All rights reserved.
|
|
|
|
#
|
|
|
|
# The license below extends only to copyright in the software and shall
|
|
|
|
# not be construed as granting a license to any other intellectual
|
|
|
|
# property including but not limited to intellectual property relating
|
|
|
|
# to a hardware implementation of the functionality of the software
|
|
|
|
# licensed hereunder. You may use the software subject to the license
|
|
|
|
# terms below provided that you ensure that this notice is replicated
|
|
|
|
# unmodified and in its entirety in all distributions of the software,
|
|
|
|
# modified or unmodified, in source code or in binary form.
|
|
|
|
#
|
2008-02-29 02:39:01 +01:00
|
|
|
# Copyright (c) 2006-2008 The Regents of The University of Michigan
|
2006-08-16 20:42:44 +02:00
|
|
|
# All rights reserved.
|
|
|
|
#
|
|
|
|
# Redistribution and use in source and binary forms, with or without
|
|
|
|
# modification, are permitted provided that the following conditions are
|
|
|
|
# met: redistributions of source code must retain the above copyright
|
|
|
|
# notice, this list of conditions and the following disclaimer;
|
|
|
|
# redistributions in binary form must reproduce the above copyright
|
|
|
|
# notice, this list of conditions and the following disclaimer in the
|
|
|
|
# documentation and/or other materials provided with the distribution;
|
|
|
|
# neither the name of the copyright holders nor the names of its
|
|
|
|
# contributors may be used to endorse or promote products derived from
|
|
|
|
# this software without specific prior written permission.
|
|
|
|
#
|
|
|
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
|
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
|
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
|
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
|
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
|
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
|
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
|
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
|
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
|
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
|
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
|
|
#
|
|
|
|
# Authors: Steve Reinhardt
|
|
|
|
|
|
|
|
# Simple test script
|
|
|
|
#
|
|
|
|
# "m5 test.py"
|
|
|
|
|
2009-09-23 00:24:16 +02:00
|
|
|
import optparse
|
|
|
|
import sys
|
2013-10-08 01:05:50 +02:00
|
|
|
import os
|
2009-09-23 00:24:16 +02:00
|
|
|
|
2006-08-16 20:42:44 +02:00
|
|
|
import m5
|
2009-09-23 00:24:16 +02:00
|
|
|
from m5.defines import buildEnv
|
|
|
|
from m5.objects import *
|
|
|
|
from m5.util import addToPath, fatal
|
2008-06-13 07:09:06 +02:00
|
|
|
|
2009-09-23 00:24:16 +02:00
|
|
|
addToPath('../common')
|
2011-03-20 05:13:04 +01:00
|
|
|
addToPath('../ruby')
|
|
|
|
|
2012-03-28 18:01:53 +02:00
|
|
|
import Options
|
2011-03-20 05:13:04 +01:00
|
|
|
import Ruby
|
2006-10-27 22:32:26 +02:00
|
|
|
import Simulation
|
2010-02-25 19:13:40 +01:00
|
|
|
import CacheConfig
|
2013-08-19 09:52:34 +02:00
|
|
|
import MemConfig
|
2006-10-30 22:51:46 +01:00
|
|
|
from Caches import *
|
2008-02-29 02:39:01 +01:00
|
|
|
from cpu2000 import *
|
2006-08-16 20:42:44 +02:00
|
|
|
|
2014-11-24 03:01:08 +01:00
|
|
|
# Check if KVM support has been enabled, we might need to do VM
|
|
|
|
# configuration if that's the case.
|
|
|
|
have_kvm_support = 'BaseKvmCPU' in globals()
|
|
|
|
def is_kvm_cpu(cpu_class):
|
|
|
|
return have_kvm_support and cpu_class != None and \
|
|
|
|
issubclass(cpu_class, BaseKvmCPU)
|
|
|
|
|
2012-09-09 16:33:45 +02:00
|
|
|
def get_processes(options):
|
|
|
|
"""Interprets provided options and returns a list of processes"""
|
|
|
|
|
|
|
|
multiprocesses = []
|
|
|
|
inputs = []
|
|
|
|
outputs = []
|
|
|
|
errouts = []
|
|
|
|
pargs = []
|
|
|
|
|
|
|
|
workloads = options.cmd.split(';')
|
|
|
|
if options.input != "":
|
|
|
|
inputs = options.input.split(';')
|
|
|
|
if options.output != "":
|
|
|
|
outputs = options.output.split(';')
|
|
|
|
if options.errout != "":
|
|
|
|
errouts = options.errout.split(';')
|
|
|
|
if options.options != "":
|
|
|
|
pargs = options.options.split(';')
|
|
|
|
|
|
|
|
idx = 0
|
|
|
|
for wrkld in workloads:
|
|
|
|
process = LiveProcess()
|
|
|
|
process.executable = wrkld
|
2013-10-08 01:05:50 +02:00
|
|
|
process.cwd = os.getcwd()
|
2012-09-09 16:33:45 +02:00
|
|
|
|
|
|
|
if len(pargs) > idx:
|
2012-09-12 00:47:21 +02:00
|
|
|
process.cmd = [wrkld] + pargs[idx].split()
|
2012-09-09 16:33:45 +02:00
|
|
|
else:
|
|
|
|
process.cmd = [wrkld]
|
|
|
|
|
|
|
|
if len(inputs) > idx:
|
|
|
|
process.input = inputs[idx]
|
|
|
|
if len(outputs) > idx:
|
|
|
|
process.output = outputs[idx]
|
|
|
|
if len(errouts) > idx:
|
|
|
|
process.errout = errouts[idx]
|
|
|
|
|
|
|
|
multiprocesses.append(process)
|
|
|
|
idx += 1
|
|
|
|
|
|
|
|
if options.smt:
|
2015-01-20 14:12:45 +01:00
|
|
|
assert(options.cpu_type == "detailed")
|
2012-09-09 16:33:45 +02:00
|
|
|
return multiprocesses, idx
|
|
|
|
else:
|
|
|
|
return multiprocesses, 1
|
|
|
|
|
|
|
|
|
2006-08-16 20:42:44 +02:00
|
|
|
parser = optparse.OptionParser()
|
2012-03-28 18:01:53 +02:00
|
|
|
Options.addCommonOptions(parser)
|
|
|
|
Options.addSEOptions(parser)
|
2006-08-16 20:42:44 +02:00
|
|
|
|
2012-03-01 18:36:59 +01:00
|
|
|
if '--ruby' in sys.argv:
|
|
|
|
Ruby.define_options(parser)
|
2011-07-12 02:57:10 +02:00
|
|
|
|
|
|
|
(options, args) = parser.parse_args()
|
2011-03-20 05:13:04 +01:00
|
|
|
|
2006-08-16 20:42:44 +02:00
|
|
|
if args:
|
|
|
|
print "Error: script doesn't take any positional arguments"
|
|
|
|
sys.exit(1)
|
|
|
|
|
2011-03-20 05:12:59 +01:00
|
|
|
multiprocesses = []
|
2012-09-09 16:33:45 +02:00
|
|
|
numThreads = 1
|
2011-03-20 05:12:59 +01:00
|
|
|
|
2008-02-29 02:39:01 +01:00
|
|
|
if options.bench:
|
2011-03-20 05:12:59 +01:00
|
|
|
apps = options.bench.split("-")
|
|
|
|
if len(apps) != options.num_cpus:
|
|
|
|
print "number of benchmarks not equal to set num_cpus!"
|
2008-02-29 02:39:01 +01:00
|
|
|
sys.exit(1)
|
2011-03-20 05:12:59 +01:00
|
|
|
|
|
|
|
for app in apps:
|
|
|
|
try:
|
2011-03-20 05:13:02 +01:00
|
|
|
if buildEnv['TARGET_ISA'] == 'alpha':
|
arm: Add support for ARMv8 (AArch64 & AArch32)
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.
Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.
Contributors:
Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole (AArch64 NEON, validation)
Ali Saidi (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang (AArch64 Linux support)
Rene De Jong (AArch64 Linux support, performance opt.)
Matt Horsnell (AArch64 MP, validation)
Matt Evans (device models, code integration, validation)
Chris Adeniyi-Jones (AArch64 syscall-emulation)
Prakash Ramrakhyani (validation)
Dam Sunwoo (validation)
Chander Sudanthi (validation)
Stephan Diestelhorst (validation)
Andreas Hansson (code integration, performance opt.)
Eric Van Hensbergen (performance opt.)
Gabe Black
2014-01-24 22:29:34 +01:00
|
|
|
exec("workload = %s('alpha', 'tru64', '%s')" % (
|
|
|
|
app, options.spec_input))
|
|
|
|
elif buildEnv['TARGET_ISA'] == 'arm':
|
|
|
|
exec("workload = %s('arm_%s', 'linux', '%s')" % (
|
|
|
|
app, options.arm_iset, options.spec_input))
|
2011-03-20 05:13:02 +01:00
|
|
|
else:
|
arm: Add support for ARMv8 (AArch64 & AArch32)
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.
Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.
Contributors:
Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole (AArch64 NEON, validation)
Ali Saidi (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang (AArch64 Linux support)
Rene De Jong (AArch64 Linux support, performance opt.)
Matt Horsnell (AArch64 MP, validation)
Matt Evans (device models, code integration, validation)
Chris Adeniyi-Jones (AArch64 syscall-emulation)
Prakash Ramrakhyani (validation)
Dam Sunwoo (validation)
Chander Sudanthi (validation)
Stephan Diestelhorst (validation)
Andreas Hansson (code integration, performance opt.)
Eric Van Hensbergen (performance opt.)
Gabe Black
2014-01-24 22:29:34 +01:00
|
|
|
exec("workload = %s(buildEnv['TARGET_ISA', 'linux', '%s')" % (
|
|
|
|
app, options.spec_input))
|
2011-03-20 05:12:59 +01:00
|
|
|
multiprocesses.append(workload.makeLiveProcess())
|
|
|
|
except:
|
2014-03-20 14:03:09 +01:00
|
|
|
print >>sys.stderr, "Unable to find workload for %s: %s" % (
|
|
|
|
buildEnv['TARGET_ISA'], app)
|
2011-03-20 05:12:59 +01:00
|
|
|
sys.exit(1)
|
2012-03-28 18:01:53 +02:00
|
|
|
elif options.cmd:
|
2012-09-09 16:33:45 +02:00
|
|
|
multiprocesses, numThreads = get_processes(options)
|
2012-03-28 18:01:53 +02:00
|
|
|
else:
|
|
|
|
print >> sys.stderr, "No workload specified. Exiting!\n"
|
|
|
|
sys.exit(1)
|
2008-02-29 02:39:01 +01:00
|
|
|
|
|
|
|
|
2012-01-23 18:33:52 +01:00
|
|
|
(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
|
2012-09-09 16:33:45 +02:00
|
|
|
CPUClass.numThreads = numThreads
|
2006-10-24 00:42:46 +02:00
|
|
|
|
2012-09-09 16:33:45 +02:00
|
|
|
# Check -- do not allow SMT with multiple CPUs
|
|
|
|
if options.smt and options.num_cpus > 1:
|
|
|
|
fatal("You cannot use SMT with multiple CPUs!")
|
2006-10-24 00:42:46 +02:00
|
|
|
|
2012-09-09 16:33:45 +02:00
|
|
|
np = options.num_cpus
|
2006-10-27 22:32:26 +02:00
|
|
|
system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
|
sim: Add the notion of clock domains to all ClockedObjects
This patch adds the notion of source- and derived-clock domains to the
ClockedObjects. As such, all clock information is moved to the clock
domain, and the ClockedObjects are grouped into domains.
The clock domains are either source domains, with a specific clock
period, or derived domains that have a parent domain and a divider
(potentially chained). For piece of logic that runs at a derived clock
(a ratio of the clock its parent is running at) the necessary derived
clock domain is created from its corresponding parent clock
domain. For now, the derived clock domain only supports a divider,
thus ensuring a lower speed compared to its parent. Multiplier
functionality implies a PLL logic that has not been modelled yet
(create a separate clock instead).
The clock domains should be used as a mechanism to provide a
controllable clock source that affects clock for every clocked object
lying beneath it. The clock of the domain can (in a future patch) be
controlled by a handler responsible for dynamic frequency scaling of
the respective clock domains.
All the config scripts have been retro-fitted with clock domains. For
the System a default SrcClockDomain is created. For CPUs that run at a
different speed than the system, there is a seperate clock domain
created. This domain incorporates the CPU and the associated
caches. As before, Ruby runs under its own clock domain.
The clock period of all domains are pre-computed, such that no virtual
functions or multiplications are needed when calling
clockPeriod. Instead, the clock period is pre-computed when any
changes occur. For this to be possible, each clock domain tracks its
children.
2013-06-27 11:49:49 +02:00
|
|
|
mem_mode = test_mem_mode,
|
2013-08-19 09:52:34 +02:00
|
|
|
mem_ranges = [AddrRange(options.mem_size)],
|
2013-07-18 14:31:19 +02:00
|
|
|
cache_line_size = options.cacheline_size)
|
sim: Add the notion of clock domains to all ClockedObjects
This patch adds the notion of source- and derived-clock domains to the
ClockedObjects. As such, all clock information is moved to the clock
domain, and the ClockedObjects are grouped into domains.
The clock domains are either source domains, with a specific clock
period, or derived domains that have a parent domain and a divider
(potentially chained). For piece of logic that runs at a derived clock
(a ratio of the clock its parent is running at) the necessary derived
clock domain is created from its corresponding parent clock
domain. For now, the derived clock domain only supports a divider,
thus ensuring a lower speed compared to its parent. Multiplier
functionality implies a PLL logic that has not been modelled yet
(create a separate clock instead).
The clock domains should be used as a mechanism to provide a
controllable clock source that affects clock for every clocked object
lying beneath it. The clock of the domain can (in a future patch) be
controlled by a handler responsible for dynamic frequency scaling of
the respective clock domains.
All the config scripts have been retro-fitted with clock domains. For
the System a default SrcClockDomain is created. For CPUs that run at a
different speed than the system, there is a seperate clock domain
created. This domain incorporates the CPU and the associated
caches. As before, Ruby runs under its own clock domain.
The clock period of all domains are pre-computed, such that no virtual
functions or multiplications are needed when calling
clockPeriod. Instead, the clock period is pre-computed when any
changes occur. For this to be possible, each clock domain tracks its
children.
2013-06-27 11:49:49 +02:00
|
|
|
|
2013-08-19 09:52:28 +02:00
|
|
|
# Create a top-level voltage domain
|
|
|
|
system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
|
|
|
|
|
|
|
|
# Create a source clock for the system and set the clock period
|
|
|
|
system.clk_domain = SrcClockDomain(clock = options.sys_clock,
|
|
|
|
voltage_domain = system.voltage_domain)
|
|
|
|
|
|
|
|
# Create a CPU voltage domain
|
|
|
|
system.cpu_voltage_domain = VoltageDomain()
|
|
|
|
|
sim: Add the notion of clock domains to all ClockedObjects
This patch adds the notion of source- and derived-clock domains to the
ClockedObjects. As such, all clock information is moved to the clock
domain, and the ClockedObjects are grouped into domains.
The clock domains are either source domains, with a specific clock
period, or derived domains that have a parent domain and a divider
(potentially chained). For piece of logic that runs at a derived clock
(a ratio of the clock its parent is running at) the necessary derived
clock domain is created from its corresponding parent clock
domain. For now, the derived clock domain only supports a divider,
thus ensuring a lower speed compared to its parent. Multiplier
functionality implies a PLL logic that has not been modelled yet
(create a separate clock instead).
The clock domains should be used as a mechanism to provide a
controllable clock source that affects clock for every clocked object
lying beneath it. The clock of the domain can (in a future patch) be
controlled by a handler responsible for dynamic frequency scaling of
the respective clock domains.
All the config scripts have been retro-fitted with clock domains. For
the System a default SrcClockDomain is created. For CPUs that run at a
different speed than the system, there is a seperate clock domain
created. This domain incorporates the CPU and the associated
caches. As before, Ruby runs under its own clock domain.
The clock period of all domains are pre-computed, such that no virtual
functions or multiplications are needed when calling
clockPeriod. Instead, the clock period is pre-computed when any
changes occur. For this to be possible, each clock domain tracks its
children.
2013-06-27 11:49:49 +02:00
|
|
|
# Create a separate clock domain for the CPUs
|
2013-08-19 09:52:28 +02:00
|
|
|
system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
|
|
|
|
voltage_domain =
|
|
|
|
system.cpu_voltage_domain)
|
sim: Add the notion of clock domains to all ClockedObjects
This patch adds the notion of source- and derived-clock domains to the
ClockedObjects. As such, all clock information is moved to the clock
domain, and the ClockedObjects are grouped into domains.
The clock domains are either source domains, with a specific clock
period, or derived domains that have a parent domain and a divider
(potentially chained). For piece of logic that runs at a derived clock
(a ratio of the clock its parent is running at) the necessary derived
clock domain is created from its corresponding parent clock
domain. For now, the derived clock domain only supports a divider,
thus ensuring a lower speed compared to its parent. Multiplier
functionality implies a PLL logic that has not been modelled yet
(create a separate clock instead).
The clock domains should be used as a mechanism to provide a
controllable clock source that affects clock for every clocked object
lying beneath it. The clock of the domain can (in a future patch) be
controlled by a handler responsible for dynamic frequency scaling of
the respective clock domains.
All the config scripts have been retro-fitted with clock domains. For
the System a default SrcClockDomain is created. For CPUs that run at a
different speed than the system, there is a seperate clock domain
created. This domain incorporates the CPU and the associated
caches. As before, Ruby runs under its own clock domain.
The clock period of all domains are pre-computed, such that no virtual
functions or multiplications are needed when calling
clockPeriod. Instead, the clock period is pre-computed when any
changes occur. For this to be possible, each clock domain tracks its
children.
2013-06-27 11:49:49 +02:00
|
|
|
|
|
|
|
# All cpus belong to a common cpu_clk_domain, therefore running at a common
|
|
|
|
# frequency.
|
|
|
|
for cpu in system.cpu:
|
|
|
|
cpu.clk_domain = system.cpu_clk_domain
|
2006-10-24 00:42:46 +02:00
|
|
|
|
2014-11-24 03:01:08 +01:00
|
|
|
if is_kvm_cpu(CPUClass) or is_kvm_cpu(FutureClass):
|
|
|
|
if buildEnv['TARGET_ISA'] == 'x86':
|
|
|
|
system.vm = KvmVM()
|
|
|
|
for process in multiprocesses:
|
|
|
|
process.useArchPT = True
|
|
|
|
process.kvmInSE = True
|
|
|
|
else:
|
|
|
|
fatal("KvmCPU can only be used in SE mode with x86")
|
|
|
|
|
2012-04-03 09:50:14 +02:00
|
|
|
# Sanity check
|
2012-10-26 12:42:45 +02:00
|
|
|
if options.fastmem:
|
|
|
|
if CPUClass != AtomicSimpleCPU:
|
|
|
|
fatal("Fastmem can only be used with atomic CPU!")
|
|
|
|
if (options.caches or options.l2cache):
|
|
|
|
fatal("You cannot use fastmem in combination with caches!")
|
2012-04-03 09:50:14 +02:00
|
|
|
|
2013-04-22 19:20:31 +02:00
|
|
|
if options.simpoint_profile:
|
|
|
|
if not options.fastmem:
|
|
|
|
# Atomic CPU checked with fastmem option already
|
|
|
|
fatal("SimPoint generation should be done with atomic cpu and fastmem")
|
|
|
|
if np > 1:
|
|
|
|
fatal("SimPoint generation not supported with more than one CPUs")
|
|
|
|
|
2006-10-27 22:32:26 +02:00
|
|
|
for i in xrange(np):
|
2012-09-09 16:33:45 +02:00
|
|
|
if options.smt:
|
|
|
|
system.cpu[i].workload = multiprocesses
|
|
|
|
elif len(multiprocesses) == 1:
|
2012-04-17 23:12:41 +02:00
|
|
|
system.cpu[i].workload = multiprocesses[0]
|
|
|
|
else:
|
|
|
|
system.cpu[i].workload = multiprocesses[i]
|
2006-08-16 20:42:44 +02:00
|
|
|
|
2007-08-09 00:43:12 +02:00
|
|
|
if options.fastmem:
|
2012-05-16 18:37:08 +02:00
|
|
|
system.cpu[i].fastmem = True
|
2007-08-09 00:43:12 +02:00
|
|
|
|
2013-04-22 19:20:31 +02:00
|
|
|
if options.simpoint_profile:
|
2014-09-20 23:17:43 +02:00
|
|
|
system.cpu[i].addSimPointProbe(options.simpoint_interval)
|
2013-04-22 19:20:31 +02:00
|
|
|
|
2012-03-09 15:59:27 +01:00
|
|
|
if options.checker:
|
|
|
|
system.cpu[i].addCheckerCpu()
|
|
|
|
|
2013-01-07 19:05:35 +01:00
|
|
|
system.cpu[i].createThreads()
|
|
|
|
|
2012-03-09 15:59:27 +01:00
|
|
|
if options.ruby:
|
2012-03-11 22:51:38 +01:00
|
|
|
if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
|
|
|
|
print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
|
|
|
|
sys.exit(1)
|
|
|
|
|
2014-11-06 12:41:44 +01:00
|
|
|
Ruby.create_system(options, False, system)
|
2014-03-20 15:14:14 +01:00
|
|
|
assert(options.num_cpus == len(system.ruby._cpu_ports))
|
2012-03-11 22:51:38 +01:00
|
|
|
|
2014-09-01 23:55:30 +02:00
|
|
|
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
|
|
|
|
voltage_domain = system.voltage_domain)
|
2012-03-11 22:51:38 +01:00
|
|
|
for i in xrange(np):
|
2014-03-20 15:14:14 +01:00
|
|
|
ruby_port = system.ruby._cpu_ports[i]
|
2012-03-11 22:51:38 +01:00
|
|
|
|
|
|
|
# Create the interrupt controller and connect its ports to Ruby
|
2012-09-28 15:35:25 +02:00
|
|
|
# Note that the interrupt controller is always present but only
|
|
|
|
# in x86 does it have message ports that need to be connected
|
2012-03-11 22:51:38 +01:00
|
|
|
system.cpu[i].createInterruptController()
|
|
|
|
|
|
|
|
# Connect the cpu's cache ports to Ruby
|
|
|
|
system.cpu[i].icache_port = ruby_port.slave
|
|
|
|
system.cpu[i].dcache_port = ruby_port.slave
|
2012-09-13 04:42:57 +02:00
|
|
|
if buildEnv['TARGET_ISA'] == 'x86':
|
2012-09-28 15:35:25 +02:00
|
|
|
system.cpu[i].interrupts.pio = ruby_port.master
|
|
|
|
system.cpu[i].interrupts.int_master = ruby_port.slave
|
|
|
|
system.cpu[i].interrupts.int_slave = ruby_port.master
|
2012-09-13 04:42:57 +02:00
|
|
|
system.cpu[i].itb.walker.port = ruby_port.slave
|
|
|
|
system.cpu[i].dtb.walker.port = ruby_port.slave
|
2012-03-09 15:59:27 +01:00
|
|
|
else:
|
2014-04-01 18:17:46 +02:00
|
|
|
MemClass = Simulation.setMemClass(options)
|
2015-03-02 10:00:47 +01:00
|
|
|
system.membus = SystemXBar()
|
2012-03-09 15:59:27 +01:00
|
|
|
system.system_port = system.membus.slave
|
|
|
|
CacheConfig.config_cache(options, system)
|
2013-08-19 09:52:34 +02:00
|
|
|
MemConfig.config_mem(options, system)
|
2012-03-09 15:59:27 +01:00
|
|
|
|
2012-01-28 16:24:34 +01:00
|
|
|
root = Root(full_system = False, system = system)
|
2006-11-02 01:25:09 +01:00
|
|
|
Simulation.run(options, root, system, FutureClass)
|