config: remove ruby_fs.py
The patch removes the ruby_fs.py file. The functionality is being moved to fs.py. This would being ruby fs simulations in line with how ruby se simulations are started (using --ruby option). The alpha fs config functions are being combined for classing and ruby memory systems. This required renaming the piobus in ruby to iobus. So, we will have stats being renamed in the stats file for ruby fs regression.
This commit is contained in:
Nilay Vaish
parent
9b3418d163
commit
d5b5d89b34
6 changed files with 113 additions and 231 deletions
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@ -55,8 +55,8 @@ class MemBus(CoherentBus):
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default = Self.badaddr_responder.pio
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def makeLinuxAlphaSystem(mem_mode, mdesc = None):
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IO_address_space_base = 0x80000000000
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def makeLinuxAlphaSystem(mem_mode, mdesc = None, ruby = False):
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class BaseTsunami(Tsunami):
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ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
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ide = IdeController(disks=[Parent.disk0, Parent.disk2],
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@ -67,73 +67,44 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None):
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# generic system
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mdesc = SysConfig()
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self.readfile = mdesc.script()
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self.iobus = NoncoherentBus()
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self.membus = MemBus()
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# By default the bridge responds to all addresses above the I/O
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# base address (including the PCI config space)
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self.bridge = Bridge(delay='50ns',
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ranges = [AddrRange(IO_address_space_base, Addr.max)])
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self.mem_ranges = [AddrRange(mdesc.mem())]
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self.bridge.master = self.iobus.slave
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self.bridge.slave = self.membus.master
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self.disk0 = CowIdeDisk(driveID='master')
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self.disk2 = CowIdeDisk(driveID='master')
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self.disk0.childImage(mdesc.disk())
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self.disk2.childImage(disk('linux-bigswap2.img'))
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self.tsunami = BaseTsunami()
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# Create the io bus to connect all device ports
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self.iobus = NoncoherentBus()
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self.tsunami.attachIO(self.iobus)
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self.tsunami.ide.pio = self.iobus.master
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self.tsunami.ide.config = self.iobus.master
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self.tsunami.ide.dma = self.iobus.slave
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self.tsunami.ethernet.pio = self.iobus.master
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self.tsunami.ethernet.config = self.iobus.master
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self.tsunami.ethernet.dma = self.iobus.slave
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self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
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read_only = True))
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self.intrctrl = IntrControl()
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self.mem_mode = mem_mode
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self.terminal = Terminal()
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self.kernel = binary('vmlinux')
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self.pal = binary('ts_osfpal')
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self.console = binary('console')
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self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
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self.system_port = self.membus.slave
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if ruby:
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# Store the dma devices for later connection to dma ruby ports.
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# Append an underscore to dma_ports to avoid the SimObjectVector check.
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self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
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else:
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self.membus = MemBus()
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return self
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# By default the bridge responds to all addresses above the I/O
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# base address (including the PCI config space)
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IO_address_space_base = 0x80000000000
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self.bridge = Bridge(delay='50ns',
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ranges = [AddrRange(IO_address_space_base, Addr.max)])
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self.bridge.master = self.iobus.slave
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self.bridge.slave = self.membus.master
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self.tsunami.ide.dma = self.iobus.slave
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self.tsunami.ethernet.dma = self.iobus.slave
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self.system_port = self.membus.slave
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def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
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class BaseTsunami(Tsunami):
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ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
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ide = IdeController(disks=[Parent.disk0, Parent.disk2],
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pci_func=0, pci_dev=0, pci_bus=0)
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self = LinuxAlphaSystem()
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self.mem_ranges = [AddrRange(mdesc.mem())]
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if not mdesc:
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# generic system
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mdesc = SysConfig()
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self.readfile = mdesc.script()
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# Create pio bus to connect all device pio ports to rubymem's pio port
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self.piobus = NoncoherentBus()
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self.disk0 = CowIdeDisk(driveID='master')
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self.disk2 = CowIdeDisk(driveID='master')
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self.disk0.childImage(mdesc.disk())
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self.disk2.childImage(disk('linux-bigswap2.img'))
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self.tsunami = BaseTsunami()
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self.tsunami.attachIO(self.piobus)
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self.tsunami.ide.pio = self.piobus.master
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self.tsunami.ide.config = self.piobus.master
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self.tsunami.ethernet.pio = self.piobus.master
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self.tsunami.ethernet.config = self.piobus.master
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#
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# Store the dma devices for later connection to dma ruby ports.
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# Append an underscore to dma_devices to avoid the SimObjectVector check.
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#
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self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
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self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
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read_only = True))
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self.intrctrl = IntrControl()
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@ -392,12 +363,12 @@ def connectX86ClassicSystem(x86_sys, numCPUs):
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def connectX86RubySystem(x86_sys):
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# North Bridge
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x86_sys.piobus = NoncoherentBus()
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x86_sys.iobus = NoncoherentBus()
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# add the ide to the list of dma devices that later need to attach to
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# dma controllers
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x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
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x86_sys.pc.attachIO(x86_sys.piobus, x86_sys._dma_ports)
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x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports)
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def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None,
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@ -10,6 +10,8 @@
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood
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# Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
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# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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@ -37,6 +39,7 @@
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Ali Saidi
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# Brad Beckmann
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import optparse
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import sys
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@ -47,6 +50,9 @@ from m5.objects import *
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from m5.util import addToPath, fatal
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addToPath('../common')
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addToPath('../ruby')
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import Ruby
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from FSConfig import *
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from SysPaths import *
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@ -61,6 +67,10 @@ parser = optparse.OptionParser()
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Options.addCommonOptions(parser)
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Options.addFSOptions(parser)
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# Add the ruby specific and protocol specific options
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if '--ruby' in sys.argv:
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Ruby.define_options(parser)
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(options, args) = parser.parse_args()
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if args:
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@ -104,13 +114,14 @@ else:
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np = options.num_cpus
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if buildEnv['TARGET_ISA'] == "alpha":
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test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
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test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby)
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elif buildEnv['TARGET_ISA'] == "mips":
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test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
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elif buildEnv['TARGET_ISA'] == "sparc":
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test_sys = makeSparcSystem(test_mem_mode, bm[0])
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elif buildEnv['TARGET_ISA'] == "x86":
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test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0])
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test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
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options.ruby)
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elif buildEnv['TARGET_ISA'] == "arm":
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test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0],
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options.dtb_filename,
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@ -120,6 +131,9 @@ elif buildEnv['TARGET_ISA'] == "arm":
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else:
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fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
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# Set the cache line size for the entire system
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test_sys.cache_line_size = options.cacheline_size
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# Create a top-level voltage domain
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test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
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@ -156,32 +170,72 @@ test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
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if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
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test_sys.vm = KvmVM()
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if options.caches or options.l2cache:
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# By default the IOCache runs at the system clock
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test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
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test_sys.iocache.cpu_side = test_sys.iobus.master
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test_sys.iocache.mem_side = test_sys.membus.slave
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if options.ruby:
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# Check for timing mode because ruby does not support atomic accesses
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if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
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print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
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sys.exit(1)
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Ruby.create_system(options, test_sys, test_sys.iobus, test_sys._dma_ports)
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# Create a seperate clock domain for Ruby
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test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
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voltage_domain = test_sys.voltage_domain)
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for (i, cpu) in enumerate(test_sys.cpu):
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#
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# Tie the cpu ports to the correct ruby system ports
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#
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cpu.clk_domain = test_sys.cpu_clk_domain
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cpu.createThreads()
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cpu.createInterruptController()
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cpu.icache_port = test_sys.ruby._cpu_ruby_ports[i].slave
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cpu.dcache_port = test_sys.ruby._cpu_ruby_ports[i].slave
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if buildEnv['TARGET_ISA'] == "x86":
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cpu.itb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave
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cpu.dtb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave
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cpu.interrupts.pio = test_sys.ruby._cpu_ruby_ports[i].master
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cpu.interrupts.int_master = test_sys.ruby._cpu_ruby_ports[i].slave
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cpu.interrupts.int_slave = test_sys.ruby._cpu_ruby_ports[i].master
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test_sys.ruby._cpu_ruby_ports[i].access_phys_mem = True
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# Create the appropriate memory controllers and connect them to the
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# PIO bus
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test_sys.mem_ctrls = [TestMemClass(range = r) for r in test_sys.mem_ranges]
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for i in xrange(len(test_sys.mem_ctrls)):
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test_sys.mem_ctrls[i].port = test_sys.iobus.master
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else:
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test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
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test_sys.iobridge.slave = test_sys.iobus.master
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test_sys.iobridge.master = test_sys.membus.slave
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if options.caches or options.l2cache:
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# By default the IOCache runs at the system clock
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test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
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test_sys.iocache.cpu_side = test_sys.iobus.master
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test_sys.iocache.mem_side = test_sys.membus.slave
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else:
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test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
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test_sys.iobridge.slave = test_sys.iobus.master
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test_sys.iobridge.master = test_sys.membus.slave
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# Sanity check
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if options.fastmem:
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if TestCPUClass != AtomicSimpleCPU:
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fatal("Fastmem can only be used with atomic CPU!")
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if (options.caches or options.l2cache):
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fatal("You cannot use fastmem in combination with caches!")
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for i in xrange(np):
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# Sanity check
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if options.fastmem:
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test_sys.cpu[i].fastmem = True
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if options.checker:
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test_sys.cpu[i].addCheckerCpu()
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test_sys.cpu[i].createThreads()
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if TestCPUClass != AtomicSimpleCPU:
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fatal("Fastmem can only be used with atomic CPU!")
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if (options.caches or options.l2cache):
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fatal("You cannot use fastmem in combination with caches!")
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CacheConfig.config_cache(options, test_sys)
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MemConfig.config_mem(options, test_sys)
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for i in xrange(np):
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if options.fastmem:
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test_sys.cpu[i].fastmem = True
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if options.checker:
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test_sys.cpu[i].addCheckerCpu()
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test_sys.cpu[i].createThreads()
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CacheConfig.config_cache(options, test_sys)
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MemConfig.config_mem(options, test_sys)
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if len(bm) == 2:
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if buildEnv['TARGET_ISA'] == 'alpha':
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@ -1,146 +0,0 @@
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# Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Brad Beckmann
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#
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# Full system configuraiton for ruby
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#
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import optparse
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import sys
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import m5
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from m5.defines import buildEnv
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from m5.objects import *
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from m5.util import addToPath, fatal
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addToPath('../common')
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addToPath('../ruby')
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addToPath('../topologies')
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import Ruby
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from FSConfig import *
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from SysPaths import *
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from Benchmarks import *
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import Options
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import Simulation
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parser = optparse.OptionParser()
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Options.addCommonOptions(parser)
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Options.addFSOptions(parser)
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# Add the ruby specific and protocol specific options
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Ruby.define_options(parser)
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(options, args) = parser.parse_args()
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options.ruby = True
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if args:
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print "Error: script doesn't take any positional arguments"
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sys.exit(1)
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if options.benchmark:
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try:
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bm = Benchmarks[options.benchmark]
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except KeyError:
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print "Error benchmark %s has not been defined." % options.benchmark
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print "Valid benchmarks are: %s" % DefinedBenchmarks
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sys.exit(1)
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else:
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bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)]
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# Check for timing mode because ruby does not support atomic accesses
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if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
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print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
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sys.exit(1)
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(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
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TestMemClass = Simulation.setMemClass(options)
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if buildEnv['TARGET_ISA'] == "alpha":
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system = makeLinuxAlphaRubySystem(test_mem_mode, bm[0])
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elif buildEnv['TARGET_ISA'] == "x86":
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system = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], True)
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Simulation.setWorkCountOptions(system, options)
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else:
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fatal("incapable of building non-alpha or non-x86 full system!")
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system.cache_line_size = options.cacheline_size
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# Create a top-level voltage domain and clock domain
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system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
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system.clk_domain = SrcClockDomain(clock = options.sys_clock,
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voltage_domain = system.voltage_domain)
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if options.kernel is not None:
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system.kernel = binary(options.kernel)
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if options.script is not None:
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system.readfile = options.script
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system.cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)]
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# Create a source clock for the CPUs and set the clock period
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system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
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voltage_domain = system.voltage_domain)
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Ruby.create_system(options, system, system.piobus, system._dma_ports)
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# Create a seperate clock domain for Ruby
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system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
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voltage_domain = system.voltage_domain)
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for (i, cpu) in enumerate(system.cpu):
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#
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# Tie the cpu ports to the correct ruby system ports
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#
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cpu.clk_domain = system.cpu_clk_domain
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cpu.createThreads()
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cpu.createInterruptController()
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cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave
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cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave
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if buildEnv['TARGET_ISA'] == "x86":
|
||||
cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave
|
||||
cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave
|
||||
|
||||
cpu.interrupts.pio = system.ruby._cpu_ruby_ports[i].master
|
||||
cpu.interrupts.int_master = system.ruby._cpu_ruby_ports[i].slave
|
||||
cpu.interrupts.int_slave = system.ruby._cpu_ruby_ports[i].master
|
||||
|
||||
system.ruby._cpu_ruby_ports[i].access_phys_mem = True
|
||||
|
||||
# Create the appropriate memory controllers and connect them to the
|
||||
# PIO bus
|
||||
system.mem_ctrls = [TestMemClass(range = r) for r in system.mem_ranges]
|
||||
for i in xrange(len(system.mem_ctrls)):
|
||||
system.mem_ctrls[i].port = system.piobus.master
|
||||
|
||||
root = Root(full_system = True, system = system)
|
||||
Simulation.run(options, root, system, FutureClass)
|
||||
|
|
@ -53,7 +53,6 @@ from m5.util import addToPath, fatal
|
|||
|
||||
addToPath('../common')
|
||||
addToPath('../ruby')
|
||||
addToPath('../topologies')
|
||||
|
||||
import Options
|
||||
import Ruby
|
||||
|
|
@ -145,7 +144,8 @@ if options.bench:
|
|||
app, options.spec_input))
|
||||
multiprocesses.append(workload.makeLiveProcess())
|
||||
except:
|
||||
print >>sys.stderr, "Unable to find workload for %s: %s" % (buildEnv['TARGET_ISA'], app)
|
||||
print >>sys.stderr, "Unable to find workload for %s: %s" % (
|
||||
buildEnv['TARGET_ISA'], app)
|
||||
sys.exit(1)
|
||||
elif options.cmd:
|
||||
multiprocesses, numThreads = get_processes(options)
|
||||
|
|
|
|||
|
|
@ -43,6 +43,9 @@ import math
|
|||
import m5
|
||||
from m5.objects import *
|
||||
from m5.defines import buildEnv
|
||||
from m5.util import addToPath, fatal
|
||||
|
||||
addToPath('../topologies')
|
||||
|
||||
def define_options(parser):
|
||||
# By default, ruby uses the simple timing cpu
|
||||
|
|
|
|||
|
|
@ -68,7 +68,7 @@ system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
|
|||
system.cpu = [TimingSimpleCPU(cpu_id=i, clk_domain = system.cpu_clk_domain)
|
||||
for i in xrange(options.num_cpus)]
|
||||
|
||||
Ruby.create_system(options, system, system.piobus, system._dma_ports)
|
||||
Ruby.create_system(options, system, system.iobus, system._dma_ports)
|
||||
|
||||
# Create a seperate clock domain for Ruby
|
||||
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
|
||||
|
|
@ -92,7 +92,7 @@ for (i, cpu) in enumerate(system.cpu):
|
|||
system.physmem = [DDR3_1600_x64(range = r)
|
||||
for r in system.mem_ranges]
|
||||
for i in xrange(len(system.physmem)):
|
||||
system.physmem[i].port = system.piobus.master
|
||||
system.physmem[i].port = system.iobus.master
|
||||
|
||||
root = Root(full_system = True, system = system)
|
||||
m5.ticks.setGlobalFrequency('1THz')
|
||||
|
|
|
|||
Loading…
Reference in a new issue