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ruby: Fixes clock domains in configuration files

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This patch fixes scripts related to ruby by adding the ruby clock domain.
Now the L1 controllers and  the Sequencer shares the cpu clock domain,
while the rest of the components use the ruby clock domain.

Before this patch, running simulations with the cpu clock set at 2GHz or
1GHz will output the same time results and could distort power measurements.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
This commit is contained in:
Emilio Castillo ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E) 2014-09-01 16:55:30 -05:00
parent 5efbb4442a
commit 01f792a367
10 changed files with 20 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
configs/example/ruby_direct_test.py
View file

@ -105,7 +105,7 @@ system.clk_domain = SrcClockDomain(clock = options.sys_clock,
#
# Create the ruby random tester
#
system.tester = RubyDirectedTester(requests_to_complete = \
system.cpu = RubyDirectedTester(requests_to_complete = \
options.requests,
generator = generator)

2
configs/example/ruby_random_test.py
View file

@ -97,7 +97,7 @@ tester = RubyTester(check_flush = check_flush,
# actually used by the rubytester, but is included to support the
# M5 memory size == Ruby memory size checks
#
system = System(tester = tester, physmem = SimpleMemory(),
system = System(cpu = tester, physmem = SimpleMemory(),
mem_ranges = [AddrRange(options.mem_size)])
# Create a top-level voltage domain and clock domain

2
configs/example/se.py
View file

@ -235,6 +235,8 @@ if options.ruby:
Ruby.create_system(options, system)
assert(options.num_cpus == len(system.ruby._cpu_ports))
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain = system.voltage_domain)
for i in xrange(np):
ruby_port = system.ruby._cpu_ports[i]

2
configs/ruby/MESI_Three_Level.py
View file

@ -102,9 +102,11 @@ def create_system(options, system, dma_ports, ruby_system):
l0_cntrl = L0Cache_Controller(version = i*num_cpus_per_cluster + j,
Icache = l0i_cache, Dcache = l0d_cache,
send_evictions = (options.cpu_type == "detailed"),
clk_domain=system.cpu[i].clk_domain,
ruby_system = ruby_system)
cpu_seq = RubySequencer(version = i, icache = l0i_cache,
clk_domain=system.cpu[i].clk_domain,
dcache = l0d_cache, ruby_system = ruby_system)
l0_cntrl.sequencer = cpu_seq

2
configs/ruby/MESI_Two_Level.py
View file

@ -95,12 +95,14 @@ def create_system(options, system, dma_ports, ruby_system):
options.cpu_type == "detailed"),
prefetcher = prefetcher,
ruby_system = ruby_system,
clk_domain=system.cpu[i].clk_domain,
transitions_per_cycle=options.ports,
enable_prefetch = False)
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
dcache = l1d_cache,
clk_domain=system.cpu[i].clk_domain,
ruby_system = ruby_system)
l1_cntrl.sequencer = cpu_seq

2
configs/ruby/MI_example.py
View file

@ -82,11 +82,13 @@ def create_system(options, system, dma_ports, ruby_system):
send_evictions = (
options.cpu_type == "detailed"),
transitions_per_cycle = options.ports,
clk_domain=system.cpu[i].clk_domain,
ruby_system = ruby_system)
cpu_seq = RubySequencer(version = i,
icache = cache,
dcache = cache,
clk_domain=system.cpu[i].clk_domain,
ruby_system = ruby_system)
l1_cntrl.sequencer = cpu_seq

2
configs/ruby/MOESI_CMP_directory.py
View file

@ -92,11 +92,13 @@ def create_system(options, system, dma_ports, ruby_system):
send_evictions = (
options.cpu_type == "detailed"),
transitions_per_cycle = options.ports,
clk_domain=system.cpu[i].clk_domain,
ruby_system = ruby_system)
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
dcache = l1d_cache,
clk_domain=system.cpu[i].clk_domain,
ruby_system = ruby_system)
l1_cntrl.sequencer = cpu_seq

2
configs/ruby/MOESI_CMP_token.py
View file

@ -112,11 +112,13 @@ def create_system(options, system, dma_ports, ruby_system):
send_evictions = (
options.cpu_type == "detailed"),
transitions_per_cycle = options.ports,
clk_domain=system.cpu[i].clk_domain,
ruby_system = ruby_system)
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
dcache = l1d_cache,
clk_domain=system.cpu[i].clk_domain,
ruby_system = ruby_system)
l1_cntrl.sequencer = cpu_seq

2
configs/ruby/MOESI_hammer.py
View file

@ -105,11 +105,13 @@ def create_system(options, system, dma_ports, ruby_system):
send_evictions = (
options.cpu_type == "detailed"),
transitions_per_cycle = options.ports,
clk_domain=system.cpu[i].clk_domain,
ruby_system = ruby_system)
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
dcache = l1d_cache,
clk_domain=system.cpu[i].clk_domain,
ruby_system = ruby_system)
l1_cntrl.sequencer = cpu_seq

5
tests/configs/rubytest-ruby.py
View file

@ -78,7 +78,10 @@ if buildEnv['PROTOCOL'] == 'MOESI_hammer':
tester = RubyTester(check_flush = check_flush, checks_to_complete = 100,
wakeup_frequency = 10, num_cpus = options.num_cpus)
system = System(tester = tester, physmem = SimpleMemory(null = True))
# We set the testers as cpu for ruby to find the correct clock domains
# for the L1 Objects.
system = System(cpu = tester, physmem = SimpleMemory(null = True))
# Dummy voltage domain for all our clock domains
system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
system.clk_domain = SrcClockDomain(clock = '1GHz',