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gem5/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout

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regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
Redirecting stdout to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic/simout
Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic/simerr
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
tests: update config.ini and stdout for the various tests. These files were a bit too out of date and resulted in a bit of confusion.
2008-07-22 23:00:18 +02:00
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
gem5 compiled Sep 22 2013 06:07:13
gem5 started Sep 22 2013 06:11:45
gem5 executing on zizzer
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic
tests: update config.ini and stdout for the various tests. These files were a bit too out of date and resulted in a bit of confusion.
2008-07-22 23:00:18 +02:00
Global frequency set at 1000000000000 ticks per second
Reference updates. Since split cache is gone, a lot of config.ini changes, and minor changes to stats that are likely due to the decoupling of insertions/evictions in the cache.
2008-11-06 17:11:42 +01:00
info: Entering event queue @ 0. Starting simulation...
Add regression for SPARC "hard" instruction test. Only runs in simple-atomic right now since we don't have cache support for the atomic instructions. --HG-- extra : convert_revision : b7013e6963885dfe2b4630ac175e24ddad6d42a6
2007-03-06 21:57:28 +01:00
Begining test of difficult SPARC instructions...
LDSTUB: Passed
SWAP: Passed
CAS FAIL: Passed
CAS WORK: Passed
CASX FAIL: Passed
CASX WORK: Passed
LDTX: Passed
LDTW: Passed
add to instruction test sttw instruction --HG-- extra : convert_revision : 16efbe12e609a909a589505ad6c473eb44c38f9c
2007-03-29 21:41:09 +02:00
STTW: Passed
Add regression for SPARC "hard" instruction test. Only runs in simple-atomic right now since we don't have cache support for the atomic instructions. --HG-- extra : convert_revision : b7013e6963885dfe2b4630ac175e24ddad6d42a6
2007-03-06 21:57:28 +01:00
Done
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
Exiting @ tick 7612000 because target called exit()
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