2010-06-02 19:58:00 +02:00
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// -*- mode:c++ -*-
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// Copyright (c) 2010 ARM Limited
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Copyright (c) 2007-2008 The Florida State University
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Stephen Hines
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////////////////////////////////////////////////////////////////////
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//
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// The actual ARM ISA decoder
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// --------------------------
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// The following instructions are specified in the ARM ISA
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// Specification. Decoding closely follows the style specified
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// in the ARM ISA specification document starting with Table B.1 or 3-1
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//
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//
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2010-06-02 19:58:04 +02:00
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0: decode COND_CODE {
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0xF: ArmUnconditional::armUnconditional();
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default: decode ENCODING {
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2010-06-02 19:58:00 +02:00
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format DataOp {
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0x0: decode SEVEN_AND_FOUR {
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1: decode MISC_OPCODE {
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0x9: decode PREPOST {
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2010-06-02 19:58:03 +02:00
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0: ArmMultAndMultAcc::armMultAndMultAcc();
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2010-06-02 19:58:05 +02:00
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1: ArmSyncMem::armSyncMem();
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2010-06-02 19:58:00 +02:00
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}
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2010-06-02 19:58:01 +02:00
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0xb, 0xd, 0xf: AddrMode3::addrMode3();
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2010-06-02 19:58:00 +02:00
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}
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0: decode IS_MISC {
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2010-06-02 19:58:02 +02:00
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0: ArmDataProcReg::armDataProcReg();
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2010-06-02 19:58:03 +02:00
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1: decode OPCODE_7 {
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0x0: decode MISC_OPCODE {
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2010-06-02 19:58:05 +02:00
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0x0: ArmMsrMrs::armMsrMrs();
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2010-06-02 19:58:08 +02:00
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0x1: ArmBxClz::armBxClz();
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2010-06-02 19:58:03 +02:00
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0x2: decode OPCODE {
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0x9: WarnUnimpl::bxj();
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}
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0x3: decode OPCODE {
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0x9: ArmBlxReg::armBlxReg();
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}
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2010-06-02 19:58:05 +02:00
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0x5: ArmSatAddSub::armSatAddSub();
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2010-06-02 19:58:00 +02:00
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}
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2010-06-02 19:58:03 +02:00
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0x1: ArmHalfWordMultAndMultAcc::armHalfWordMultAndMultAcc();
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2010-06-02 19:58:00 +02:00
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}
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}
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}
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0x1: decode IS_MISC {
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2010-06-02 19:58:02 +02:00
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0: ArmDataProcImm::armDataProcImm();
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2010-06-02 19:58:00 +02:00
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1: decode OPCODE {
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// The following two instructions aren't supposed to be defined
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0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }});
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0x9: decode RN {
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0: decode IMM {
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0: PredImmOp::nop({{ ; }});
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1: WarnUnimpl::yield();
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2: WarnUnimpl::wfe();
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3: WarnUnimpl::wfi();
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4: WarnUnimpl::sev();
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}
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default: PredImmOp::msr_i_cpsr({{
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uint32_t newCpsr =
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cpsrWriteByInstr(Cpsr | CondCodes,
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rotated_imm, RN, false);
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Cpsr = ~CondCodesMask & newCpsr;
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CondCodes = CondCodesMask & newCpsr;
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}});
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}
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0xa: PredOp::movt({{ Rd = IMMED_11_0 << 16 | RN << 28 | Rd<15:0>; }});
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0xb: PredImmOp::msr_i_spsr({{
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Spsr = spsrWriteByInstr(Spsr, rotated_imm, RN, false);
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}});
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}
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}
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2010-06-02 19:58:01 +02:00
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0x2: AddrMode2::addrMode2(True);
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2010-06-02 19:58:00 +02:00
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0x3: decode OPCODE_4 {
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2010-06-02 19:58:01 +02:00
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0: AddrMode2::addrMode2(False);
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2010-06-02 19:58:03 +02:00
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1: decode OPCODE_24_23 {
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2010-06-02 19:58:05 +02:00
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0x0: ArmParallelAddSubtract::armParallelAddSubtract();
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2010-06-02 19:58:05 +02:00
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0x1: ArmPackUnpackSatReverse::armPackUnpackSatReverse();
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2010-06-02 19:58:03 +02:00
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0x2: ArmSignedMultiplies::armSignedMultiplies();
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0x3: decode MEDIA_OPCODE {
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2010-06-02 19:58:07 +02:00
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0x18: ArmUsad::armUsad();
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2010-06-02 19:58:00 +02:00
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}
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}
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}
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2010-06-02 19:58:02 +02:00
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0x4: ArmMacroMem::armMacroMem();
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2010-06-02 19:58:00 +02:00
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0x5: decode OPCODE_24 {
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2010-06-02 19:58:02 +02:00
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0: ArmBBlxImm::armBBlxImm();
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1: ArmBlBlxImm::armBlBlxImm();
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2010-06-02 19:58:00 +02:00
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}
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0x6: decode CPNUM {
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2010-06-02 19:58:04 +02:00
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0xb: ExtensionRegLoadStore::extensionRegLoadStore();
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2010-06-02 19:58:00 +02:00
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}
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0x7: decode OPCODE_24 {
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0: decode OPCODE_4 {
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0: decode CPNUM {
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2010-06-02 19:58:00 +02:00
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0xa, 0xb: decode OPCODE_23_20 {
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2010-06-02 19:58:01 +02:00
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##include "vfp.isa"
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2010-06-02 19:58:00 +02:00
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}
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2010-06-02 19:58:00 +02:00
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} // CPNUM
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1: decode CPNUM { // 27-24=1110,4 ==1
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1: decode OPCODE_15_12 {
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format FloatOp {
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0xf: decode OPCODE_23_21 {
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format FloatCmp {
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0x4: cmf({{ Fn.df }}, {{ Fm.df }});
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0x5: cnf({{ Fn.df }}, {{ -Fm.df }});
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0x6: cmfe({{ Fn.df }}, {{ Fm.df}});
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0x7: cnfe({{ Fn.df }}, {{ -Fm.df}});
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}
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}
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default: decode OPCODE_23_20 {
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0x0: decode OPCODE_7 {
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0: flts({{ Fn.sf = (float) Rd.sw; }});
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1: fltd({{ Fn.df = (double) Rd.sw; }});
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}
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0x1: decode OPCODE_7 {
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0: fixs({{ Rd = (uint32_t) Fm.sf; }});
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1: fixd({{ Rd = (uint32_t) Fm.df; }});
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}
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0x2: wfs({{ Fpsr = Rd; }});
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0x3: rfs({{ Rd = Fpsr; }});
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0x4: FailUnimpl::wfc();
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0x5: FailUnimpl::rfc();
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}
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} // format FloatOp
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}
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0xa: decode MISC_OPCODE {
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0x1: decode MEDIA_OPCODE {
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0xf: decode RN {
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0x0: FloatOp::fmrx_fpsid({{ Rd = Fpsid; }});
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0x1: FloatOp::fmrx_fpscr({{ Rd = Fpscr; }});
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0x8: FloatOp::fmrx_fpexc({{ Rd = Fpexc; }});
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}
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0xe: decode RN {
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0x0: FloatOp::fmxr_fpsid({{ Fpsid = Rd; }});
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0x1: FloatOp::fmxr_fpscr({{ Fpscr = Rd; }});
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0x8: FloatOp::fmxr_fpexc({{ Fpexc = Rd; }});
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}
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} // MEDIA_OPCODE (MISC_OPCODE 0x1)
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} // MISC_OPCODE (CPNUM 0xA)
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0xf: decode RN {
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// Barrriers, Cache Maintence, NOPS
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7: decode OPCODE_23_21 {
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0: decode RM {
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0: decode OPC2 {
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4: decode OPCODE_20 {
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0: PredOp::mcr_cp15_nop1({{ }}); // was wfi
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}
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}
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1: WarnUnimpl::cp15_cache_maint();
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4: WarnUnimpl::cp15_par();
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5: decode OPC2 {
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0,1: WarnUnimpl::cp15_cache_maint2();
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4: PredOp::cp15_isb({{ ; }}, IsMemBarrier, IsSerializeBefore);
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6,7: WarnUnimpl::cp15_bp_maint();
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}
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6: WarnUnimpl::cp15_cache_maint3();
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8: WarnUnimpl::cp15_va_to_pa();
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10: decode OPC2 {
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1,2: WarnUnimpl::cp15_cache_maint3();
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4: PredOp::cp15_dsb({{ ; }}, IsMemBarrier, IsSerializeBefore);
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5: PredOp::cp15_dmb({{ ; }}, IsMemBarrier, IsSerializeBefore);
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}
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11: WarnUnimpl::cp15_cache_maint4();
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13: decode OPC2 {
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1: decode OPCODE_20 {
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0: PredOp::mcr_cp15_nop2({{ }}); // was prefetch
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}
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}
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14: WarnUnimpl::cp15_cache_maint5();
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} // RM
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} // OPCODE_23_21 CR
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// Thread ID and context ID registers
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// Thread ID register needs cheaper access than miscreg
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13: WarnUnimpl::mcr_mrc_cp15_c7();
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// All the rest
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default: decode OPCODE_20 {
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0: PredOp::mcr_cp15({{
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fault = setCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2);
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}});
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1: PredOp::mrc_cp15({{
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fault = readCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2);
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}});
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}
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} // RN
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} // CPNUM (OP4 == 1)
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} //OPCODE_4
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2010-06-02 19:58:05 +02:00
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1: Svc::svc();
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2010-06-02 19:58:00 +02:00
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} // OPCODE_24
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}
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}
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2010-06-02 19:58:04 +02:00
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}
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2010-06-02 19:58:00 +02:00
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