2007-02-07 06:16:33 +01:00
---------- Begin Simulation Statistics ----------
2015-11-06 09:26:50 +01:00
sim_seconds 0.000534 # Number of seconds simulated
sim_ticks 534039500 # Number of ticks simulated
final_tick 534039500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2012-01-25 18:19:50 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2015-11-06 09:26:50 +01:00
host_tick_rate 107991246 # Simulator tick rate (ticks/s)
host_mem_usage 280540 # Number of bytes of host memory used
host_seconds 4.95 # Real time elapsed on the host
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2015-11-06 09:26:50 +01:00
system.physmem.bytes_read::cpu0 80135 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1 83816 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2 79566 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3 82290 # Number of bytes read from this memory
system.physmem.bytes_read::cpu4 82935 # Number of bytes read from this memory
system.physmem.bytes_read::cpu5 84320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu6 79631 # Number of bytes read from this memory
system.physmem.bytes_read::cpu7 84304 # Number of bytes read from this memory
system.physmem.bytes_read::total 656997 # Number of bytes read from this memory
system.physmem.bytes_written::writebacks 418368 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0 5512 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1 5388 # Number of bytes written to this memory
system.physmem.bytes_written::cpu2 5320 # Number of bytes written to this memory
system.physmem.bytes_written::cpu3 5503 # Number of bytes written to this memory
system.physmem.bytes_written::cpu4 5449 # Number of bytes written to this memory
system.physmem.bytes_written::cpu5 5363 # Number of bytes written to this memory
system.physmem.bytes_written::cpu6 5499 # Number of bytes written to this memory
system.physmem.bytes_written::cpu7 5488 # Number of bytes written to this memory
system.physmem.bytes_written::total 461890 # Number of bytes written to this memory
system.physmem.num_reads::cpu0 10898 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1 10988 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2 10833 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3 10911 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu4 10989 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu5 10862 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu6 10835 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu7 10972 # Number of read requests responded to by this memory
system.physmem.num_reads::total 87288 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 6537 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0 5512 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1 5388 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu2 5320 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu3 5503 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu4 5449 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu5 5363 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu6 5499 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu7 5488 # Number of write requests responded to by this memory
system.physmem.num_writes::total 50059 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0 150054444 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1 156947192 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2 148988979 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3 154089726 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu4 155297501 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu5 157890943 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu6 149110693 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu7 157860982 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1230240460 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 783402726 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0 10321334 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1 10089141 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu2 9961810 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu3 10304481 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu4 10203365 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu5 10042328 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu6 10296991 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu7 10276393 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 864898570 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 783402726 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0 160375777 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1 167036333 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2 158950789 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3 164394207 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu4 165500867 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu5 167933271 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu6 159407684 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu7 168137376 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2095139030 # Total bandwidth to/from this memory (bytes/s)
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2015-11-06 09:26:50 +01:00
system.cpu0.num_reads 98970 # number of read accesses completed
system.cpu0.num_writes 54697 # number of write accesses completed
system.cpu0.l1c.tags.replacements 22262 # number of replacements
system.cpu0.l1c.tags.tagsinuse 392.444163 # Cycle average of tags in use
system.cpu0.l1c.tags.total_refs 13142 # Total number of references to valid blocks.
system.cpu0.l1c.tags.sampled_refs 22657 # Sample count of references to valid blocks.
system.cpu0.l1c.tags.avg_refs 0.580041 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-11-06 09:26:50 +01:00
system.cpu0.l1c.tags.occ_blocks::cpu0 392.444163 # Average occupied blocks per requestor
system.cpu0.l1c.tags.occ_percent::cpu0 0.766493 # Average percentage of cache occupancy
system.cpu0.l1c.tags.occ_percent::total 0.766493 # Average percentage of cache occupancy
system.cpu0.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id
system.cpu0.l1c.tags.age_task_id_blocks_1024::0 382 # Occupied blocks per task id
system.cpu0.l1c.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id
system.cpu0.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id
system.cpu0.l1c.tags.tag_accesses 335259 # Number of tag accesses
system.cpu0.l1c.tags.data_accesses 335259 # Number of data accesses
system.cpu0.l1c.ReadReq_hits::cpu0 8424 # number of ReadReq hits
system.cpu0.l1c.ReadReq_hits::total 8424 # number of ReadReq hits
system.cpu0.l1c.WriteReq_hits::cpu0 1108 # number of WriteReq hits
system.cpu0.l1c.WriteReq_hits::total 1108 # number of WriteReq hits
system.cpu0.l1c.demand_hits::cpu0 9532 # number of demand (read+write) hits
system.cpu0.l1c.demand_hits::total 9532 # number of demand (read+write) hits
system.cpu0.l1c.overall_hits::cpu0 9532 # number of overall hits
system.cpu0.l1c.overall_hits::total 9532 # number of overall hits
system.cpu0.l1c.ReadReq_misses::cpu0 36392 # number of ReadReq misses
system.cpu0.l1c.ReadReq_misses::total 36392 # number of ReadReq misses
system.cpu0.l1c.WriteReq_misses::cpu0 23768 # number of WriteReq misses
system.cpu0.l1c.WriteReq_misses::total 23768 # number of WriteReq misses
system.cpu0.l1c.demand_misses::cpu0 60160 # number of demand (read+write) misses
system.cpu0.l1c.demand_misses::total 60160 # number of demand (read+write) misses
system.cpu0.l1c.overall_misses::cpu0 60160 # number of overall misses
system.cpu0.l1c.overall_misses::total 60160 # number of overall misses
system.cpu0.l1c.ReadReq_miss_latency::cpu0 598420373 # number of ReadReq miss cycles
system.cpu0.l1c.ReadReq_miss_latency::total 598420373 # number of ReadReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::cpu0 705577272 # number of WriteReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::total 705577272 # number of WriteReq miss cycles
system.cpu0.l1c.demand_miss_latency::cpu0 1303997645 # number of demand (read+write) miss cycles
system.cpu0.l1c.demand_miss_latency::total 1303997645 # number of demand (read+write) miss cycles
system.cpu0.l1c.overall_miss_latency::cpu0 1303997645 # number of overall miss cycles
system.cpu0.l1c.overall_miss_latency::total 1303997645 # number of overall miss cycles
system.cpu0.l1c.ReadReq_accesses::cpu0 44816 # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.ReadReq_accesses::total 44816 # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::cpu0 24876 # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::total 24876 # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.demand_accesses::cpu0 69692 # number of demand (read+write) accesses
system.cpu0.l1c.demand_accesses::total 69692 # number of demand (read+write) accesses
system.cpu0.l1c.overall_accesses::cpu0 69692 # number of overall (read+write) accesses
system.cpu0.l1c.overall_accesses::total 69692 # number of overall (read+write) accesses
system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.812031 # miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_miss_rate::total 0.812031 # miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.955459 # miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_miss_rate::total 0.955459 # miss rate for WriteReq accesses
system.cpu0.l1c.demand_miss_rate::cpu0 0.863227 # miss rate for demand accesses
system.cpu0.l1c.demand_miss_rate::total 0.863227 # miss rate for demand accesses
system.cpu0.l1c.overall_miss_rate::cpu0 0.863227 # miss rate for overall accesses
system.cpu0.l1c.overall_miss_rate::total 0.863227 # miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16443.734145 # average ReadReq miss latency
system.cpu0.l1c.ReadReq_avg_miss_latency::total 16443.734145 # average ReadReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 29686.017839 # average WriteReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::total 29686.017839 # average WriteReq miss latency
system.cpu0.l1c.demand_avg_miss_latency::cpu0 21675.492769 # average overall miss latency
system.cpu0.l1c.demand_avg_miss_latency::total 21675.492769 # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::cpu0 21675.492769 # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::total 21675.492769 # average overall miss latency
system.cpu0.l1c.blocked_cycles::no_mshrs 798798 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu0.l1c.blocked::no_mshrs 61887 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu0.l1c.avg_blocked_cycles::no_mshrs 12.907363 # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2012-01-25 18:19:50 +01:00
system.cpu0.l1c.fast_writes 0 # number of fast writes performed
system.cpu0.l1c.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.cpu0.l1c.writebacks::writebacks 9766 # number of writebacks
system.cpu0.l1c.writebacks::total 9766 # number of writebacks
system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36392 # number of ReadReq MSHR misses
system.cpu0.l1c.ReadReq_mshr_misses::total 36392 # number of ReadReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23768 # number of WriteReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::total 23768 # number of WriteReq MSHR misses
system.cpu0.l1c.demand_mshr_misses::cpu0 60160 # number of demand (read+write) MSHR misses
system.cpu0.l1c.demand_mshr_misses::total 60160 # number of demand (read+write) MSHR misses
system.cpu0.l1c.overall_mshr_misses::cpu0 60160 # number of overall MSHR misses
system.cpu0.l1c.overall_mshr_misses::total 60160 # number of overall MSHR misses
system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9799 # number of ReadReq MSHR uncacheable
system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9799 # number of ReadReq MSHR uncacheable
system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5512 # number of WriteReq MSHR uncacheable
system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5512 # number of WriteReq MSHR uncacheable
system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15311 # number of overall MSHR uncacheable misses
system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15311 # number of overall MSHR uncacheable misses
system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 562029373 # number of ReadReq MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_miss_latency::total 562029373 # number of ReadReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 681810272 # number of WriteReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::total 681810272 # number of WriteReq MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1243839645 # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::total 1243839645 # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1243839645 # number of overall MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::total 1243839645 # number of overall MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 706647630 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 706647630 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 855364129 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 855364129 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1562011759 # number of overall MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1562011759 # number of overall MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.812031 # mshr miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.812031 # mshr miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.955459 # mshr miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.955459 # mshr miss rate for WriteReq accesses
system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.863227 # mshr miss rate for demand accesses
system.cpu0.l1c.demand_mshr_miss_rate::total 0.863227 # mshr miss rate for demand accesses
system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.863227 # mshr miss rate for overall accesses
system.cpu0.l1c.overall_mshr_miss_rate::total 0.863227 # mshr miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 15443.761623 # average ReadReq mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 15443.761623 # average ReadReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 28686.059912 # average WriteReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 28686.059912 # average WriteReq mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 20675.526014 # average overall mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20675.526014 # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20675.526014 # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20675.526014 # average overall mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 72114.259618 # average ReadReq mshr uncacheable latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 72114.259618 # average ReadReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 155182.171444 # average WriteReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 155182.171444 # average WriteReq mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 102018.924891 # average overall mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 102018.924891 # average overall mshr uncacheable latency
2012-01-25 18:19:50 +01:00
system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-06 09:26:50 +01:00
system.cpu1.num_reads 98379 # number of read accesses completed
system.cpu1.num_writes 54883 # number of write accesses completed
system.cpu1.l1c.tags.replacements 22236 # number of replacements
system.cpu1.l1c.tags.tagsinuse 391.015365 # Cycle average of tags in use
system.cpu1.l1c.tags.total_refs 13378 # Total number of references to valid blocks.
system.cpu1.l1c.tags.sampled_refs 22622 # Sample count of references to valid blocks.
system.cpu1.l1c.tags.avg_refs 0.591371 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-11-06 09:26:50 +01:00
system.cpu1.l1c.tags.occ_blocks::cpu1 391.015365 # Average occupied blocks per requestor
system.cpu1.l1c.tags.occ_percent::cpu1 0.763702 # Average percentage of cache occupancy
system.cpu1.l1c.tags.occ_percent::total 0.763702 # Average percentage of cache occupancy
2015-07-03 16:15:03 +02:00
system.cpu1.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu1.l1c.tags.age_task_id_blocks_1024::0 375 # Occupied blocks per task id
system.cpu1.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id
2015-07-03 16:15:03 +02:00
system.cpu1.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id
2015-11-06 09:26:50 +01:00
system.cpu1.l1c.tags.tag_accesses 335372 # Number of tag accesses
system.cpu1.l1c.tags.data_accesses 335372 # Number of data accesses
system.cpu1.l1c.ReadReq_hits::cpu1 8546 # number of ReadReq hits
system.cpu1.l1c.ReadReq_hits::total 8546 # number of ReadReq hits
system.cpu1.l1c.WriteReq_hits::cpu1 1143 # number of WriteReq hits
system.cpu1.l1c.WriteReq_hits::total 1143 # number of WriteReq hits
system.cpu1.l1c.demand_hits::cpu1 9689 # number of demand (read+write) hits
system.cpu1.l1c.demand_hits::total 9689 # number of demand (read+write) hits
system.cpu1.l1c.overall_hits::cpu1 9689 # number of overall hits
system.cpu1.l1c.overall_hits::total 9689 # number of overall hits
system.cpu1.l1c.ReadReq_misses::cpu1 36240 # number of ReadReq misses
system.cpu1.l1c.ReadReq_misses::total 36240 # number of ReadReq misses
system.cpu1.l1c.WriteReq_misses::cpu1 23835 # number of WriteReq misses
system.cpu1.l1c.WriteReq_misses::total 23835 # number of WriteReq misses
system.cpu1.l1c.demand_misses::cpu1 60075 # number of demand (read+write) misses
system.cpu1.l1c.demand_misses::total 60075 # number of demand (read+write) misses
system.cpu1.l1c.overall_misses::cpu1 60075 # number of overall misses
system.cpu1.l1c.overall_misses::total 60075 # number of overall misses
system.cpu1.l1c.ReadReq_miss_latency::cpu1 593535449 # number of ReadReq miss cycles
system.cpu1.l1c.ReadReq_miss_latency::total 593535449 # number of ReadReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::cpu1 712426271 # number of WriteReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::total 712426271 # number of WriteReq miss cycles
system.cpu1.l1c.demand_miss_latency::cpu1 1305961720 # number of demand (read+write) miss cycles
system.cpu1.l1c.demand_miss_latency::total 1305961720 # number of demand (read+write) miss cycles
system.cpu1.l1c.overall_miss_latency::cpu1 1305961720 # number of overall miss cycles
system.cpu1.l1c.overall_miss_latency::total 1305961720 # number of overall miss cycles
system.cpu1.l1c.ReadReq_accesses::cpu1 44786 # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.ReadReq_accesses::total 44786 # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::cpu1 24978 # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::total 24978 # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.demand_accesses::cpu1 69764 # number of demand (read+write) accesses
system.cpu1.l1c.demand_accesses::total 69764 # number of demand (read+write) accesses
system.cpu1.l1c.overall_accesses::cpu1 69764 # number of overall (read+write) accesses
system.cpu1.l1c.overall_accesses::total 69764 # number of overall (read+write) accesses
system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.809181 # miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_miss_rate::total 0.809181 # miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954240 # miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_miss_rate::total 0.954240 # miss rate for WriteReq accesses
system.cpu1.l1c.demand_miss_rate::cpu1 0.861117 # miss rate for demand accesses
system.cpu1.l1c.demand_miss_rate::total 0.861117 # miss rate for demand accesses
system.cpu1.l1c.overall_miss_rate::cpu1 0.861117 # miss rate for overall accesses
system.cpu1.l1c.overall_miss_rate::total 0.861117 # miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16377.909741 # average ReadReq miss latency
system.cpu1.l1c.ReadReq_avg_miss_latency::total 16377.909741 # average ReadReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 29889.921166 # average WriteReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::total 29889.921166 # average WriteReq miss latency
system.cpu1.l1c.demand_avg_miss_latency::cpu1 21738.855098 # average overall miss latency
system.cpu1.l1c.demand_avg_miss_latency::total 21738.855098 # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::cpu1 21738.855098 # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::total 21738.855098 # average overall miss latency
system.cpu1.l1c.blocked_cycles::no_mshrs 803378 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu1.l1c.blocked::no_mshrs 62137 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.929140 # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2012-01-25 18:19:50 +01:00
system.cpu1.l1c.fast_writes 0 # number of fast writes performed
system.cpu1.l1c.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.cpu1.l1c.writebacks::writebacks 9779 # number of writebacks
system.cpu1.l1c.writebacks::total 9779 # number of writebacks
system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36240 # number of ReadReq MSHR misses
system.cpu1.l1c.ReadReq_mshr_misses::total 36240 # number of ReadReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23835 # number of WriteReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::total 23835 # number of WriteReq MSHR misses
system.cpu1.l1c.demand_mshr_misses::cpu1 60075 # number of demand (read+write) MSHR misses
system.cpu1.l1c.demand_mshr_misses::total 60075 # number of demand (read+write) MSHR misses
system.cpu1.l1c.overall_mshr_misses::cpu1 60075 # number of overall MSHR misses
system.cpu1.l1c.overall_mshr_misses::total 60075 # number of overall MSHR misses
system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9833 # number of ReadReq MSHR uncacheable
system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9833 # number of ReadReq MSHR uncacheable
system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5388 # number of WriteReq MSHR uncacheable
system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5388 # number of WriteReq MSHR uncacheable
system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15221 # number of overall MSHR uncacheable misses
system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15221 # number of overall MSHR uncacheable misses
system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 557295449 # number of ReadReq MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_miss_latency::total 557295449 # number of ReadReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 688592271 # number of WriteReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::total 688592271 # number of WriteReq MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1245887720 # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::total 1245887720 # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1245887720 # number of overall MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::total 1245887720 # number of overall MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 707451122 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 707451122 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 858171680 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 858171680 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1565622802 # number of overall MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1565622802 # number of overall MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.809181 # mshr miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.809181 # mshr miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954240 # mshr miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954240 # mshr miss rate for WriteReq accesses
system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.861117 # mshr miss rate for demand accesses
system.cpu1.l1c.demand_mshr_miss_rate::total 0.861117 # mshr miss rate for demand accesses
system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.861117 # mshr miss rate for overall accesses
system.cpu1.l1c.overall_mshr_miss_rate::total 0.861117 # mshr miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 15377.909741 # average ReadReq mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 15377.909741 # average ReadReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 28889.963121 # average WriteReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 28889.963121 # average WriteReq mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 20738.871744 # average overall mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::total 20738.871744 # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 20738.871744 # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::total 20738.871744 # average overall mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 71946.620767 # average ReadReq mshr uncacheable latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 71946.620767 # average ReadReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 159274.625093 # average WriteReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 159274.625093 # average WriteReq mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 102859.391761 # average overall mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 102859.391761 # average overall mshr uncacheable latency
2012-01-25 18:19:50 +01:00
system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-06 09:26:50 +01:00
system.cpu2.num_reads 99126 # number of read accesses completed
system.cpu2.num_writes 55057 # number of write accesses completed
system.cpu2.l1c.tags.replacements 22416 # number of replacements
system.cpu2.l1c.tags.tagsinuse 392.045662 # Cycle average of tags in use
system.cpu2.l1c.tags.total_refs 13448 # Total number of references to valid blocks.
system.cpu2.l1c.tags.sampled_refs 22823 # Sample count of references to valid blocks.
system.cpu2.l1c.tags.avg_refs 0.589230 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-11-06 09:26:50 +01:00
system.cpu2.l1c.tags.occ_blocks::cpu2 392.045662 # Average occupied blocks per requestor
system.cpu2.l1c.tags.occ_percent::cpu2 0.765714 # Average percentage of cache occupancy
system.cpu2.l1c.tags.occ_percent::total 0.765714 # Average percentage of cache occupancy
system.cpu2.l1c.tags.occ_task_id_blocks::1024 407 # Occupied blocks per task id
system.cpu2.l1c.tags.age_task_id_blocks_1024::0 394 # Occupied blocks per task id
system.cpu2.l1c.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id
system.cpu2.l1c.tags.occ_task_id_percent::1024 0.794922 # Percentage of cache occupancy per task id
system.cpu2.l1c.tags.tag_accesses 337969 # Number of tag accesses
system.cpu2.l1c.tags.data_accesses 337969 # Number of data accesses
system.cpu2.l1c.ReadReq_hits::cpu2 8656 # number of ReadReq hits
system.cpu2.l1c.ReadReq_hits::total 8656 # number of ReadReq hits
system.cpu2.l1c.WriteReq_hits::cpu2 1187 # number of WriteReq hits
system.cpu2.l1c.WriteReq_hits::total 1187 # number of WriteReq hits
system.cpu2.l1c.demand_hits::cpu2 9843 # number of demand (read+write) hits
system.cpu2.l1c.demand_hits::total 9843 # number of demand (read+write) hits
system.cpu2.l1c.overall_hits::cpu2 9843 # number of overall hits
system.cpu2.l1c.overall_hits::total 9843 # number of overall hits
system.cpu2.l1c.ReadReq_misses::cpu2 36613 # number of ReadReq misses
system.cpu2.l1c.ReadReq_misses::total 36613 # number of ReadReq misses
system.cpu2.l1c.WriteReq_misses::cpu2 23839 # number of WriteReq misses
system.cpu2.l1c.WriteReq_misses::total 23839 # number of WriteReq misses
system.cpu2.l1c.demand_misses::cpu2 60452 # number of demand (read+write) misses
system.cpu2.l1c.demand_misses::total 60452 # number of demand (read+write) misses
system.cpu2.l1c.overall_misses::cpu2 60452 # number of overall misses
system.cpu2.l1c.overall_misses::total 60452 # number of overall misses
system.cpu2.l1c.ReadReq_miss_latency::cpu2 594021809 # number of ReadReq miss cycles
system.cpu2.l1c.ReadReq_miss_latency::total 594021809 # number of ReadReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::cpu2 716005587 # number of WriteReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::total 716005587 # number of WriteReq miss cycles
system.cpu2.l1c.demand_miss_latency::cpu2 1310027396 # number of demand (read+write) miss cycles
system.cpu2.l1c.demand_miss_latency::total 1310027396 # number of demand (read+write) miss cycles
system.cpu2.l1c.overall_miss_latency::cpu2 1310027396 # number of overall miss cycles
system.cpu2.l1c.overall_miss_latency::total 1310027396 # number of overall miss cycles
system.cpu2.l1c.ReadReq_accesses::cpu2 45269 # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.ReadReq_accesses::total 45269 # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::cpu2 25026 # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::total 25026 # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.demand_accesses::cpu2 70295 # number of demand (read+write) accesses
system.cpu2.l1c.demand_accesses::total 70295 # number of demand (read+write) accesses
system.cpu2.l1c.overall_accesses::cpu2 70295 # number of overall (read+write) accesses
system.cpu2.l1c.overall_accesses::total 70295 # number of overall (read+write) accesses
system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.808787 # miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_miss_rate::total 0.808787 # miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.952569 # miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_miss_rate::total 0.952569 # miss rate for WriteReq accesses
system.cpu2.l1c.demand_miss_rate::cpu2 0.859976 # miss rate for demand accesses
system.cpu2.l1c.demand_miss_rate::total 0.859976 # miss rate for demand accesses
system.cpu2.l1c.overall_miss_rate::cpu2 0.859976 # miss rate for overall accesses
system.cpu2.l1c.overall_miss_rate::total 0.859976 # miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16224.341327 # average ReadReq miss latency
system.cpu2.l1c.ReadReq_avg_miss_latency::total 16224.341327 # average ReadReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 30035.051261 # average WriteReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::total 30035.051261 # average WriteReq miss latency
system.cpu2.l1c.demand_avg_miss_latency::cpu2 21670.538543 # average overall miss latency
system.cpu2.l1c.demand_avg_miss_latency::total 21670.538543 # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::cpu2 21670.538543 # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::total 21670.538543 # average overall miss latency
system.cpu2.l1c.blocked_cycles::no_mshrs 801429 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu2.l1c.blocked::no_mshrs 62324 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu2.l1c.avg_blocked_cycles::no_mshrs 12.859075 # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2012-01-25 18:19:50 +01:00
system.cpu2.l1c.fast_writes 0 # number of fast writes performed
system.cpu2.l1c.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.cpu2.l1c.writebacks::writebacks 9798 # number of writebacks
system.cpu2.l1c.writebacks::total 9798 # number of writebacks
system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36613 # number of ReadReq MSHR misses
system.cpu2.l1c.ReadReq_mshr_misses::total 36613 # number of ReadReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23839 # number of WriteReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::total 23839 # number of WriteReq MSHR misses
system.cpu2.l1c.demand_mshr_misses::cpu2 60452 # number of demand (read+write) MSHR misses
system.cpu2.l1c.demand_mshr_misses::total 60452 # number of demand (read+write) MSHR misses
system.cpu2.l1c.overall_mshr_misses::cpu2 60452 # number of overall MSHR misses
system.cpu2.l1c.overall_mshr_misses::total 60452 # number of overall MSHR misses
system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9743 # number of ReadReq MSHR uncacheable
system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9743 # number of ReadReq MSHR uncacheable
system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5322 # number of WriteReq MSHR uncacheable
system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5322 # number of WriteReq MSHR uncacheable
system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15065 # number of overall MSHR uncacheable misses
system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15065 # number of overall MSHR uncacheable misses
system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 557410809 # number of ReadReq MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_miss_latency::total 557410809 # number of ReadReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 692167587 # number of WriteReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::total 692167587 # number of WriteReq MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1249578396 # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::total 1249578396 # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1249578396 # number of overall MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::total 1249578396 # number of overall MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 702012144 # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 702012144 # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 835893746 # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 835893746 # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1537905890 # number of overall MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1537905890 # number of overall MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.808787 # mshr miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.808787 # mshr miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.952569 # mshr miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.952569 # mshr miss rate for WriteReq accesses
system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.859976 # mshr miss rate for demand accesses
system.cpu2.l1c.demand_mshr_miss_rate::total 0.859976 # mshr miss rate for demand accesses
system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.859976 # mshr miss rate for overall accesses
system.cpu2.l1c.overall_mshr_miss_rate::total 0.859976 # mshr miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 15224.395952 # average ReadReq mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 15224.395952 # average ReadReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 29035.093209 # average WriteReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 29035.093209 # average WriteReq mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 20670.588169 # average overall mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::total 20670.588169 # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 20670.588169 # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::total 20670.588169 # average overall mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 72052.975880 # average ReadReq mshr uncacheable latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 72052.975880 # average ReadReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 157063.838031 # average WriteReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157063.838031 # average WriteReq mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 102084.692333 # average overall mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 102084.692333 # average overall mshr uncacheable latency
2012-01-25 18:19:50 +01:00
system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-06 09:26:50 +01:00
system.cpu3.num_reads 99267 # number of read accesses completed
system.cpu3.num_writes 54937 # number of write accesses completed
system.cpu3.l1c.tags.replacements 22308 # number of replacements
system.cpu3.l1c.tags.tagsinuse 393.396608 # Cycle average of tags in use
system.cpu3.l1c.tags.total_refs 13642 # Total number of references to valid blocks.
system.cpu3.l1c.tags.sampled_refs 22699 # Sample count of references to valid blocks.
system.cpu3.l1c.tags.avg_refs 0.600996 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-11-06 09:26:50 +01:00
system.cpu3.l1c.tags.occ_blocks::cpu3 393.396608 # Average occupied blocks per requestor
system.cpu3.l1c.tags.occ_percent::cpu3 0.768353 # Average percentage of cache occupancy
system.cpu3.l1c.tags.occ_percent::total 0.768353 # Average percentage of cache occupancy
system.cpu3.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id
system.cpu3.l1c.tags.age_task_id_blocks_1024::0 377 # Occupied blocks per task id
system.cpu3.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
system.cpu3.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id
system.cpu3.l1c.tags.tag_accesses 336965 # Number of tag accesses
system.cpu3.l1c.tags.data_accesses 336965 # Number of data accesses
system.cpu3.l1c.ReadReq_hits::cpu3 8834 # number of ReadReq hits
system.cpu3.l1c.ReadReq_hits::total 8834 # number of ReadReq hits
system.cpu3.l1c.WriteReq_hits::cpu3 1126 # number of WriteReq hits
system.cpu3.l1c.WriteReq_hits::total 1126 # number of WriteReq hits
system.cpu3.l1c.demand_hits::cpu3 9960 # number of demand (read+write) hits
system.cpu3.l1c.demand_hits::total 9960 # number of demand (read+write) hits
system.cpu3.l1c.overall_hits::cpu3 9960 # number of overall hits
system.cpu3.l1c.overall_hits::total 9960 # number of overall hits
system.cpu3.l1c.ReadReq_misses::cpu3 36404 # number of ReadReq misses
system.cpu3.l1c.ReadReq_misses::total 36404 # number of ReadReq misses
system.cpu3.l1c.WriteReq_misses::cpu3 23769 # number of WriteReq misses
system.cpu3.l1c.WriteReq_misses::total 23769 # number of WriteReq misses
system.cpu3.l1c.demand_misses::cpu3 60173 # number of demand (read+write) misses
system.cpu3.l1c.demand_misses::total 60173 # number of demand (read+write) misses
system.cpu3.l1c.overall_misses::cpu3 60173 # number of overall misses
system.cpu3.l1c.overall_misses::total 60173 # number of overall misses
system.cpu3.l1c.ReadReq_miss_latency::cpu3 595557078 # number of ReadReq miss cycles
system.cpu3.l1c.ReadReq_miss_latency::total 595557078 # number of ReadReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::cpu3 707954928 # number of WriteReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::total 707954928 # number of WriteReq miss cycles
system.cpu3.l1c.demand_miss_latency::cpu3 1303512006 # number of demand (read+write) miss cycles
system.cpu3.l1c.demand_miss_latency::total 1303512006 # number of demand (read+write) miss cycles
system.cpu3.l1c.overall_miss_latency::cpu3 1303512006 # number of overall miss cycles
system.cpu3.l1c.overall_miss_latency::total 1303512006 # number of overall miss cycles
system.cpu3.l1c.ReadReq_accesses::cpu3 45238 # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.ReadReq_accesses::total 45238 # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::cpu3 24895 # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::total 24895 # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.demand_accesses::cpu3 70133 # number of demand (read+write) accesses
system.cpu3.l1c.demand_accesses::total 70133 # number of demand (read+write) accesses
system.cpu3.l1c.overall_accesses::cpu3 70133 # number of overall (read+write) accesses
system.cpu3.l1c.overall_accesses::total 70133 # number of overall (read+write) accesses
system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.804722 # miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_miss_rate::total 0.804722 # miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954770 # miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_miss_rate::total 0.954770 # miss rate for WriteReq accesses
system.cpu3.l1c.demand_miss_rate::cpu3 0.857984 # miss rate for demand accesses
system.cpu3.l1c.demand_miss_rate::total 0.857984 # miss rate for demand accesses
system.cpu3.l1c.overall_miss_rate::cpu3 0.857984 # miss rate for overall accesses
system.cpu3.l1c.overall_miss_rate::total 0.857984 # miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16359.660422 # average ReadReq miss latency
system.cpu3.l1c.ReadReq_avg_miss_latency::total 16359.660422 # average ReadReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 29784.800707 # average WriteReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::total 29784.800707 # average WriteReq miss latency
system.cpu3.l1c.demand_avg_miss_latency::cpu3 21662.739202 # average overall miss latency
system.cpu3.l1c.demand_avg_miss_latency::total 21662.739202 # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::cpu3 21662.739202 # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::total 21662.739202 # average overall miss latency
system.cpu3.l1c.blocked_cycles::no_mshrs 796210 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu3.l1c.blocked::no_mshrs 61792 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu3.l1c.avg_blocked_cycles::no_mshrs 12.885325 # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2012-01-25 18:19:50 +01:00
system.cpu3.l1c.fast_writes 0 # number of fast writes performed
system.cpu3.l1c.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.cpu3.l1c.writebacks::writebacks 9835 # number of writebacks
system.cpu3.l1c.writebacks::total 9835 # number of writebacks
system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36404 # number of ReadReq MSHR misses
system.cpu3.l1c.ReadReq_mshr_misses::total 36404 # number of ReadReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23769 # number of WriteReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::total 23769 # number of WriteReq MSHR misses
system.cpu3.l1c.demand_mshr_misses::cpu3 60173 # number of demand (read+write) MSHR misses
system.cpu3.l1c.demand_mshr_misses::total 60173 # number of demand (read+write) MSHR misses
system.cpu3.l1c.overall_mshr_misses::cpu3 60173 # number of overall MSHR misses
system.cpu3.l1c.overall_mshr_misses::total 60173 # number of overall MSHR misses
system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9778 # number of ReadReq MSHR uncacheable
system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9778 # number of ReadReq MSHR uncacheable
system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5503 # number of WriteReq MSHR uncacheable
system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5503 # number of WriteReq MSHR uncacheable
system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15281 # number of overall MSHR uncacheable misses
system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15281 # number of overall MSHR uncacheable misses
system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 559153078 # number of ReadReq MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_miss_latency::total 559153078 # number of ReadReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 684188928 # number of WriteReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::total 684188928 # number of WriteReq MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1243342006 # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::total 1243342006 # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1243342006 # number of overall MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::total 1243342006 # number of overall MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 702217176 # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 702217176 # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 867552200 # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 867552200 # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1569769376 # number of overall MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1569769376 # number of overall MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.804722 # mshr miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.804722 # mshr miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954770 # mshr miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954770 # mshr miss rate for WriteReq accesses
system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.857984 # mshr miss rate for demand accesses
system.cpu3.l1c.demand_mshr_miss_rate::total 0.857984 # mshr miss rate for demand accesses
system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.857984 # mshr miss rate for overall accesses
system.cpu3.l1c.overall_mshr_miss_rate::total 0.857984 # mshr miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 15359.660422 # average ReadReq mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 15359.660422 # average ReadReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 28784.926922 # average WriteReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 28784.926922 # average WriteReq mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 20662.789058 # average overall mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::total 20662.789058 # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 20662.789058 # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::total 20662.789058 # average overall mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 71816.033545 # average ReadReq mshr uncacheable latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 71816.033545 # average ReadReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 157650.772306 # average WriteReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157650.772306 # average WriteReq mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 102726.874943 # average overall mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 102726.874943 # average overall mshr uncacheable latency
2012-01-25 18:19:50 +01:00
system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-06 09:26:50 +01:00
system.cpu4.num_reads 98613 # number of read accesses completed
system.cpu4.num_writes 54610 # number of write accesses completed
system.cpu4.l1c.tags.replacements 21998 # number of replacements
system.cpu4.l1c.tags.tagsinuse 392.447255 # Cycle average of tags in use
system.cpu4.l1c.tags.total_refs 13326 # Total number of references to valid blocks.
system.cpu4.l1c.tags.sampled_refs 22393 # Sample count of references to valid blocks.
system.cpu4.l1c.tags.avg_refs 0.595097 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-11-06 09:26:50 +01:00
system.cpu4.l1c.tags.occ_blocks::cpu4 392.447255 # Average occupied blocks per requestor
system.cpu4.l1c.tags.occ_percent::cpu4 0.766499 # Average percentage of cache occupancy
system.cpu4.l1c.tags.occ_percent::total 0.766499 # Average percentage of cache occupancy
system.cpu4.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id
system.cpu4.l1c.tags.age_task_id_blocks_1024::0 385 # Occupied blocks per task id
system.cpu4.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id
system.cpu4.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id
system.cpu4.l1c.tags.tag_accesses 335144 # Number of tag accesses
system.cpu4.l1c.tags.data_accesses 335144 # Number of data accesses
system.cpu4.l1c.ReadReq_hits::cpu4 8557 # number of ReadReq hits
system.cpu4.l1c.ReadReq_hits::total 8557 # number of ReadReq hits
system.cpu4.l1c.WriteReq_hits::cpu4 1170 # number of WriteReq hits
system.cpu4.l1c.WriteReq_hits::total 1170 # number of WriteReq hits
system.cpu4.l1c.demand_hits::cpu4 9727 # number of demand (read+write) hits
system.cpu4.l1c.demand_hits::total 9727 # number of demand (read+write) hits
system.cpu4.l1c.overall_hits::cpu4 9727 # number of overall hits
system.cpu4.l1c.overall_hits::total 9727 # number of overall hits
system.cpu4.l1c.ReadReq_misses::cpu4 36223 # number of ReadReq misses
system.cpu4.l1c.ReadReq_misses::total 36223 # number of ReadReq misses
system.cpu4.l1c.WriteReq_misses::cpu4 23758 # number of WriteReq misses
system.cpu4.l1c.WriteReq_misses::total 23758 # number of WriteReq misses
system.cpu4.l1c.demand_misses::cpu4 59981 # number of demand (read+write) misses
system.cpu4.l1c.demand_misses::total 59981 # number of demand (read+write) misses
system.cpu4.l1c.overall_misses::cpu4 59981 # number of overall misses
system.cpu4.l1c.overall_misses::total 59981 # number of overall misses
system.cpu4.l1c.ReadReq_miss_latency::cpu4 587952444 # number of ReadReq miss cycles
system.cpu4.l1c.ReadReq_miss_latency::total 587952444 # number of ReadReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::cpu4 716203349 # number of WriteReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::total 716203349 # number of WriteReq miss cycles
system.cpu4.l1c.demand_miss_latency::cpu4 1304155793 # number of demand (read+write) miss cycles
system.cpu4.l1c.demand_miss_latency::total 1304155793 # number of demand (read+write) miss cycles
system.cpu4.l1c.overall_miss_latency::cpu4 1304155793 # number of overall miss cycles
system.cpu4.l1c.overall_miss_latency::total 1304155793 # number of overall miss cycles
system.cpu4.l1c.ReadReq_accesses::cpu4 44780 # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.ReadReq_accesses::total 44780 # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::cpu4 24928 # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::total 24928 # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.demand_accesses::cpu4 69708 # number of demand (read+write) accesses
system.cpu4.l1c.demand_accesses::total 69708 # number of demand (read+write) accesses
system.cpu4.l1c.overall_accesses::cpu4 69708 # number of overall (read+write) accesses
system.cpu4.l1c.overall_accesses::total 69708 # number of overall (read+write) accesses
system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.808910 # miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_miss_rate::total 0.808910 # miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953065 # miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_miss_rate::total 0.953065 # miss rate for WriteReq accesses
system.cpu4.l1c.demand_miss_rate::cpu4 0.860461 # miss rate for demand accesses
system.cpu4.l1c.demand_miss_rate::total 0.860461 # miss rate for demand accesses
system.cpu4.l1c.overall_miss_rate::cpu4 0.860461 # miss rate for overall accesses
system.cpu4.l1c.overall_miss_rate::total 0.860461 # miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16231.467410 # average ReadReq miss latency
system.cpu4.l1c.ReadReq_avg_miss_latency::total 16231.467410 # average ReadReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 30145.776118 # average WriteReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::total 30145.776118 # average WriteReq miss latency
system.cpu4.l1c.demand_avg_miss_latency::cpu4 21742.815108 # average overall miss latency
system.cpu4.l1c.demand_avg_miss_latency::total 21742.815108 # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::cpu4 21742.815108 # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::total 21742.815108 # average overall miss latency
system.cpu4.l1c.blocked_cycles::no_mshrs 805297 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu4.l1c.blocked::no_mshrs 61957 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu4.l1c.avg_blocked_cycles::no_mshrs 12.997676 # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2012-01-25 18:19:50 +01:00
system.cpu4.l1c.fast_writes 0 # number of fast writes performed
system.cpu4.l1c.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.cpu4.l1c.writebacks::writebacks 9749 # number of writebacks
system.cpu4.l1c.writebacks::total 9749 # number of writebacks
system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36223 # number of ReadReq MSHR misses
system.cpu4.l1c.ReadReq_mshr_misses::total 36223 # number of ReadReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23758 # number of WriteReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::total 23758 # number of WriteReq MSHR misses
system.cpu4.l1c.demand_mshr_misses::cpu4 59981 # number of demand (read+write) MSHR misses
system.cpu4.l1c.demand_mshr_misses::total 59981 # number of demand (read+write) MSHR misses
system.cpu4.l1c.overall_mshr_misses::cpu4 59981 # number of overall MSHR misses
system.cpu4.l1c.overall_mshr_misses::total 59981 # number of overall MSHR misses
system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9847 # number of ReadReq MSHR uncacheable
system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9847 # number of ReadReq MSHR uncacheable
system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5452 # number of WriteReq MSHR uncacheable
system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5452 # number of WriteReq MSHR uncacheable
system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15299 # number of overall MSHR uncacheable misses
system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15299 # number of overall MSHR uncacheable misses
system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 551729444 # number of ReadReq MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_miss_latency::total 551729444 # number of ReadReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 692447349 # number of WriteReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::total 692447349 # number of WriteReq MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1244176793 # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::total 1244176793 # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1244176793 # number of overall MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::total 1244176793 # number of overall MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 708336585 # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 708336585 # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 860694197 # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 860694197 # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1569030782 # number of overall MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1569030782 # number of overall MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.808910 # mshr miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.808910 # mshr miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953065 # mshr miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953065 # mshr miss rate for WriteReq accesses
system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.860461 # mshr miss rate for demand accesses
system.cpu4.l1c.demand_mshr_miss_rate::total 0.860461 # mshr miss rate for demand accesses
system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.860461 # mshr miss rate for overall accesses
system.cpu4.l1c.overall_mshr_miss_rate::total 0.860461 # mshr miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 15231.467410 # average ReadReq mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 15231.467410 # average ReadReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 29145.860300 # average WriteReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 29145.860300 # average WriteReq mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 20742.848452 # average overall mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::total 20742.848452 # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 20742.848452 # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::total 20742.848452 # average overall mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 71934.252564 # average ReadReq mshr uncacheable latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 71934.252564 # average ReadReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 157867.607667 # average WriteReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157867.607667 # average WriteReq mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 102557.734623 # average overall mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 102557.734623 # average overall mshr uncacheable latency
2012-01-25 18:19:50 +01:00
system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-06 09:26:50 +01:00
system.cpu5.num_reads 99530 # number of read accesses completed
system.cpu5.num_writes 55068 # number of write accesses completed
system.cpu5.l1c.tags.replacements 22260 # number of replacements
system.cpu5.l1c.tags.tagsinuse 393.692529 # Cycle average of tags in use
system.cpu5.l1c.tags.total_refs 13670 # Total number of references to valid blocks.
system.cpu5.l1c.tags.sampled_refs 22641 # Sample count of references to valid blocks.
system.cpu5.l1c.tags.avg_refs 0.603772 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-11-06 09:26:50 +01:00
system.cpu5.l1c.tags.occ_blocks::cpu5 393.692529 # Average occupied blocks per requestor
system.cpu5.l1c.tags.occ_percent::cpu5 0.768931 # Average percentage of cache occupancy
system.cpu5.l1c.tags.occ_percent::total 0.768931 # Average percentage of cache occupancy
system.cpu5.l1c.tags.occ_task_id_blocks::1024 381 # Occupied blocks per task id
system.cpu5.l1c.tags.age_task_id_blocks_1024::0 370 # Occupied blocks per task id
system.cpu5.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id
system.cpu5.l1c.tags.occ_task_id_percent::1024 0.744141 # Percentage of cache occupancy per task id
system.cpu5.l1c.tags.tag_accesses 337364 # Number of tag accesses
system.cpu5.l1c.tags.data_accesses 337364 # Number of data accesses
system.cpu5.l1c.ReadReq_hits::cpu5 8908 # number of ReadReq hits
system.cpu5.l1c.ReadReq_hits::total 8908 # number of ReadReq hits
system.cpu5.l1c.WriteReq_hits::cpu5 1154 # number of WriteReq hits
system.cpu5.l1c.WriteReq_hits::total 1154 # number of WriteReq hits
system.cpu5.l1c.demand_hits::cpu5 10062 # number of demand (read+write) hits
system.cpu5.l1c.demand_hits::total 10062 # number of demand (read+write) hits
system.cpu5.l1c.overall_hits::cpu5 10062 # number of overall hits
system.cpu5.l1c.overall_hits::total 10062 # number of overall hits
system.cpu5.l1c.ReadReq_misses::cpu5 36264 # number of ReadReq misses
system.cpu5.l1c.ReadReq_misses::total 36264 # number of ReadReq misses
system.cpu5.l1c.WriteReq_misses::cpu5 23895 # number of WriteReq misses
system.cpu5.l1c.WriteReq_misses::total 23895 # number of WriteReq misses
system.cpu5.l1c.demand_misses::cpu5 60159 # number of demand (read+write) misses
system.cpu5.l1c.demand_misses::total 60159 # number of demand (read+write) misses
system.cpu5.l1c.overall_misses::cpu5 60159 # number of overall misses
system.cpu5.l1c.overall_misses::total 60159 # number of overall misses
system.cpu5.l1c.ReadReq_miss_latency::cpu5 595565994 # number of ReadReq miss cycles
system.cpu5.l1c.ReadReq_miss_latency::total 595565994 # number of ReadReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::cpu5 715910266 # number of WriteReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::total 715910266 # number of WriteReq miss cycles
system.cpu5.l1c.demand_miss_latency::cpu5 1311476260 # number of demand (read+write) miss cycles
system.cpu5.l1c.demand_miss_latency::total 1311476260 # number of demand (read+write) miss cycles
system.cpu5.l1c.overall_miss_latency::cpu5 1311476260 # number of overall miss cycles
system.cpu5.l1c.overall_miss_latency::total 1311476260 # number of overall miss cycles
system.cpu5.l1c.ReadReq_accesses::cpu5 45172 # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.ReadReq_accesses::total 45172 # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::cpu5 25049 # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::total 25049 # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.demand_accesses::cpu5 70221 # number of demand (read+write) accesses
system.cpu5.l1c.demand_accesses::total 70221 # number of demand (read+write) accesses
system.cpu5.l1c.overall_accesses::cpu5 70221 # number of overall (read+write) accesses
system.cpu5.l1c.overall_accesses::total 70221 # number of overall (read+write) accesses
system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.802798 # miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_miss_rate::total 0.802798 # miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.953930 # miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_miss_rate::total 0.953930 # miss rate for WriteReq accesses
system.cpu5.l1c.demand_miss_rate::cpu5 0.856710 # miss rate for demand accesses
system.cpu5.l1c.demand_miss_rate::total 0.856710 # miss rate for demand accesses
system.cpu5.l1c.overall_miss_rate::cpu5 0.856710 # miss rate for overall accesses
system.cpu5.l1c.overall_miss_rate::total 0.856710 # miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16423.064030 # average ReadReq miss latency
system.cpu5.l1c.ReadReq_avg_miss_latency::total 16423.064030 # average ReadReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 29960.672358 # average WriteReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::total 29960.672358 # average WriteReq miss latency
system.cpu5.l1c.demand_avg_miss_latency::cpu5 21800.167224 # average overall miss latency
system.cpu5.l1c.demand_avg_miss_latency::total 21800.167224 # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::cpu5 21800.167224 # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::total 21800.167224 # average overall miss latency
system.cpu5.l1c.blocked_cycles::no_mshrs 800309 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu5.l1c.blocked::no_mshrs 61932 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.922383 # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2012-01-25 18:19:50 +01:00
system.cpu5.l1c.fast_writes 0 # number of fast writes performed
system.cpu5.l1c.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.cpu5.l1c.writebacks::writebacks 9774 # number of writebacks
system.cpu5.l1c.writebacks::total 9774 # number of writebacks
system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36264 # number of ReadReq MSHR misses
system.cpu5.l1c.ReadReq_mshr_misses::total 36264 # number of ReadReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23895 # number of WriteReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::total 23895 # number of WriteReq MSHR misses
system.cpu5.l1c.demand_mshr_misses::cpu5 60159 # number of demand (read+write) MSHR misses
system.cpu5.l1c.demand_mshr_misses::total 60159 # number of demand (read+write) MSHR misses
system.cpu5.l1c.overall_mshr_misses::cpu5 60159 # number of overall MSHR misses
system.cpu5.l1c.overall_mshr_misses::total 60159 # number of overall MSHR misses
system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9698 # number of ReadReq MSHR uncacheable
system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9698 # number of ReadReq MSHR uncacheable
system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5363 # number of WriteReq MSHR uncacheable
system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5363 # number of WriteReq MSHR uncacheable
system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15061 # number of overall MSHR uncacheable misses
system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15061 # number of overall MSHR uncacheable misses
system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 559302994 # number of ReadReq MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_miss_latency::total 559302994 # number of ReadReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 692016266 # number of WriteReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::total 692016266 # number of WriteReq MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1251319260 # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::total 1251319260 # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1251319260 # number of overall MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::total 1251319260 # number of overall MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 697234186 # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 697234186 # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 847695253 # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 847695253 # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1544929439 # number of overall MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1544929439 # number of overall MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.802798 # mshr miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.802798 # mshr miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.953930 # mshr miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.953930 # mshr miss rate for WriteReq accesses
system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.856710 # mshr miss rate for demand accesses
system.cpu5.l1c.demand_mshr_miss_rate::total 0.856710 # mshr miss rate for demand accesses
system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.856710 # mshr miss rate for overall accesses
system.cpu5.l1c.overall_mshr_miss_rate::total 0.856710 # mshr miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 15423.091606 # average ReadReq mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 15423.091606 # average ReadReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 28960.714208 # average WriteReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 28960.714208 # average WriteReq mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 20800.200469 # average overall mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::total 20800.200469 # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 20800.200469 # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::total 20800.200469 # average overall mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 71894.636626 # average ReadReq mshr uncacheable latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 71894.636626 # average ReadReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 158063.630990 # average WriteReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 158063.630990 # average WriteReq mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 102578.144811 # average overall mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 102578.144811 # average overall mshr uncacheable latency
2012-01-25 18:19:50 +01:00
system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-06 09:26:50 +01:00
system.cpu6.num_reads 100001 # number of read accesses completed
system.cpu6.num_writes 54955 # number of write accesses completed
system.cpu6.l1c.tags.replacements 22371 # number of replacements
system.cpu6.l1c.tags.tagsinuse 392.789220 # Cycle average of tags in use
system.cpu6.l1c.tags.total_refs 13659 # Total number of references to valid blocks.
system.cpu6.l1c.tags.sampled_refs 22773 # Sample count of references to valid blocks.
system.cpu6.l1c.tags.avg_refs 0.599789 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-11-06 09:26:50 +01:00
system.cpu6.l1c.tags.occ_blocks::cpu6 392.789220 # Average occupied blocks per requestor
system.cpu6.l1c.tags.occ_percent::cpu6 0.767166 # Average percentage of cache occupancy
system.cpu6.l1c.tags.occ_percent::total 0.767166 # Average percentage of cache occupancy
system.cpu6.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
system.cpu6.l1c.tags.age_task_id_blocks_1024::0 393 # Occupied blocks per task id
system.cpu6.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id
system.cpu6.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
system.cpu6.l1c.tags.tag_accesses 338676 # Number of tag accesses
system.cpu6.l1c.tags.data_accesses 338676 # Number of data accesses
system.cpu6.l1c.ReadReq_hits::cpu6 8791 # number of ReadReq hits
system.cpu6.l1c.ReadReq_hits::total 8791 # number of ReadReq hits
system.cpu6.l1c.WriteReq_hits::cpu6 1193 # number of WriteReq hits
system.cpu6.l1c.WriteReq_hits::total 1193 # number of WriteReq hits
system.cpu6.l1c.demand_hits::cpu6 9984 # number of demand (read+write) hits
system.cpu6.l1c.demand_hits::total 9984 # number of demand (read+write) hits
system.cpu6.l1c.overall_hits::cpu6 9984 # number of overall hits
system.cpu6.l1c.overall_hits::total 9984 # number of overall hits
system.cpu6.l1c.ReadReq_misses::cpu6 36779 # number of ReadReq misses
system.cpu6.l1c.ReadReq_misses::total 36779 # number of ReadReq misses
system.cpu6.l1c.WriteReq_misses::cpu6 23715 # number of WriteReq misses
system.cpu6.l1c.WriteReq_misses::total 23715 # number of WriteReq misses
system.cpu6.l1c.demand_misses::cpu6 60494 # number of demand (read+write) misses
system.cpu6.l1c.demand_misses::total 60494 # number of demand (read+write) misses
system.cpu6.l1c.overall_misses::cpu6 60494 # number of overall misses
system.cpu6.l1c.overall_misses::total 60494 # number of overall misses
system.cpu6.l1c.ReadReq_miss_latency::cpu6 595549144 # number of ReadReq miss cycles
system.cpu6.l1c.ReadReq_miss_latency::total 595549144 # number of ReadReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::cpu6 708070907 # number of WriteReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::total 708070907 # number of WriteReq miss cycles
system.cpu6.l1c.demand_miss_latency::cpu6 1303620051 # number of demand (read+write) miss cycles
system.cpu6.l1c.demand_miss_latency::total 1303620051 # number of demand (read+write) miss cycles
system.cpu6.l1c.overall_miss_latency::cpu6 1303620051 # number of overall miss cycles
system.cpu6.l1c.overall_miss_latency::total 1303620051 # number of overall miss cycles
system.cpu6.l1c.ReadReq_accesses::cpu6 45570 # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.ReadReq_accesses::total 45570 # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::cpu6 24908 # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::total 24908 # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.demand_accesses::cpu6 70478 # number of demand (read+write) accesses
system.cpu6.l1c.demand_accesses::total 70478 # number of demand (read+write) accesses
system.cpu6.l1c.overall_accesses::cpu6 70478 # number of overall (read+write) accesses
system.cpu6.l1c.overall_accesses::total 70478 # number of overall (read+write) accesses
system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.807088 # miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_miss_rate::total 0.807088 # miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.952104 # miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_miss_rate::total 0.952104 # miss rate for WriteReq accesses
system.cpu6.l1c.demand_miss_rate::cpu6 0.858339 # miss rate for demand accesses
system.cpu6.l1c.demand_miss_rate::total 0.858339 # miss rate for demand accesses
system.cpu6.l1c.overall_miss_rate::cpu6 0.858339 # miss rate for overall accesses
system.cpu6.l1c.overall_miss_rate::total 0.858339 # miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16192.641018 # average ReadReq miss latency
system.cpu6.l1c.ReadReq_avg_miss_latency::total 16192.641018 # average ReadReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 29857.512418 # average WriteReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::total 29857.512418 # average WriteReq miss latency
system.cpu6.l1c.demand_avg_miss_latency::cpu6 21549.576008 # average overall miss latency
system.cpu6.l1c.demand_avg_miss_latency::total 21549.576008 # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::cpu6 21549.576008 # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::total 21549.576008 # average overall miss latency
system.cpu6.l1c.blocked_cycles::no_mshrs 794028 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu6.l1c.blocked::no_mshrs 62044 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.797821 # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2012-01-25 18:19:50 +01:00
system.cpu6.l1c.fast_writes 0 # number of fast writes performed
system.cpu6.l1c.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.cpu6.l1c.writebacks::writebacks 9773 # number of writebacks
system.cpu6.l1c.writebacks::total 9773 # number of writebacks
system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36779 # number of ReadReq MSHR misses
system.cpu6.l1c.ReadReq_mshr_misses::total 36779 # number of ReadReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23715 # number of WriteReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::total 23715 # number of WriteReq MSHR misses
system.cpu6.l1c.demand_mshr_misses::cpu6 60494 # number of demand (read+write) MSHR misses
system.cpu6.l1c.demand_mshr_misses::total 60494 # number of demand (read+write) MSHR misses
system.cpu6.l1c.overall_mshr_misses::cpu6 60494 # number of overall MSHR misses
system.cpu6.l1c.overall_mshr_misses::total 60494 # number of overall MSHR misses
system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9743 # number of ReadReq MSHR uncacheable
system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9743 # number of ReadReq MSHR uncacheable
system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5502 # number of WriteReq MSHR uncacheable
system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5502 # number of WriteReq MSHR uncacheable
system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15245 # number of overall MSHR uncacheable misses
system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15245 # number of overall MSHR uncacheable misses
system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 558770144 # number of ReadReq MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_miss_latency::total 558770144 # number of ReadReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 684356907 # number of WriteReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::total 684356907 # number of WriteReq MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1243127051 # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::total 1243127051 # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1243127051 # number of overall MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::total 1243127051 # number of overall MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 702205139 # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 702205139 # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 875087157 # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 875087157 # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1577292296 # number of overall MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1577292296 # number of overall MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.807088 # mshr miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.807088 # mshr miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.952104 # mshr miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.952104 # mshr miss rate for WriteReq accesses
system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858339 # mshr miss rate for demand accesses
system.cpu6.l1c.demand_mshr_miss_rate::total 0.858339 # mshr miss rate for demand accesses
system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858339 # mshr miss rate for overall accesses
system.cpu6.l1c.overall_mshr_miss_rate::total 0.858339 # mshr miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 15192.641018 # average ReadReq mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 15192.641018 # average ReadReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 28857.554586 # average WriteReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 28857.554586 # average WriteReq mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20549.592538 # average overall mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20549.592538 # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20549.592538 # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20549.592538 # average overall mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 72072.784461 # average ReadReq mshr uncacheable latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 72072.784461 # average ReadReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 159048.919847 # average WriteReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 159048.919847 # average WriteReq mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 103462.925287 # average overall mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 103462.925287 # average overall mshr uncacheable latency
2012-01-25 18:19:50 +01:00
system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-06 09:26:50 +01:00
system.cpu7.num_reads 99732 # number of read accesses completed
system.cpu7.num_writes 55186 # number of write accesses completed
system.cpu7.l1c.tags.replacements 22105 # number of replacements
system.cpu7.l1c.tags.tagsinuse 391.370136 # Cycle average of tags in use
system.cpu7.l1c.tags.total_refs 13595 # Total number of references to valid blocks.
system.cpu7.l1c.tags.sampled_refs 22490 # Sample count of references to valid blocks.
system.cpu7.l1c.tags.avg_refs 0.604491 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-11-06 09:26:50 +01:00
system.cpu7.l1c.tags.occ_blocks::cpu7 391.370136 # Average occupied blocks per requestor
system.cpu7.l1c.tags.occ_percent::cpu7 0.764395 # Average percentage of cache occupancy
system.cpu7.l1c.tags.occ_percent::total 0.764395 # Average percentage of cache occupancy
system.cpu7.l1c.tags.occ_task_id_blocks::1024 385 # Occupied blocks per task id
system.cpu7.l1c.tags.age_task_id_blocks_1024::0 370 # Occupied blocks per task id
system.cpu7.l1c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id
system.cpu7.l1c.tags.occ_task_id_percent::1024 0.751953 # Percentage of cache occupancy per task id
system.cpu7.l1c.tags.tag_accesses 337196 # Number of tag accesses
system.cpu7.l1c.tags.data_accesses 337196 # Number of data accesses
system.cpu7.l1c.ReadReq_hits::cpu7 8779 # number of ReadReq hits
system.cpu7.l1c.ReadReq_hits::total 8779 # number of ReadReq hits
system.cpu7.l1c.WriteReq_hits::cpu7 1155 # number of WriteReq hits
system.cpu7.l1c.WriteReq_hits::total 1155 # number of WriteReq hits
system.cpu7.l1c.demand_hits::cpu7 9934 # number of demand (read+write) hits
system.cpu7.l1c.demand_hits::total 9934 # number of demand (read+write) hits
system.cpu7.l1c.overall_hits::cpu7 9934 # number of overall hits
system.cpu7.l1c.overall_hits::total 9934 # number of overall hits
system.cpu7.l1c.ReadReq_misses::cpu7 36327 # number of ReadReq misses
system.cpu7.l1c.ReadReq_misses::total 36327 # number of ReadReq misses
system.cpu7.l1c.WriteReq_misses::cpu7 23913 # number of WriteReq misses
system.cpu7.l1c.WriteReq_misses::total 23913 # number of WriteReq misses
system.cpu7.l1c.demand_misses::cpu7 60240 # number of demand (read+write) misses
system.cpu7.l1c.demand_misses::total 60240 # number of demand (read+write) misses
system.cpu7.l1c.overall_misses::cpu7 60240 # number of overall misses
system.cpu7.l1c.overall_misses::total 60240 # number of overall misses
system.cpu7.l1c.ReadReq_miss_latency::cpu7 591115609 # number of ReadReq miss cycles
system.cpu7.l1c.ReadReq_miss_latency::total 591115609 # number of ReadReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::cpu7 714870765 # number of WriteReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::total 714870765 # number of WriteReq miss cycles
system.cpu7.l1c.demand_miss_latency::cpu7 1305986374 # number of demand (read+write) miss cycles
system.cpu7.l1c.demand_miss_latency::total 1305986374 # number of demand (read+write) miss cycles
system.cpu7.l1c.overall_miss_latency::cpu7 1305986374 # number of overall miss cycles
system.cpu7.l1c.overall_miss_latency::total 1305986374 # number of overall miss cycles
system.cpu7.l1c.ReadReq_accesses::cpu7 45106 # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.ReadReq_accesses::total 45106 # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::cpu7 25068 # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::total 25068 # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.demand_accesses::cpu7 70174 # number of demand (read+write) accesses
system.cpu7.l1c.demand_accesses::total 70174 # number of demand (read+write) accesses
system.cpu7.l1c.overall_accesses::cpu7 70174 # number of overall (read+write) accesses
system.cpu7.l1c.overall_accesses::total 70174 # number of overall (read+write) accesses
system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.805370 # miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_miss_rate::total 0.805370 # miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953925 # miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_miss_rate::total 0.953925 # miss rate for WriteReq accesses
system.cpu7.l1c.demand_miss_rate::cpu7 0.858438 # miss rate for demand accesses
system.cpu7.l1c.demand_miss_rate::total 0.858438 # miss rate for demand accesses
system.cpu7.l1c.overall_miss_rate::cpu7 0.858438 # miss rate for overall accesses
system.cpu7.l1c.overall_miss_rate::total 0.858438 # miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16272.073361 # average ReadReq miss latency
system.cpu7.l1c.ReadReq_avg_miss_latency::total 16272.073361 # average ReadReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 29894.649981 # average WriteReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::total 29894.649981 # average WriteReq miss latency
system.cpu7.l1c.demand_avg_miss_latency::cpu7 21679.720684 # average overall miss latency
system.cpu7.l1c.demand_avg_miss_latency::total 21679.720684 # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::cpu7 21679.720684 # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::total 21679.720684 # average overall miss latency
system.cpu7.l1c.blocked_cycles::no_mshrs 800916 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu7.l1c.blocked::no_mshrs 62109 # number of cycles access was blocked
2012-01-25 18:19:50 +01:00
system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu7.l1c.avg_blocked_cycles::no_mshrs 12.895329 # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2012-01-25 18:19:50 +01:00
system.cpu7.l1c.fast_writes 0 # number of fast writes performed
system.cpu7.l1c.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.cpu7.l1c.writebacks::writebacks 9688 # number of writebacks
system.cpu7.l1c.writebacks::total 9688 # number of writebacks
system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36327 # number of ReadReq MSHR misses
system.cpu7.l1c.ReadReq_mshr_misses::total 36327 # number of ReadReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23913 # number of WriteReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::total 23913 # number of WriteReq MSHR misses
system.cpu7.l1c.demand_mshr_misses::cpu7 60240 # number of demand (read+write) MSHR misses
system.cpu7.l1c.demand_mshr_misses::total 60240 # number of demand (read+write) MSHR misses
system.cpu7.l1c.overall_mshr_misses::cpu7 60240 # number of overall MSHR misses
system.cpu7.l1c.overall_mshr_misses::total 60240 # number of overall MSHR misses
system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9808 # number of ReadReq MSHR uncacheable
system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9808 # number of ReadReq MSHR uncacheable
system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5490 # number of WriteReq MSHR uncacheable
system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5490 # number of WriteReq MSHR uncacheable
system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15298 # number of overall MSHR uncacheable misses
system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15298 # number of overall MSHR uncacheable misses
system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 554789609 # number of ReadReq MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_miss_latency::total 554789609 # number of ReadReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 690958765 # number of WriteReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::total 690958765 # number of WriteReq MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1245748374 # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::total 1245748374 # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1245748374 # number of overall MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::total 1245748374 # number of overall MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 704741576 # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 704741576 # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 868948151 # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 868948151 # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1573689727 # number of overall MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1573689727 # number of overall MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805370 # mshr miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805370 # mshr miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953925 # mshr miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953925 # mshr miss rate for WriteReq accesses
system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.858438 # mshr miss rate for demand accesses
system.cpu7.l1c.demand_mshr_miss_rate::total 0.858438 # mshr miss rate for demand accesses
system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.858438 # mshr miss rate for overall accesses
system.cpu7.l1c.overall_mshr_miss_rate::total 0.858438 # mshr miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 15272.100889 # average ReadReq mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 15272.100889 # average ReadReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 28894.691799 # average WriteReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 28894.691799 # average WriteReq mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20679.753884 # average overall mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20679.753884 # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20679.753884 # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20679.753884 # average overall mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 71853.749592 # average ReadReq mshr uncacheable latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 71853.749592 # average ReadReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 158278.351730 # average WriteReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 158278.351730 # average WriteReq mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 102868.984639 # average overall mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 102868.984639 # average overall mshr uncacheable latency
2012-01-25 18:19:50 +01:00
system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-06 09:26:50 +01:00
system.l2c.tags.replacements 13995 # number of replacements
system.l2c.tags.tagsinuse 787.283340 # Cycle average of tags in use
system.l2c.tags.total_refs 163090 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 14802 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 11.018106 # Average number of references to valid blocks.
2015-02-11 16:23:31 +01:00
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-11-06 09:26:50 +01:00
system.l2c.tags.occ_blocks::writebacks 729.204744 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0 7.276243 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1 7.685702 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2 7.303189 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3 7.305571 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu4 6.947966 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu5 7.333904 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu6 7.314281 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu7 6.911739 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.712114 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0 0.007106 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1 0.007506 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2 0.007132 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3 0.007134 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu4 0.006785 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu5 0.007162 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu6 0.007143 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu7 0.006750 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.768831 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024 807 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 673 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.788086 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 2092027 # Number of tag accesses
system.l2c.tags.data_accesses 2092027 # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks 76994 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 76994 # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0 283 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1 283 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2 290 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3 275 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu4 271 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu5 268 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu6 273 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu7 273 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 2216 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0 1696 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1 1826 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2 1766 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu3 1793 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu4 1691 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu5 1701 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu6 1693 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu7 1794 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 13960 # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0 10787 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1 10737 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2 10799 # number of ReadSharedReq hits
2015-09-25 13:27:03 +02:00
system.l2c.ReadSharedReq_hits::cpu3 10853 # number of ReadSharedReq hits
2015-11-06 09:26:50 +01:00
system.l2c.ReadSharedReq_hits::cpu4 10789 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu5 10747 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu6 10936 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu7 10812 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 86460 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0 12483 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1 12563 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2 12565 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3 12646 # number of demand (read+write) hits
system.l2c.demand_hits::cpu4 12480 # number of demand (read+write) hits
system.l2c.demand_hits::cpu5 12448 # number of demand (read+write) hits
system.l2c.demand_hits::cpu6 12629 # number of demand (read+write) hits
system.l2c.demand_hits::cpu7 12606 # number of demand (read+write) hits
system.l2c.demand_hits::total 100420 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0 12483 # number of overall hits
system.l2c.overall_hits::cpu1 12563 # number of overall hits
system.l2c.overall_hits::cpu2 12565 # number of overall hits
system.l2c.overall_hits::cpu3 12646 # number of overall hits
system.l2c.overall_hits::cpu4 12480 # number of overall hits
system.l2c.overall_hits::cpu5 12448 # number of overall hits
system.l2c.overall_hits::cpu6 12629 # number of overall hits
system.l2c.overall_hits::cpu7 12606 # number of overall hits
system.l2c.overall_hits::total 100420 # number of overall hits
system.l2c.UpgradeReq_misses::cpu0 2004 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1 2095 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2 2038 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3 2061 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu4 2078 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu5 2100 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu6 2074 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu7 2069 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 16519 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0 4524 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1 4568 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2 4664 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3 4580 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu4 4684 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu5 4609 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu6 4587 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu7 4667 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 36883 # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0 734 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1 790 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2 729 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu3 742 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu4 716 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu5 769 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu6 725 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu7 744 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 5949 # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0 5258 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1 5358 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2 5393 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3 5322 # number of demand (read+write) misses
system.l2c.demand_misses::cpu4 5400 # number of demand (read+write) misses
system.l2c.demand_misses::cpu5 5378 # number of demand (read+write) misses
system.l2c.demand_misses::cpu6 5312 # number of demand (read+write) misses
system.l2c.demand_misses::cpu7 5411 # number of demand (read+write) misses
system.l2c.demand_misses::total 42832 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0 5258 # number of overall misses
system.l2c.overall_misses::cpu1 5358 # number of overall misses
system.l2c.overall_misses::cpu2 5393 # number of overall misses
system.l2c.overall_misses::cpu3 5322 # number of overall misses
system.l2c.overall_misses::cpu4 5400 # number of overall misses
system.l2c.overall_misses::cpu5 5378 # number of overall misses
system.l2c.overall_misses::cpu6 5312 # number of overall misses
system.l2c.overall_misses::cpu7 5411 # number of overall misses
system.l2c.overall_misses::total 42832 # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0 68311482 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1 71351474 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2 71595476 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu3 70154979 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu4 71820479 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu5 71543984 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu6 71643479 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu7 74781299 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 571202652 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0 282056369 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1 284888871 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2 290531378 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3 285646696 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu4 292456878 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu5 287933871 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu6 285764379 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu7 290745363 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 2300023805 # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0 50144908 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1 53259395 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu2 49512906 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu3 50638402 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu4 48277416 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu5 51495417 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu6 49403402 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu7 50638912 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 403370758 # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0 332201277 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1 338148266 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2 340044284 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3 336285098 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu4 340734294 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu5 339429288 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu6 335167781 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu7 341384275 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 2703394563 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0 332201277 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1 338148266 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2 340044284 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3 336285098 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu4 340734294 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu5 339429288 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu6 335167781 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu7 341384275 # number of overall miss cycles
system.l2c.overall_miss_latency::total 2703394563 # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks 76994 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 76994 # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0 2287 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1 2378 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2 2328 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3 2336 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu4 2349 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu5 2368 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu6 2347 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu7 2342 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 18735 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0 6220 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1 6394 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2 6430 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3 6373 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu4 6375 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu5 6310 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu6 6280 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu7 6461 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 50843 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0 11521 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1 11527 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu2 11528 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu3 11595 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu4 11505 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu5 11516 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu6 11661 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu7 11556 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 92409 # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0 17741 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1 17921 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2 17958 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3 17968 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu4 17880 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu5 17826 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu6 17941 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu7 18017 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 143252 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0 17741 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1 17921 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2 17958 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3 17968 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu4 17880 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu5 17826 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu6 17941 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu7 18017 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 143252 # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0 0.876257 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1 0.880992 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2 0.875430 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3 0.882277 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu4 0.884632 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu5 0.886824 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu6 0.883681 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu7 0.883433 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.881719 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0 0.727331 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1 0.714420 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2 0.725350 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3 0.718657 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu4 0.734745 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu5 0.730428 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu6 0.730414 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu7 0.722334 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.725429 # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0 0.063710 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1 0.068535 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2 0.063237 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu3 0.063993 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu4 0.062234 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu5 0.066777 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu6 0.062173 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu7 0.064382 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.064377 # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0 0.296376 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1 0.298979 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2 0.300312 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3 0.296193 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu4 0.302013 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu5 0.301694 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu6 0.296082 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu7 0.300327 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.298998 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0 0.296376 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1 0.298979 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2 0.300312 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3 0.296193 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu4 0.302013 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu5 0.301694 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu6 0.296082 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu7 0.300327 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.298998 # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0 34087.565868 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1 34057.982816 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2 35130.263003 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu3 34039.291121 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu4 34562.309432 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu5 34068.563810 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu6 34543.625362 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu7 36143.692122 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 34578.524850 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0 62346.677498 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1 62366.215193 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2 62292.319468 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3 62368.274236 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu4 62437.420581 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu5 62472.091777 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu6 62298.752780 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu7 62298.127919 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 62359.997967 # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0 68317.313351 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1 67416.955696 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu2 67918.938272 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu3 68245.824798 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu4 67426.558659 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu5 66964.131339 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu6 68142.623448 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu7 68063.053763 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 67804.800471 # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0 63180.159186 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1 63110.911907 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2 63052.898943 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3 63187.729801 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu4 63098.943333 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu5 63114.408330 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu6 63096.344315 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu7 63090.791905 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 63116.234661 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0 63180.159186 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1 63110.911907 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2 63052.898943 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3 63187.729801 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu4 63098.943333 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu5 63114.408330 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu6 63096.344315 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu7 63090.791905 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 63116.234661 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 33757 # number of cycles access was blocked
2015-02-11 16:23:31 +01:00
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.l2c.blocked::no_mshrs 6432 # number of cycles access was blocked
2015-02-11 16:23:31 +01:00
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.l2c.avg_blocked_cycles::no_mshrs 5.248290 # average number of cycles each access was blocked
2015-02-11 16:23:31 +01:00
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.l2c.writebacks::writebacks 6537 # number of writebacks
system.l2c.writebacks::total 6537 # number of writebacks
system.l2c.UpgradeReq_mshr_hits::cpu0 1 # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu5 1 # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::total 2 # number of UpgradeReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu0 5 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu1 4 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu2 2 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu3 3 # number of ReadExReq MSHR hits
2015-09-25 13:27:03 +02:00
system.l2c.ReadExReq_mshr_hits::cpu4 4 # number of ReadExReq MSHR hits
2015-11-06 09:26:50 +01:00
system.l2c.ReadExReq_mshr_hits::cpu5 10 # number of ReadExReq MSHR hits
2015-09-25 13:27:03 +02:00
system.l2c.ReadExReq_mshr_hits::cpu6 7 # number of ReadExReq MSHR hits
2015-11-06 09:26:50 +01:00
system.l2c.ReadExReq_mshr_hits::cpu7 4 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::total 39 # number of ReadExReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0 4 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1 13 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu2 7 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu3 6 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu4 14 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu5 11 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu6 9 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu7 11 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total 75 # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0 9 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1 17 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2 9 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3 9 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu4 18 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu5 21 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu6 16 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu7 15 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 114 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0 9 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1 17 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2 9 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3 9 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu4 18 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu5 21 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu6 16 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu7 15 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 114 # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks 1240 # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total 1240 # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0 2003 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1 2095 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2 2038 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3 2061 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu4 2078 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu5 2099 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu6 2074 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu7 2069 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 16517 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0 4519 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1 4564 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2 4662 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3 4577 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu4 4680 # number of ReadExReq MSHR misses
2015-09-25 13:27:03 +02:00
system.l2c.ReadExReq_mshr_misses::cpu5 4599 # number of ReadExReq MSHR misses
2015-11-06 09:26:50 +01:00
system.l2c.ReadExReq_mshr_misses::cpu6 4580 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu7 4663 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 36844 # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0 730 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1 777 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu2 722 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu3 736 # number of ReadSharedReq MSHR misses
2015-09-25 13:27:03 +02:00
system.l2c.ReadSharedReq_mshr_misses::cpu4 702 # number of ReadSharedReq MSHR misses
2015-11-06 09:26:50 +01:00
system.l2c.ReadSharedReq_mshr_misses::cpu5 758 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu6 716 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu7 733 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total 5874 # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0 5249 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1 5341 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2 5384 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3 5313 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu4 5382 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu5 5357 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu6 5296 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu7 5396 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 42718 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0 5249 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1 5341 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2 5384 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3 5313 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu4 5382 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu5 5357 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu6 5296 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu7 5396 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 42718 # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0 9799 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1 9833 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu2 9742 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu3 9778 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu4 9847 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu5 9698 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu6 9743 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu7 9808 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total 78248 # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0 5512 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1 5388 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu2 5320 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu3 5503 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu4 5449 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu5 5363 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu6 5499 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu7 5489 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total 43523 # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0 15311 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1 15221 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu2 15062 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu3 15281 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu4 15296 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu5 15061 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu6 15242 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu7 15297 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total 121771 # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0 103796466 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1 108591953 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2 105681456 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3 106934463 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu4 107650463 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu5 108806472 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu6 107556959 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu7 107077279 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 856095511 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0 236726369 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1 239139871 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2 243801378 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3 239818196 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu4 245529878 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu5 241617872 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu6 239761379 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu7 244006864 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 1930401807 # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0 42764408 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1 44950896 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2 42066908 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu3 43073402 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu4 40746918 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu5 43606418 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu6 41895903 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu7 42768413 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 341873266 # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0 279490777 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1 284090767 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2 285868286 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3 282891598 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu4 286276796 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu5 285224290 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu6 281657282 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu7 286775277 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 2272275073 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0 279490777 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1 284090767 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2 285868286 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3 282891598 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu4 286276796 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu5 285224290 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu6 281657282 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu7 286775277 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 2272275073 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 503232104 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 504891308 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 500756647 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 501380612 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 505534787 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 497694775 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 500159589 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 503166776 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 4016816598 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 292229228 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 286836409 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 283709721 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 292753904 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 289394212 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 284248382 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 293152393 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 291492896 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 2313817145 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0 795461332 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1 791727717 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2 784466368 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu3 794134516 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu4 794928999 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu5 781943157 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu6 793311982 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu7 794659672 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 6330633743 # number of overall MSHR uncacheable cycles
2015-07-03 16:15:03 +02:00
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2015-11-06 09:26:50 +01:00
system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.875820 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.880992 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.875430 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.882277 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.884632 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.886402 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.883681 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.883433 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.881612 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.726527 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.713794 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.725039 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.718186 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.734118 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.728843 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.729299 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.721715 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.724662 # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.063363 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.067407 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.062630 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.063476 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.061017 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.065821 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.061401 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.063430 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.063565 # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0 0.295868 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1 0.298030 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2 0.299811 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3 0.295692 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu4 0.301007 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu5 0.300516 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu6 0.295190 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu7 0.299495 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.298202 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0 0.295868 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1 0.298030 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2 0.299811 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3 0.295692 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu4 0.301007 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu5 0.300516 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu6 0.295190 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu7 0.299495 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.298202 # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 51820.502247 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 51833.867780 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 51855.473994 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 51884.746725 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 51804.842637 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 51837.290138 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 51859.671649 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 51753.155631 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 51831.174608 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 52384.680018 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 52396.991893 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 52295.447876 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 52396.372296 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 52463.649145 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 52537.045445 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 52349.646070 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 52328.300236 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 52393.925931 # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 58581.380822 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 57851.861004 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 58264.415512 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 58523.644022 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 58044.042735 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 57528.255937 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 58513.831006 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 58347.084584 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 58201.100783 # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0 53246.480663 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1 53190.557386 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2 53095.892645 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3 53245.171843 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu4 53191.526570 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu5 53243.287288 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu6 53183.021526 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu7 53145.900111 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 53192.449857 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0 53246.480663 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1 53190.557386 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2 53095.892645 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3 53245.171843 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu4 53191.526570 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu5 53243.287288 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu6 53183.021526 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu7 53145.900111 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 53192.449857 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 51355.455046 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 51346.619343 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 51401.831965 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 51276.397218 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 51338.964862 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 51319.320994 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 51335.275480 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 51301.669657 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 51334.431525 # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 53016.913643 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 53236.156088 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 53328.894925 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 53198.964928 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 53109.600294 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 53001.749394 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 53310.127841 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 53104.918200 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 53163.089516 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 51953.584482 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 52015.486302 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 52082.483601 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 51968.753092 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 51969.730583 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 51918.408937 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 52047.761580 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 51948.726678 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 51988.024595 # average overall mshr uncacheable latency
2015-02-11 16:23:31 +01:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-06 09:26:50 +01:00
system.membus.trans_dist::ReadReq 78245 # Transaction distribution
system.membus.trans_dist::ReadResp 84100 # Transaction distribution
system.membus.trans_dist::WriteReq 43522 # Transaction distribution
system.membus.trans_dist::WriteResp 43520 # Transaction distribution
system.membus.trans_dist::WritebackDirty 6537 # Transaction distribution
system.membus.trans_dist::CleanEvict 1268 # Transaction distribution
system.membus.trans_dist::UpgradeReq 61107 # Transaction distribution
system.membus.trans_dist::UpgradeResp 50201 # Transaction distribution
system.membus.trans_dist::ReadExReq 48942 # Transaction distribution
system.membus.trans_dist::ReadExResp 3181 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 5862 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 426485 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 426485 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1118817 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 1118817 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 56662 # Total snoops (count)
system.membus.snoop_fanout::samples 253744 # Request fanout histogram
2015-02-11 16:23:31 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.membus.snoop_fanout::0 253744 100.00% 100.00% # Request fanout histogram
2015-02-11 16:23:31 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.membus.snoop_fanout::total 253744 # Request fanout histogram
system.membus.reqLayer0.occupancy 292620525 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 54.8 # Layer utilization (%)
system.membus.respLayer0.occupancy 295409000 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 55.3 # Layer utilization (%)
system.toL2Bus.snoop_filter.tot_requests 663684 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 282033 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 335738 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 12570 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 5835 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 6735 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq 78248 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 369469 # Transaction distribution
system.toL2Bus.trans_dist::ReadRespWithInvalidate 4 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 43523 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 43520 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 83531 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 20342 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 29636 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 29633 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 160854 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 160848 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 291239 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 121995 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122071 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122139 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122334 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122013 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 121723 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122513 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122322 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 977110 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1766349 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1778610 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1781270 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1785072 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1775296 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1771667 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1779976 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1778751 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 14216991 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 333737 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 624990 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 1.150519 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.991140 # Request fanout histogram
2015-02-11 16:23:31 +01:00
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.toL2Bus.snoop_fanout::0 174852 27.98% 27.98% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 256379 41.02% 69.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 133497 21.36% 90.36% # Request fanout histogram
system.toL2Bus.snoop_fanout::3 47307 7.57% 97.93% # Request fanout histogram
system.toL2Bus.snoop_fanout::4 11157 1.79% 99.71% # Request fanout histogram
system.toL2Bus.snoop_fanout::5 1650 0.26% 99.98% # Request fanout histogram
system.toL2Bus.snoop_fanout::6 145 0.02% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::7 3 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
2015-02-11 16:23:31 +01:00
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.toL2Bus.snoop_fanout::total 624990 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 497290718 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 93.1 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 100872915 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 18.9 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 100601006 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 18.8 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 101141480 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 18.9 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 100780789 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 18.9 # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy 100568051 # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization 18.8 # Layer utilization (%)
system.toL2Bus.respLayer5.occupancy 100691951 # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization 18.9 # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy 101210192 # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization 19.0 # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy 100872512 # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization 18.9 # Layer utilization (%)
2007-02-07 06:16:33 +01:00
---------- End Simulation Statistics ----------
