2013-03-11 23:45:09 +01:00
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Real time: Mar/11/2013 13:21:59
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2009-05-11 19:38:46 +02:00
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Profiler Stats
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--------------
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2013-03-11 23:45:09 +01:00
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Elapsed_time_in_seconds: 1
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Elapsed_time_in_minutes: 0.0166667
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Elapsed_time_in_hours: 0.000277778
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Elapsed_time_in_days: 1.15741e-05
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2009-05-11 19:38:46 +02:00
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2013-03-11 23:45:09 +01:00
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Virtual_time_in_seconds: 0.6
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Virtual_time_in_minutes: 0.01
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Virtual_time_in_hours: 0.000166667
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Virtual_time_in_days: 6.94444e-06
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2009-05-11 19:38:46 +02:00
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2012-09-10 19:44:03 +02:00
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Ruby_current_time: 121759
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2010-01-30 05:29:40 +01:00
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Ruby_start_time: 0
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2012-09-10 19:44:03 +02:00
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Ruby_cycles: 121759
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2009-05-11 19:38:46 +02:00
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2013-03-11 23:45:09 +01:00
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mbytes_resident: 66.582
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mbytes_total: 163.426
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resident_ratio: 0.407486
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2009-05-11 19:38:46 +02:00
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2012-09-10 19:44:03 +02:00
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ruby_cycles_executed: [ 121760 ]
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2009-08-09 13:01:56 +02:00
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2009-05-11 19:38:46 +02:00
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Busy Controller Counts:
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L1Cache-0:0
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Directory-0:0
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2010-01-30 05:29:40 +01:00
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2009-05-11 19:38:46 +02:00
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Busy Bank Count:0
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2013-03-11 23:45:09 +01:00
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sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8853 average: 1 | standard deviation: 0 | 0 8853 ]
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2009-05-11 19:38:46 +02:00
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All Non-Zero Cycle Demand Cache Accesses
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----------------------------------------
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2013-03-11 23:45:09 +01:00
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miss_latency: [binsize: 1 max: 125 count: 8852 average: 12.755 | standard deviation: 22.8655 | 0 0 0 7475 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 10 4 312 432 494 10 6 5 9 7 11 0 1 0 1 0 0 0 1 1 0 0 1 0 0 1 0 0 0 9 16 40 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
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miss_latency_LD: [binsize: 1 max: 101 count: 1045 average: 33.0842 | standard deviation: 31.8534 | 0 0 0 546 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 2 97 201 150 1 3 2 0 1 1 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 3 5 22 0 0 1 0 0 0 0 0 1 ]
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miss_latency_ST: [binsize: 1 max: 92 count: 935 average: 20.0845 | standard deviation: 28.1878 | 0 0 0 681 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 59 61 107 3 0 0 2 1 3 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 2 3 9 ]
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miss_latency_IFETCH: [binsize: 1 max: 125 count: 6864 average: 8.6639 | standard deviation: 18.0088 | 0 0 0 6241 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 4 1 156 170 236 6 3 3 7 5 7 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 4 8 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
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2012-09-10 19:44:03 +02:00
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miss_latency_RMW_Read: [binsize: 1 max: 65 count: 8 average: 10.75 | standard deviation: 21.9219 | 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
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2013-03-11 23:45:09 +01:00
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miss_latency_L1Cache: [binsize: 1 max: 3 count: 7475 average: 3 | standard deviation: 0 | 0 0 0 7475 ]
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miss_latency_Directory: [binsize: 1 max: 125 count: 1377 average: 65.7095 | standard deviation: 6.31582 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 10 4 312 432 494 10 6 5 9 7 11 0 1 0 1 0 0 0 1 1 0 0 1 0 0 1 0 0 0 9 16 40 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
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2011-02-04 12:47:23 +01:00
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miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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imcomplete_wCC_Times: 0
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miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
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miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
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miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
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2012-09-10 19:44:03 +02:00
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miss_latency_dir_first_response_to_completion: [binsize: 1 max: 61 count: 1 average: 61 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
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2011-02-04 12:47:23 +01:00
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imcomplete_dir_Times: 1376
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2013-03-11 23:45:09 +01:00
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miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 546 average: 3 | standard deviation: 0 | 0 0 0 546 ]
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2012-09-10 19:44:03 +02:00
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miss_latency_LD_Directory: [binsize: 1 max: 101 count: 499 average: 66.002 | standard deviation: 7.00186 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 2 97 201 150 1 3 2 0 1 1 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 3 5 22 0 0 1 0 0 0 0 0 1 ]
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2012-12-30 19:45:52 +01:00
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miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 681 average: 3 | standard deviation: 0 | 0 0 0 681 ]
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2013-03-11 23:45:09 +01:00
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miss_latency_ST_Directory: [binsize: 1 max: 92 count: 254 average: 65.8898 | standard deviation: 6.41669 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 59 61 107 3 0 0 2 1 3 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 2 3 9 ]
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2012-09-10 19:44:03 +02:00
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miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 6241 average: 3 | standard deviation: 0 | 0 0 0 6241 ]
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2013-03-11 23:45:09 +01:00
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miss_latency_IFETCH_Directory: [binsize: 1 max: 125 count: 623 average: 65.4029 | standard deviation: 5.66282 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 4 1 156 170 236 6 3 3 7 5 7 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 4 8 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
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2011-02-08 04:23:13 +01:00
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miss_latency_RMW_Read_L1Cache: [binsize: 1 max: 3 count: 7 average: 3 | standard deviation: 0 | 0 0 0 7 ]
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2012-09-10 19:44:03 +02:00
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miss_latency_RMW_Read_Directory: [binsize: 1 max: 65 count: 1 average: 65 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
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2009-05-11 19:38:46 +02:00
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All Non-Zero Cycle SW Prefetch Requests
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------------------------------------
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prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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Request vs. RubySystem State Profile
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--------------------------------
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filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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Message Delayed Cycles
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----------------------
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2010-05-06 22:41:08 +02:00
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Total_delay_cycles: [binsize: 1 max: 0 count: 2750 average: 0 | standard deviation: 0 | 2750 ]
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2009-05-11 19:38:46 +02:00
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virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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2010-05-06 22:41:08 +02:00
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virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 1377 average: 0 | standard deviation: 0 | 1377 ]
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virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 1373 average: 0 | standard deviation: 0 | 1373 ]
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2009-05-11 19:38:46 +02:00
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virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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2009-07-07 00:49:48 +02:00
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virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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2010-01-30 05:29:40 +01:00
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virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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2009-05-11 19:38:46 +02:00
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Resource Usage
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--------------
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page_size: 4096
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2010-01-30 05:29:40 +01:00
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user_time: 0
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2009-05-11 19:38:46 +02:00
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system_time: 0
|
2013-03-11 23:45:09 +01:00
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page_reclaims: 14769
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2013-01-14 17:20:16 +01:00
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page_faults: 0
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2009-05-11 19:38:46 +02:00
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swaps: 0
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2013-01-24 19:29:00 +01:00
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block_inputs: 0
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block_outputs: 88
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2009-05-11 19:38:46 +02:00
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Network Stats
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-------------
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2011-02-04 12:47:23 +01:00
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total_msg_count_Control: 4131 33048
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total_msg_count_Data: 4119 296568
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total_msg_count_Response_Data: 4131 297432
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total_msg_count_Writeback_Control: 4119 32952
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total_msgs: 16500 total_bytes: 660000
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2009-07-07 00:49:48 +02:00
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switch_0_inlinks: 2
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switch_0_outlinks: 2
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2012-09-10 19:44:03 +02:00
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links_utilized_percent_switch_0: 5.6464
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links_utilized_percent_switch_0_link_0: 5.65297 bw: 16000 base_latency: 1
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links_utilized_percent_switch_0_link_1: 5.63983 bw: 16000 base_latency: 1
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2009-05-11 19:38:46 +02:00
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2010-05-06 22:41:08 +02:00
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outgoing_messages_switch_0_link_0_Response_Data: 1377 99144 [ 0 0 0 0 1377 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_0_Writeback_Control: 1373 10984 [ 0 0 0 1373 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_1_Control: 1377 11016 [ 0 0 1377 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_1_Data: 1373 98856 [ 0 0 1373 0 0 0 0 0 0 0 ] base_latency: 1
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2009-05-11 19:38:46 +02:00
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2009-07-07 00:49:48 +02:00
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switch_1_inlinks: 2
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switch_1_outlinks: 2
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2012-09-10 19:44:03 +02:00
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links_utilized_percent_switch_1: 5.6464
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links_utilized_percent_switch_1_link_0: 5.63983 bw: 16000 base_latency: 1
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links_utilized_percent_switch_1_link_1: 5.65297 bw: 16000 base_latency: 1
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2009-05-11 19:38:46 +02:00
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2010-05-06 22:41:08 +02:00
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outgoing_messages_switch_1_link_0_Control: 1377 11016 [ 0 0 1377 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_0_Data: 1373 98856 [ 0 0 1373 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_1_Response_Data: 1377 99144 [ 0 0 0 0 1377 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_1_Writeback_Control: 1373 10984 [ 0 0 0 1373 0 0 0 0 0 0 ] base_latency: 1
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2009-05-11 19:38:46 +02:00
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switch_2_inlinks: 2
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switch_2_outlinks: 2
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2012-09-10 19:44:03 +02:00
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links_utilized_percent_switch_2: 5.6464
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links_utilized_percent_switch_2_link_0: 5.65297 bw: 16000 base_latency: 1
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links_utilized_percent_switch_2_link_1: 5.63983 bw: 16000 base_latency: 1
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2010-01-30 05:29:40 +01:00
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2010-05-06 22:41:08 +02:00
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outgoing_messages_switch_2_link_0_Response_Data: 1377 99144 [ 0 0 0 0 1377 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_0_Writeback_Control: 1373 10984 [ 0 0 0 1373 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_1_Control: 1377 11016 [ 0 0 1377 0 0 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_2_link_1_Data: 1373 98856 [ 0 0 1373 0 0 0 0 0 0 0 ] base_latency: 1
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2010-01-30 05:29:40 +01:00
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|
2013-01-14 17:20:16 +01:00
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|
Cache Stats: system.ruby.l1_cntrl0.cacheMemory
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system.ruby.l1_cntrl0.cacheMemory_total_misses: 1377
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|
system.ruby.l1_cntrl0.cacheMemory_total_demand_misses: 1377
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|
|
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|
system.ruby.l1_cntrl0.cacheMemory_total_prefetches: 0
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|
|
|
|
system.ruby.l1_cntrl0.cacheMemory_total_sw_prefetches: 0
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|
|
|
|
system.ruby.l1_cntrl0.cacheMemory_total_hw_prefetches: 0
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2013-01-14 17:20:16 +01:00
|
|
|
system.ruby.l1_cntrl0.cacheMemory_request_type_LD: 36.2382%
|
|
|
|
|
system.ruby.l1_cntrl0.cacheMemory_request_type_ST: 18.5185%
|
|
|
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|
system.ruby.l1_cntrl0.cacheMemory_request_type_IFETCH: 45.2433%
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2013-01-14 17:20:16 +01:00
|
|
|
system.ruby.l1_cntrl0.cacheMemory_access_mode_type_Supervisor: 1377 100%
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2011-02-04 12:47:23 +01:00
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|
|
--- L1Cache ---
|
2009-05-11 19:38:46 +02:00
|
|
|
- Event Counts -
|
2013-03-11 23:45:09 +01:00
|
|
|
Load [1045 ] 1045
|
2012-09-10 19:44:03 +02:00
|
|
|
Ifetch [6864 ] 6864
|
2012-12-30 19:45:52 +01:00
|
|
|
Store [943 ] 943
|
2011-02-04 12:47:23 +01:00
|
|
|
Data [1377 ] 1377
|
|
|
|
|
Fwd_GETX [0 ] 0
|
|
|
|
|
Inv [0 ] 0
|
|
|
|
|
Replacement [1373 ] 1373
|
|
|
|
|
Writeback_Ack [1373 ] 1373
|
|
|
|
|
Writeback_Nack [0 ] 0
|
2009-05-11 19:38:46 +02:00
|
|
|
|
|
|
|
|
- Transitions -
|
2011-02-08 04:23:13 +01:00
|
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|
I Load [499 ] 499
|
2011-02-04 12:47:23 +01:00
|
|
|
I Ifetch [623 ] 623
|
2011-02-08 04:23:13 +01:00
|
|
|
I Store [255 ] 255
|
2011-02-04 12:47:23 +01:00
|
|
|
I Inv [0 ] 0
|
|
|
|
|
I Replacement [0 ] 0
|
2009-07-07 00:49:48 +02:00
|
|
|
|
2011-02-04 12:47:23 +01:00
|
|
|
II Writeback_Nack [0 ] 0
|
2009-07-07 00:49:48 +02:00
|
|
|
|
2013-03-11 23:45:09 +01:00
|
|
|
M Load [546 ] 546
|
2012-09-10 19:44:03 +02:00
|
|
|
M Ifetch [6241 ] 6241
|
2012-12-30 19:45:52 +01:00
|
|
|
M Store [688 ] 688
|
2011-02-04 12:47:23 +01:00
|
|
|
M Fwd_GETX [0 ] 0
|
|
|
|
|
M Inv [0 ] 0
|
|
|
|
|
M Replacement [1373 ] 1373
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2011-02-04 12:47:23 +01:00
|
|
|
MI Fwd_GETX [0 ] 0
|
|
|
|
|
MI Inv [0 ] 0
|
|
|
|
|
MI Writeback_Ack [1373 ] 1373
|
|
|
|
|
MI Writeback_Nack [0 ] 0
|
2010-05-06 22:41:08 +02:00
|
|
|
|
2011-02-04 12:47:23 +01:00
|
|
|
MII Fwd_GETX [0 ] 0
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2011-02-08 04:23:13 +01:00
|
|
|
IS Data [1122 ] 1122
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2011-02-08 04:23:13 +01:00
|
|
|
IM Data [255 ] 255
|
2010-01-30 05:29:40 +01:00
|
|
|
|
2013-01-14 17:20:16 +01:00
|
|
|
Memory controller: system.ruby.dir_cntrl0.memBuffer:
|
2010-05-06 22:41:08 +02:00
|
|
|
memory_total_requests: 2750
|
|
|
|
|
memory_reads: 1377
|
|
|
|
|
memory_writes: 1373
|
2012-09-10 19:44:03 +02:00
|
|
|
memory_refreshes: 846
|
2013-03-11 23:45:09 +01:00
|
|
|
memory_total_request_delays: 1968
|
|
|
|
|
memory_delays_per_request: 0.715636
|
2012-09-10 19:44:03 +02:00
|
|
|
memory_delays_in_input_queue: 0
|
2013-03-11 23:45:09 +01:00
|
|
|
memory_delays_behind_head_of_bank_queue: 3
|
|
|
|
|
memory_delays_stalled_at_head_of_bank_queue: 1965
|
|
|
|
|
memory_stalls_for_bank_busy: 823
|
2010-01-30 05:29:40 +01:00
|
|
|
memory_stalls_for_random_busy: 0
|
|
|
|
|
memory_stalls_for_anti_starvation: 0
|
2013-03-11 23:45:09 +01:00
|
|
|
memory_stalls_for_arbitration: 65
|
|
|
|
|
memory_stalls_for_bus: 1044
|
2010-01-30 05:29:40 +01:00
|
|
|
memory_stalls_for_tfaw: 0
|
2013-03-11 23:45:09 +01:00
|
|
|
memory_stalls_for_read_write_turnaround: 33
|
2010-01-30 05:29:40 +01:00
|
|
|
memory_stalls_for_read_read_turnaround: 0
|
2010-05-06 22:41:08 +02:00
|
|
|
accesses_per_bank: 160 144 210 146 196 96 66 38 22 20 184 297 71 124 60 18 84 6 8 14 92 56 14 60 34 58 84 66 42 122 104 54
|
2009-05-11 19:38:46 +02:00
|
|
|
|
2011-02-04 12:47:23 +01:00
|
|
|
--- Directory ---
|
2009-05-11 19:38:46 +02:00
|
|
|
- Event Counts -
|
2011-02-04 12:47:23 +01:00
|
|
|
GETX [1377 ] 1377
|
|
|
|
|
GETS [0 ] 0
|
|
|
|
|
PUTX [1373 ] 1373
|
|
|
|
|
PUTX_NotOwner [0 ] 0
|
|
|
|
|
DMA_READ [0 ] 0
|
|
|
|
|
DMA_WRITE [0 ] 0
|
|
|
|
|
Memory_Data [1377 ] 1377
|
|
|
|
|
Memory_Ack [1373 ] 1373
|
2009-05-11 19:38:46 +02:00
|
|
|
|
|
|
|
|
- Transitions -
|
2011-02-04 12:47:23 +01:00
|
|
|
I GETX [1377 ] 1377
|
|
|
|
|
I PUTX_NotOwner [0 ] 0
|
|
|
|
|
I DMA_READ [0 ] 0
|
|
|
|
|
I DMA_WRITE [0 ] 0
|
|
|
|
|
|
|
|
|
|
M GETX [0 ] 0
|
|
|
|
|
M PUTX [1373 ] 1373
|
|
|
|
|
M PUTX_NotOwner [0 ] 0
|
|
|
|
|
M DMA_READ [0 ] 0
|
|
|
|
|
M DMA_WRITE [0 ] 0
|
|
|
|
|
|
|
|
|
|
M_DRD GETX [0 ] 0
|
|
|
|
|
M_DRD PUTX [0 ] 0
|
|
|
|
|
|
|
|
|
|
M_DWR GETX [0 ] 0
|
|
|
|
|
M_DWR PUTX [0 ] 0
|
|
|
|
|
|
|
|
|
|
M_DWRI GETX [0 ] 0
|
|
|
|
|
M_DWRI Memory_Ack [0 ] 0
|
|
|
|
|
|
|
|
|
|
M_DRDI GETX [0 ] 0
|
|
|
|
|
M_DRDI Memory_Ack [0 ] 0
|
|
|
|
|
|
|
|
|
|
IM GETX [0 ] 0
|
|
|
|
|
IM GETS [0 ] 0
|
|
|
|
|
IM PUTX [0 ] 0
|
|
|
|
|
IM PUTX_NotOwner [0 ] 0
|
|
|
|
|
IM DMA_READ [0 ] 0
|
|
|
|
|
IM DMA_WRITE [0 ] 0
|
|
|
|
|
IM Memory_Data [1377 ] 1377
|
|
|
|
|
|
|
|
|
|
MI GETX [0 ] 0
|
|
|
|
|
MI GETS [0 ] 0
|
|
|
|
|
MI PUTX [0 ] 0
|
|
|
|
|
MI PUTX_NotOwner [0 ] 0
|
|
|
|
|
MI DMA_READ [0 ] 0
|
|
|
|
|
MI DMA_WRITE [0 ] 0
|
|
|
|
|
MI Memory_Ack [1373 ] 1373
|
|
|
|
|
|
|
|
|
|
ID GETX [0 ] 0
|
|
|
|
|
ID GETS [0 ] 0
|
|
|
|
|
ID PUTX [0 ] 0
|
|
|
|
|
ID PUTX_NotOwner [0 ] 0
|
|
|
|
|
ID DMA_READ [0 ] 0
|
|
|
|
|
ID DMA_WRITE [0 ] 0
|
|
|
|
|
ID Memory_Data [0 ] 0
|
|
|
|
|
|
|
|
|
|
ID_W GETX [0 ] 0
|
|
|
|
|
ID_W GETS [0 ] 0
|
|
|
|
|
ID_W PUTX [0 ] 0
|
|
|
|
|
ID_W PUTX_NotOwner [0 ] 0
|
|
|
|
|
ID_W DMA_READ [0 ] 0
|
|
|
|
|
ID_W DMA_WRITE [0 ] 0
|
2012-01-10 16:59:01 +01:00
|
|
|
ID_W Memory_Ack [0 ] 0
|
|
|
|
|
|
