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40 commits

Author SHA1 Message Date
Frans Kaashoek 4714c20521 Checkpoint page-table version for SMP
Includes code for TLB shootdown (which actually seems unnecessary for xv6)
2010-07-23 07:41:13 -04:00
Frans Kaashoek 40889627ba Initial version of single-cpu xv6 with page tables 2010-07-02 14:51:53 -04:00
Russ Cox d26025d124 can set just %gs now. 2009-09-02 10:09:34 -07:00
Russ Cox 0aef891495 shuffle and tweak for formatting.
pdf has very good page breaks now.
would be a good copy for fall 2009.
2009-08-08 01:07:30 -07:00
rsc 7b644318dd clean up %fs %gs use 2009-05-31 01:12:08 +00:00
rsc 19333efb9e Some proc cleanup, moving some of copyproc into allocproc.
Also, an experiment: use "thread-local" storage for c and cp
instead of the #define macro for curproc[cpu()].
2009-05-31 00:28:45 +00:00
rsc 2157576107 be consistent: no underscores in function names 2009-03-08 22:07:13 +00:00
rsc c396d065d3 xv6/x86.h: add stosb, fix bugs in insl/outsl (rep not repne) 2009-03-08 21:27:57 +00:00
rsc 4003e9bed8 xv6/x86.h: inline assembly cleanup 2009-03-08 20:56:38 +00:00
kolya c7317d4dc7 always save and restore %fs, %gs to ensure old segment entries are never
accessible to user from the hidden CPU segment registers.
2008-09-24 01:48:31 +00:00
rsc 943fd378a1 Incorporate new understanding of/with Intel SMP spec.
Dropped cmpxchg in favor of xchg, to match lecture notes.

Use xchg to release lock, for future protection and to
keep gcc from acting clever.
2007-10-01 20:43:15 +00:00
rsc 9fd9f80431 Re: why cpuid() in locking code?
rtm wrote:
> Why does acquire() call cpuid()? Why does release() call cpuid()?

The cpuid in acquire is redundant with the cmpxchg, as you said.
I have removed the cpuid from acquire.

The cpuid in release is actually doing something important,
but not on the hardware.  It keeps gcc from reordering the
lock->locked assignment above the other two during optimization.
(Not that current gcc -O2 would choose to do that, but it is allowed to.)
I have replaced the cpuid in release with a "gcc barrier" that
keeps gcc from moving things around but has no hardware effect.

On a related note, I don't think the cpuid in mpmain is necessary,
for the same reason that the cpuid wasn't needed in release.

As to the question of whether

  acquire();
  x = protected;
  release();

might read protected after release(), I still haven't convinced
myself whether it can.  I'll put the cpuid back into release if
we determine that it can.

Russ
2007-09-30 14:30:04 +00:00
rsc c8919e6537 kernel SMP interruptibility fixes.
Last year, right before I sent xv6 to the printer, I changed the
SETGATE calls so that interrupts would be disabled on entry to
interrupt handlers, and I added the nlock++ / nlock-- in trap()
so that interrupts would stay disabled while the hw handlers
(but not the syscall handler) did their work.  I did this because
the kernel was otherwise causing Bochs to triple-fault in SMP
mode, and time was short.

Robert observed yesterday that something was keeping the SMP
preemption user test from working.  It turned out that when I
simplified the lapic code I swapped the order of two register
writes that I didn't realize were order dependent.  I fixed that
and then since I had everything paged in kept going and tried
to figure out why you can't leave interrupts on during interrupt
handlers.  There are a few issues.

First, there must be some way to keep interrupts from "stacking
up" and overflowing the stack.  Keeping interrupts off the whole
time solves this problem -- even if the clock tick handler runs
long enough that the next clock tick is waiting when it finishes,
keeping interrupts off means that the handler runs all the way
through the "iret" before the next handler begins.  This is not
really a problem unless you are putting too many prints in trap
-- if the OS is doing its job right, the handlers should run
quickly and not stack up.

Second, if xv6 had page faults, then it would be important to
keep interrupts disabled between the start of the interrupt and
the time that cr2 was read, to avoid a scenario like:

   p1 page faults [cr2 set to faulting address]
   p1 starts executing trapasm.S
   clock interrupt, p1 preempted, p2 starts executing
   p2 page faults [cr2 set to another faulting address]
   p2 starts, finishes fault handler
   p1 rescheduled, reads cr2, sees wrong fault address

Alternately p1 could be rescheduled on the other cpu, in which
case it would still see the wrong cr2.  That said, I think cr2
is the only interrupt state that isn't pushed onto the interrupt
stack atomically at fault time, and xv6 doesn't care.  (This isn't
entirely hypothetical -- I debugged this problem on Plan 9.)

Third, and this is the big one, it is not safe to call cpu()
unless interrupts are disabled.  If interrupts are enabled then
there is no guarantee that, between the time cpu() looks up the
cpu id and the time that it the result gets used, the process
has not been rescheduled to the other cpu.  For example, the
very commonly-used expression curproc[cpu()] (aka the macro cp)
can end up referring to the wrong proc: the code stores the
result of cpu() in %eax, gets rescheduled to the other cpu at
just the wrong instant, and then reads curproc[%eax].

We use curproc[cpu()] to get the current process a LOT.  In that
particular case, if we arranged for the current curproc entry
to be addressed by %fs:0 and just use a different %fs on each
CPU, then we could safely get at curproc even with interrupts
disabled, since the read of %fs would be atomic with the read
of %fs:0.  Alternately, we could have a curproc() function that
disables interrupts while computing curproc[cpu()].  I've done
that last one.

Even in the current kernel, with interrupts off on entry to trap,
interrupts are enabled inside release if there are no locks held.
Also, the scheduler's idle loop must be interruptible at times
so that the clock and disk interrupts (which might make processes
runnable) can be handled.

In addition to the rampant use of curproc[cpu()], this little
snippet from acquire is wrong on smp:

  if(cpus[cpu()].nlock == 0)
    cli();
  cpus[cpu()].nlock++;

because if interrupts are off then we might call cpu(), get
rescheduled to a different cpu, look at cpus[oldcpu].nlock, and
wrongly decide not to disable interrupts on the new cpu.  The
fix is to always call cli().  But this is wrong too:

  if(holding(lock))
    panic("acquire");
  cli();
  cpus[cpu()].nlock++;

because holding looks at cpu().  The fix is:

  cli();
  if(holding(lock))
    panic("acquire");
  cpus[cpu()].nlock++;

I've done that, and I changed cpu() to complain the first time
it gets called with interrupts disabled.  (It gets called too
much to complain every time.)

I added new functions splhi and spllo that are like acquire and
release but without the locking:

  void
  splhi(void)
  {
    cli();
    cpus[cpu()].nsplhi++;
  }

  void
  spllo(void)
  {
    if(--cpus[cpu()].nsplhi == 0)
      sti();
  }

and I've used those to protect other sections of code that refer
to cpu() when interrupts would otherwise be disabled (basically
just curproc and setupsegs).  I also use them in acquire/release
and got rid of nlock.

I'm not thrilled with the names, but I think the concept -- a
counted cli/sti -- is sound.  Having them also replaces the
nlock++/nlock-- in trap.c and main.c, which is nice.


Final note: it's still not safe to enable interrupts in
the middle of trap() between lapic_eoi and returning
to user space.  I don't understand why, but we get a
fault on pop %es because 0x10 is a bad segment
descriptor (!) and then the fault faults trying to go into
a new interrupt because 0x8 is a bad segment descriptor too!
Triple fault.  I haven't debugged this yet.
2007-09-27 12:58:42 +00:00
rtm ab4cedb593 continuous quality management 2007-08-31 19:55:27 +00:00
rsc 7bb73cdbc7 nits 2007-08-27 12:48:20 +00:00
rsc 68ae4cc127 comment what +m means; omit needless __ 2007-08-24 00:34:54 +00:00
rsc 2aae720537 omit needless ampersands 2007-08-24 00:02:03 +00:00
rsc ef30c2c749 no more w 2007-08-20 18:55:51 +00:00
rsc 64659055bd ditto 2007-08-14 04:06:02 +00:00
rsc 3163085ace Cannot use "g" as an arg constraint because
some memory references aren't actually valid
and gcc is a bit too smart in parsing (%0) and
a bit too dumb in knowing which memory refs
are not valid.  Using "r" seems to constrain gcc
to use a register as in (%eax) and not substitute
a memory reference like (-36(%ebp)).

No one really understands these things.
2007-08-14 04:05:27 +00:00
rsc 31085bb416 more comments 2006-09-07 14:12:30 +00:00
rsc f552738889 no /* */ comments 2006-09-06 17:50:20 +00:00
rsc 9e9bcaf143 standardize various * conventions 2006-09-06 17:27:19 +00:00
rsc a650c606fe spacing fixes: no tabs, 2-space indents (for rtm) 2006-09-06 17:04:06 +00:00
kaashoek 7abf49d2f2 remove duplication
don't use the same name for two different pieces of code
2006-09-03 15:39:29 +00:00
rtm 2b19190c13 clean up stale error checks and panics
delete unused functions
a few comments
2006-08-29 14:45:45 +00:00
rtm 8a8be1b8c3 low-level keyboard input (not hooked up to /dev yet)
fix acquire() to cli() *before* incrementing nlock
make T_SYSCALL a trap gate, not an interrupt gate
sadly, various crashes if you hold down a keyboard key...
2006-08-10 02:07:10 +00:00
rtm 2927081628 uint32_t -> uint &c 2006-07-20 09:07:53 +00:00
rsc b5f17007f4 standarize on unix-like lowercase struct names 2006-07-17 01:58:13 +00:00
rsc ee9c7f3bfc goodbye PushRegs 2006-07-17 01:36:39 +00:00
rsc 564f787e91 Eliminate annoying Pseudodesc structure.
Eliminate unnecessary parts of mmu.h.
2006-07-16 16:55:52 +00:00
rsc ef2bd07ae4 standardize on not using foo_ prefix in struct foo 2006-07-16 15:41:47 +00:00
rsc 65bd8e139a New scheduler.
Removed cli and sti stack in favor of tracking
number of locks held on each CPU and explicit
conditionals in spinlock.c.
2006-07-16 01:15:28 +00:00
rtm 8148b6ee53 i think my cmpxchg use was wrong in acquire
nesting cli/sti: release shouldn't always enable interrupts
separate setup of lapic from starting of other cpus, so cpu() works earlier
flag to disable locking in console output
make locks work even when curproc==0
(still crashes in clock interrupt)
2006-07-12 11:15:38 +00:00
rsc 5ce9751cab Changes to allow use of native x86 ELF compilers, which on my
Linux 2.4 box using gcc 3.4.6 don't seem to follow the same
conventions as the i386-jos-elf-gcc compilers.
Can run make 'TOOLPREFIX=' or edit the Makefile.

curproc[cpu()] can now be NULL, indicating that no proc is running.
This seemed safer to me than having curproc[0] and curproc[1]
both pointing at proc[0] potentially.

The old implementation of swtch depended on the stack frame layout
used inside swtch being okay to return from on the other stack
(exactly the V6 you are not expected to understand this).
It also could be called in two contexts: at boot time, to schedule
the very first process, and later, on behalf of a process, to sleep
or schedule some other process.

I split this into two functions: scheduler and swtch.

The scheduler is now a separate never-returning function, invoked
by each cpu once set up.  The scheduler looks like:

	scheduler() {
		setjmp(cpu.context);

		pick proc to schedule
		blah blah blah

		longjmp(proc.context)
	}

The new swtch is intended to be called only when curproc[cpu()] is not NULL,
that is, only on behalf of a user proc.  It does:

	swtch() {
		if(setjmp(proc.context) == 0)
			longjmp(cpu.context)
	}

to save the current proc context and then jump over to the scheduler,
running on the cpu stack.

Similarly the system call stubs are now in assembly in usys.S to avoid
needing to know the details of stack frame layout used by the compiler.

Also various changes in the debugging prints.
2006-07-11 01:07:40 +00:00
kaashoek 7837c71b32 disable all interrupts when acquiring lock
user program that makes a blocking system call
2006-07-06 21:47:22 +00:00
kaashoek b22d898297 timer interrupts
disk interrupts (assuming bochs has a bug)
2006-07-05 20:00:14 +00:00
rtm 8b4e2a08fe swtch saves callee-saved registers
swtch idles on per-CPU stack, not on calling process's stack
fix pipe bugs
usertest.c tests pipes, fork, exit, close
2006-07-01 21:26:01 +00:00
kaashoek 21a88fd487 checkpoint. booting second processor. stack is messed up, but thanks to cliff
and plan 9 code, at least boots and gets into C code.
2006-06-22 01:28:57 +00:00
rtm 55e95b16db import 2006-06-12 15:22:12 +00:00