9fd9f80431
rtm wrote: > Why does acquire() call cpuid()? Why does release() call cpuid()? The cpuid in acquire is redundant with the cmpxchg, as you said. I have removed the cpuid from acquire. The cpuid in release is actually doing something important, but not on the hardware. It keeps gcc from reordering the lock->locked assignment above the other two during optimization. (Not that current gcc -O2 would choose to do that, but it is allowed to.) I have replaced the cpuid in release with a "gcc barrier" that keeps gcc from moving things around but has no hardware effect. On a related note, I don't think the cpuid in mpmain is necessary, for the same reason that the cpuid wasn't needed in release. As to the question of whether acquire(); x = protected; release(); might read protected after release(), I still haven't convinced myself whether it can. I'll put the cpuid back into release if we determine that it can. Russ
175 lines
3.1 KiB
C
175 lines
3.1 KiB
C
// Routines to let C code use special x86 instructions.
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static inline uchar
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inb(ushort port)
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{
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uchar data;
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asm volatile("in %1,%0" : "=a" (data) : "d" (port));
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return data;
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}
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static inline void
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insl(int port, void *addr, int cnt)
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{
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asm volatile("cld\n\trepne\n\tinsl" :
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"=D" (addr), "=c" (cnt) :
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"d" (port), "0" (addr), "1" (cnt) :
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"memory", "cc");
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}
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static inline void
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outb(ushort port, uchar data)
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{
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asm volatile("out %0,%1" : : "a" (data), "d" (port));
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}
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static inline void
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outw(ushort port, ushort data)
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{
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asm volatile("out %0,%1" : : "a" (data), "d" (port));
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}
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static inline void
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outsl(int port, const void *addr, int cnt)
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{
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asm volatile("cld\n\trepne\n\toutsl" :
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"=S" (addr), "=c" (cnt) :
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"d" (port), "0" (addr), "1" (cnt) :
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"cc");
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}
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static inline uint
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read_ebp(void)
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{
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uint ebp;
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asm volatile("movl %%ebp, %0" : "=a" (ebp));
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return ebp;
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}
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struct segdesc;
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static inline void
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lgdt(struct segdesc *p, int size)
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{
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volatile ushort pd[3];
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pd[0] = size-1;
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pd[1] = (uint)p;
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pd[2] = (uint)p >> 16;
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asm volatile("lgdt (%0)" : : "r" (pd));
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}
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struct gatedesc;
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static inline void
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lidt(struct gatedesc *p, int size)
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{
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volatile ushort pd[3];
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pd[0] = size-1;
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pd[1] = (uint)p;
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pd[2] = (uint)p >> 16;
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asm volatile("lidt (%0)" : : "r" (pd));
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}
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static inline void
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ltr(ushort sel)
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{
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asm volatile("ltr %0" : : "r" (sel));
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}
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static inline uint
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read_eflags(void)
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{
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uint eflags;
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asm volatile("pushfl; popl %0" : "=r" (eflags));
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return eflags;
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}
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static inline void
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write_eflags(uint eflags)
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{
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asm volatile("pushl %0; popfl" : : "r" (eflags));
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}
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// XXX: Kill this if not used.
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static inline void
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cpuid(uint info, uint *eaxp, uint *ebxp, uint *ecxp, uint *edxp)
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{
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uint eax, ebx, ecx, edx;
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asm volatile("cpuid" :
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"=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) :
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"a" (info));
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if(eaxp)
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*eaxp = eax;
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if(ebxp)
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*ebxp = ebx;
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if(ecxp)
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*ecxp = ecx;
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if(edxp)
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*edxp = edx;
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}
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static inline uint
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cmpxchg(uint oldval, uint newval, volatile uint* lock_addr)
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{
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uint result;
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// The + in "+m" denotes a read-modify-write operand.
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asm volatile("lock; cmpxchgl %2, %0" :
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"+m" (*lock_addr), "=a" (result) :
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"r"(newval), "1"(oldval) :
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"cc");
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return result;
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}
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static inline void
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cli(void)
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{
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asm volatile("cli");
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}
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static inline void
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sti(void)
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{
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asm volatile("sti");
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}
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// Layout of the trap frame built on the stack by the
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// hardware and by trapasm.S, and passed to trap().
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struct trapframe {
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// registers as pushed by pusha
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uint edi;
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uint esi;
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uint ebp;
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uint oesp; // useless & ignored
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uint ebx;
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uint edx;
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uint ecx;
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uint eax;
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// rest of trap frame
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ushort es;
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ushort padding1;
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ushort ds;
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ushort padding2;
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uint trapno;
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// below here defined by x86 hardware
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uint err;
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uint eip;
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ushort cs;
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ushort padding3;
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uint eflags;
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// below here only when crossing rings, such as from user to kernel
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uint esp;
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ushort ss;
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ushort padding4;
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};
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