checkpoint. booting second processor. stack is messed up, but thanks to cliff
and plan 9 code, at least boots and gets into C code.
This commit is contained in:
kaashoek
parent
7baa34a421
commit
21a88fd487
10
Makefile
10
Makefile
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@ -1,5 +1,5 @@
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OBJS = main.o console.o string.o kalloc.o proc.o trapasm.o trap.o vectors.o \
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syscall.o ide.o picirq.o mp.o
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syscall.o ide.o picirq.o mp.o spinlock.o
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CC = i386-jos-elf-gcc
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LD = i386-jos-elf-ld
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@ -20,8 +20,12 @@ bootblock : bootasm.S bootmain.c
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$(OBJCOPY) -S -O binary bootblock.o bootblock
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./sign.pl bootblock
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kernel : $(OBJS)
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$(LD) -Ttext 0x100000 -e main -o kernel $(OBJS)
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kernel : $(OBJS) bootother.S
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$(CC) -nostdinc -I. -c bootother.S
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$(LD) -N -e start -Ttext 0x7000 -o bootother.out bootother.o
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$(OBJCOPY) -S -O binary bootother.out bootother
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$(OBJDUMP) -S bootother.o > bootother.asm
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$(LD) -Ttext 0x100000 -e main -o kernel $(OBJS) -b binary bootother
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$(OBJDUMP) -S kernel > kernel.asm
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vectors.S : vectors.pl
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15
bootasm.S
15
bootasm.S
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@ -1,17 +1,4 @@
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#define SEG_NULL \
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.word 0, 0; \
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.byte 0, 0, 0, 0
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#define SEG(type,base,lim) \
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.word (((lim) >> 12) & 0xffff), ((base) & 0xffff); \
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.byte (((base) >> 16) & 0xff), (0x90 | (type)), \
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(0xC0 | (((lim) >> 28) & 0xf)), (((base) >> 24) & 0xff)
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#define STA_X 0x8 // Executable segment
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#define STA_E 0x4 // Expand down (non-executable segments)
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#define STA_C 0x4 // Conforming code segment (executable only)
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#define STA_W 0x2 // Writeable (non-executable segments)
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#define STA_R 0x2 // Readable (executable segments)
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#define STA_A 0x1 // Accessed
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#include "asm.h"
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.set PROT_MODE_CSEG,0x8 # code segment selector
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.set PROT_MODE_DSEG,0x10 # data segment selector
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77
bootother.S
Normal file
77
bootother.S
Normal file
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@ -0,0 +1,77 @@
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#include "asm.h"
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/*
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* Start an Application Processor. This must be placed on a 4KB boundary
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* somewhere in the 1st MB of conventional memory (APBOOTSTRAP). However,
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* due to some shortcuts below it's restricted further to within the 1st
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* 64KB. The AP starts in real-mode, with
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* CS selector set to the startup memory address/16;
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* CS base set to startup memory address;
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* CS limit set to 64KB;
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* CPL and IP set to 0.
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*
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* Credit: Cliff Frey
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*/
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.set PROT_MODE_CSEG,0x8 # code segment selector
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.set PROT_MODE_DSEG,0x10 # data segment selector
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.set CR0_PE_ON,0x1 # protected mode enable flag
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.globl start
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start: .code16 # This runs in real mode
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cli # Disable interrupts
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cld # String operations increment
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# Set up the important data segment registers (DS, ES, SS).
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xorw %ax,%ax # Segment number zero
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movw %ax,%ds # -> Data Segment
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movw %ax,%es # -> Extra Segment
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movw %ax,%ss # -> Stack Segment
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# Set up the stack pointer, growing downward from 0x7000.
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movw $start,%sp # Stack Pointer
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#### Switch from real to protected mode
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#### The descriptors in our GDT allow all physical memory to be accessed.
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#### Furthermore, the descriptors have base addresses of 0, so that the
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#### segment translation is a NOP, ie. virtual addresses are identical to
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#### their physical addresses. With this setup, immediately after
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#### enabling protected mode it will still appear to this code
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#### that it is running directly on physical memory with no translation.
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#### This initial NOP-translation setup is required by the processor
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#### to ensure that the transition to protected mode occurs smoothly.
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lgdt gdtdesc # load GDT -- mandatory in protected mode
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movl %cr0, %eax # turn on protected mode
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orl $CR0_PE_ON, %eax #
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movl %eax, %cr0 #
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### CPU magic: jump to relocation, flush prefetch queue, and reload %cs
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### Has the effect of just jmp to the next instruction, but simultaneous
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### loads CS with $PROT_MODE_CSEG.
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ljmp $PROT_MODE_CSEG, $protcseg
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#### we are in 32-bit protected mode (hence the .code32)
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.code32
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protcseg:
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# Set up the protected-mode data segment registers
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movw $PROT_MODE_DSEG, %ax # Our data segment selector
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movw %ax, %ds # -> DS: Data Segment
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movw %ax, %es # -> ES: Extra Segment
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movw %ax, %fs # -> FS
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movw %ax, %gs # -> GS
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movw %ax, %ss # -> SS: Stack Segment
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# XXX hack
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movl 0x10018, %eax # elfhdr->entry (left over in scratch space)
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# subl $KERNBASE, %eax
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jmp *%eax # this jumps to _start in kern/entry.S
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.p2align 2 # force 4 byte alignment
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gdt:
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SEG_NULL # null seg
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SEG(STA_X|STA_R, 0x0, 0xffffffff) # code seg
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SEG(STA_W, 0x0, 0xffffffff) # data seg
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gdtdesc:
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.word 0x17 # sizeof(gdt) - 1
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.long gdt # address gdt
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11
defs.h
11
defs.h
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@ -22,6 +22,7 @@ void tinit(void);
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void * memcpy(void *dst, void *src, unsigned n);
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void * memset(void *dst, int c, unsigned n);
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int memcmp(const void *v1, const void *v2, unsigned n);
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void *memmove(void *dst, const void *src, unsigned n);
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// syscall.c
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void syscall(void);
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@ -31,5 +32,13 @@ void irq_setmask_8259A(uint16_t mask);
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void pic_init(void);
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// mp.c
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void mpinit(void);
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void mp_init(void);
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int lapic_cpu_number(void);
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int mp_isbcpu(void);
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// spinlock.c
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extern uint32_t kernel_lock;
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void acquire_spinlock(uint32_t* lock);
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void release_spinlock(uint32_t* lock);
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void release_grant_spinlock(uint32_t* lock, int cpu);
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11
main.c
11
main.c
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@ -8,6 +8,7 @@
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#include "syscall.h"
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extern char edata[], end[];
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extern int acpu;
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char buf[512];
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@ -16,13 +17,19 @@ main()
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{
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struct proc *p;
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int i;
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if (acpu) {
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cprintf("an application processor\n");
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release_spinlock(&kernel_lock);
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while (1) ;
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}
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acpu = 1;
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// clear BSS
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memset(edata, 0, end - edata);
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cprintf("\nxV6\n\n");
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mpinit(); // multiprocessor
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mp_init(); // multiprocessor
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kinit(); // physical memory allocator
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tinit(); // traps and interrupts
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pic_init();
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284
mp.c
284
mp.c
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@ -2,11 +2,201 @@
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#include "mp.h"
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#include "defs.h"
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#include "memlayout.h"
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#include "param.h"
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#include "x86.h"
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#include "mmu.h"
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static struct _MP_* _mp_; /* The MP floating point structure */
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/*
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* Credit: Plan 9 sources, Intel MP spec, and Cliff Frey
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*/
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enum { /* Local APIC registers */
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LAPIC_ID = 0x0020, /* ID */
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LAPIC_VER = 0x0030, /* Version */
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LAPIC_TPR = 0x0080, /* Task Priority */
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LAPIC_APR = 0x0090, /* Arbitration Priority */
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LAPIC_PPR = 0x00A0, /* Processor Priority */
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LAPIC_EOI = 0x00B0, /* EOI */
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LAPIC_LDR = 0x00D0, /* Logical Destination */
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LAPIC_DFR = 0x00E0, /* Destination Format */
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LAPIC_SVR = 0x00F0, /* Spurious Interrupt Vector */
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LAPIC_ISR = 0x0100, /* Interrupt Status (8 registers) */
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LAPIC_TMR = 0x0180, /* Trigger Mode (8 registers) */
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LAPIC_IRR = 0x0200, /* Interrupt Request (8 registers) */
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LAPIC_ESR = 0x0280, /* Error Status */
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LAPIC_ICRLO = 0x0300, /* Interrupt Command */
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LAPIC_ICRHI = 0x0310, /* Interrupt Command [63:32] */
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LAPIC_TIMER = 0x0320, /* Local Vector Table 0 (TIMER) */
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LAPIC_PCINT = 0x0340, /* Performance Counter LVT */
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LAPIC_LINT0 = 0x0350, /* Local Vector Table 1 (LINT0) */
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LAPIC_LINT1 = 0x0360, /* Local Vector Table 2 (LINT1) */
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LAPIC_ERROR = 0x0370, /* Local Vector Table 3 (ERROR) */
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LAPIC_TICR = 0x0380, /* Timer Initial Count */
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LAPIC_TCCR = 0x0390, /* Timer Current Count */
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LAPIC_TDCR = 0x03E0, /* Timer Divide Configuration */
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};
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enum { /* LAPIC_SVR */
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LAPIC_ENABLE = 0x00000100, /* Unit Enable */
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LAPIC_FOCUS = 0x00000200, /* Focus Processor Checking Disable */
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};
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enum { /* LAPIC_ICRLO */
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/* [14] IPI Trigger Mode Level (RW) */
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LAPIC_DEASSERT = 0x00000000, /* Deassert level-sensitive interrupt */
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LAPIC_ASSERT = 0x00004000, /* Assert level-sensitive interrupt */
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/* [17:16] Remote Read Status */
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LAPIC_INVALID = 0x00000000, /* Invalid */
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LAPIC_WAIT = 0x00010000, /* In-Progress */
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LAPIC_VALID = 0x00020000, /* Valid */
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/* [19:18] Destination Shorthand */
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LAPIC_FIELD = 0x00000000, /* No shorthand */
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LAPIC_SELF = 0x00040000, /* Self is single destination */
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LAPIC_ALLINC = 0x00080000, /* All including self */
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LAPIC_ALLEXC = 0x000C0000, /* All Excluding self */
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};
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enum { /* LAPIC_ESR */
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LAPIC_SENDCS = 0x00000001, /* Send CS Error */
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LAPIC_RCVCS = 0x00000002, /* Receive CS Error */
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LAPIC_SENDACCEPT = 0x00000004, /* Send Accept Error */
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LAPIC_RCVACCEPT = 0x00000008, /* Receive Accept Error */
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LAPIC_SENDVECTOR = 0x00000020, /* Send Illegal Vector */
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LAPIC_RCVVECTOR = 0x00000040, /* Receive Illegal Vector */
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LAPIC_REGISTER = 0x00000080, /* Illegal Register Address */
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};
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enum { /* LAPIC_TIMER */
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/* [17] Timer Mode (RW) */
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LAPIC_ONESHOT = 0x00000000, /* One-shot */
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LAPIC_PERIODIC = 0x00020000, /* Periodic */
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/* [19:18] Timer Base (RW) */
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LAPIC_CLKIN = 0x00000000, /* use CLKIN as input */
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LAPIC_TMBASE = 0x00040000, /* use TMBASE */
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LAPIC_DIVIDER = 0x00080000, /* use output of the divider */
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};
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enum { /* LAPIC_TDCR */
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LAPIC_X2 = 0x00000000, /* divide by 2 */
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LAPIC_X4 = 0x00000001, /* divide by 4 */
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LAPIC_X8 = 0x00000002, /* divide by 8 */
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LAPIC_X16 = 0x00000003, /* divide by 16 */
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LAPIC_X32 = 0x00000008, /* divide by 32 */
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LAPIC_X64 = 0x00000009, /* divide by 64 */
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LAPIC_X128 = 0x0000000A, /* divide by 128 */
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LAPIC_X1 = 0x0000000B, /* divide by 1 */
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};
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#define APBOOTCODE 0x7000 // XXX hack
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static struct MP* mp; /* The MP floating point structure */
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static uint32_t *lapicaddr;
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static struct cpu {
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uint8_t apicid; /* Local APIC ID */
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int lintr[2]; /* Local APIC */
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} cpu[NCPU];
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static int ncpu;
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static struct cpu *bcpu;
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static struct _MP_*
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static int
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lapic_read(int r)
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{
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return *(lapicaddr+(r/sizeof(*lapicaddr)));
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}
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static void
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lapic_write(int r, int data)
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{
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*(lapicaddr+(r/sizeof(*lapicaddr))) = data;
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}
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static void
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lapic_init(int c)
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{
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uint32_t r, lvt;
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cprintf("lapic_init %d\n", c);
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lapic_write(LAPIC_DFR, 0xFFFFFFFF);
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r = (lapic_read(LAPIC_ID)>>24) & 0xFF;
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lapic_write(LAPIC_LDR, (1<<r)<<24);
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lapic_write(LAPIC_TPR, 0xFF);
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lapic_write(LAPIC_SVR, LAPIC_ENABLE|(IRQ_OFFSET+IRQ_SPURIOUS));
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/*
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* Set the local interrupts. It's likely these should just be
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* masked off for SMP mode as some Pentium Pros have problems if
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* LINT[01] are set to ExtINT.
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* Acknowledge any outstanding interrupts.
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*/
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lapic_write(LAPIC_LINT0, cpu[c].lintr[0]);
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lapic_write(LAPIC_LINT1, cpu[c].lintr[1]);
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lapic_write(LAPIC_EOI, 0);
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lvt = (lapic_read(LAPIC_VER)>>16) & 0xFF;
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if(lvt >= 4)
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lapic_write(LAPIC_PCINT, APIC_IMASK);
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lapic_write(LAPIC_ERROR, IRQ_OFFSET+IRQ_ERROR);
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lapic_write(LAPIC_ESR, 0);
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lapic_read(LAPIC_ESR);
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/*
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* Issue an INIT Level De-Assert to synchronise arbitration ID's.
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*/
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lapic_write(LAPIC_ICRHI, 0);
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lapic_write(LAPIC_ICRLO, LAPIC_ALLINC|APIC_LEVEL|LAPIC_DEASSERT|APIC_INIT);
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while(lapic_read(LAPIC_ICRLO) & APIC_DELIVS)
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;
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/*
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* Do not allow acceptance of interrupts until all initialisation
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* for this processor is done. For the bootstrap processor this can be
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* early duing initialisation. For the application processors this should
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* be after the bootstrap processor has lowered priority and is accepting
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* interrupts.
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*/
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lapic_write(LAPIC_TPR, 0);
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cprintf("Done init of an apic\n");
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}
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static void
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lapic_online(void)
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{
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lapic_write(LAPIC_TPR, 0);
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}
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int
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lapic_cpu_number(void)
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{
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return (lapic_read(LAPIC_ID)>>24) & 0xFF;
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}
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static void
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lapic_startap(struct cpu *c, int v)
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{
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int crhi, i;
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volatile int j = 0;
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crhi = c->apicid<<24;
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lapic_write(LAPIC_ICRHI, crhi);
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lapic_write(LAPIC_ICRLO, LAPIC_FIELD|APIC_LEVEL|LAPIC_ASSERT|APIC_INIT);
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while (j++ < 10000) {;}
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lapic_write(LAPIC_ICRLO, LAPIC_FIELD|APIC_LEVEL|LAPIC_DEASSERT|APIC_INIT);
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while (j++ < 1000000) {;}
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// in p9 code, this was i < 2, which is what the spec says on page B-3
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for(i = 0; i < 1; i++){
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lapic_write(LAPIC_ICRHI, crhi);
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lapic_write(LAPIC_ICRLO, LAPIC_FIELD|APIC_EDGE|APIC_STARTUP|(v/PGSIZE));
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while (j++ < 100000) {;}
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}
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}
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static struct MP*
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mp_scan(uint8_t *addr, int len)
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{
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uint8_t *e, *p, sum;
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@ -14,24 +204,24 @@ mp_scan(uint8_t *addr, int len)
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cprintf("scanning: 0x%x\n", (uint32_t)addr);
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e = addr+len;
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for(p = addr; p < e; p += sizeof(struct _MP_)){
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for(p = addr; p < e; p += sizeof(struct MP)){
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if(memcmp(p, "_MP_", 4))
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continue;
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sum = 0;
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for(i = 0; i < sizeof(struct _MP_); i++)
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for(i = 0; i < sizeof(struct MP); i++)
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sum += p[i];
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if(sum == 0)
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return (struct _MP_ *)p;
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return (struct MP *)p;
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}
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return 0;
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}
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static struct _MP_*
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static struct MP*
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mp_search(void)
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{
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uint8_t *bda;
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uint32_t p;
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struct _MP_ *mp;
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struct MP *mp;
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/*
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* Search for the MP Floating Pointer Structure, which according to the
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@ -56,7 +246,7 @@ mp_search(void)
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static int
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mp_detect(void)
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{
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struct PCMP *pcmp;
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struct MPCTB *pcmp;
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uint8_t *p, sum;
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uint32_t length;
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@ -67,10 +257,10 @@ mp_detect(void)
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* if correct, check the version.
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* To do: check extended table checksum.
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*/
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if((_mp_ = mp_search()) == 0 || _mp_->physaddr == 0)
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if((mp = mp_search()) == 0 || mp->physaddr == 0)
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return 1;
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|
||||
pcmp = KADDR(_mp_->physaddr);
|
||||
pcmp = KADDR(mp->physaddr);
|
||||
if(memcmp(pcmp, "PCMP", 4))
|
||||
return 2;
|
||||
|
||||
|
|
@ -82,48 +272,65 @@ mp_detect(void)
|
|||
if(sum || (pcmp->version != 1 && pcmp->version != 4))
|
||||
return 3;
|
||||
|
||||
cprintf("MP spec rev #: %x\n", _mp_->specrev);
|
||||
cprintf("MP spec rev #: %x\n", mp->specrev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
mp_isbcpu()
|
||||
{
|
||||
if (bcpu == 0) return 1;
|
||||
else return 0;
|
||||
}
|
||||
|
||||
void
|
||||
mpinit()
|
||||
mp_init()
|
||||
{
|
||||
int r;
|
||||
uint8_t *p, *e;
|
||||
struct PCMP *pcmp;
|
||||
struct MPCTB *mpctb;
|
||||
struct MPPE *proc;
|
||||
struct cpu *c;
|
||||
|
||||
ncpu = 0;
|
||||
if ((r = mp_detect()) != 0) return;
|
||||
cprintf ("This computer is multiprocessor!\n");
|
||||
|
||||
cprintf ("This computer is a multiprocessor!\n");
|
||||
|
||||
/*
|
||||
* Run through the table saving information needed for starting
|
||||
* application processors and initialising any I/O APICs. The table
|
||||
* is guaranteed to be in order such that only one pass is necessary.
|
||||
*/
|
||||
pcmp = KADDR(_mp_->physaddr);
|
||||
p = ((uint8_t*)pcmp)+sizeof(struct PCMP);
|
||||
e = ((uint8_t*)pcmp)+pcmp->length;
|
||||
mpctb = KADDR(mp->physaddr);
|
||||
lapicaddr = KADDR(mpctb->lapicaddr);
|
||||
cprintf("apicaddr: %x\n", lapicaddr);
|
||||
p = ((uint8_t*)mpctb)+sizeof(struct MPCTB);
|
||||
e = ((uint8_t*)mpctb)+mpctb->length;
|
||||
|
||||
while(p < e) {
|
||||
switch(*p){
|
||||
case PcmpPROCESSOR:
|
||||
cprintf("a processor\n");
|
||||
case MPPROCESSOR:
|
||||
proc = (struct MPPE *) p;
|
||||
cpu[ncpu].apicid = proc->apicid;
|
||||
cpu[ncpu].lintr[0] = APIC_IMASK;
|
||||
cpu[ncpu].lintr[1] = APIC_IMASK;
|
||||
cprintf("a processor %x\n", cpu[ncpu].apicid);
|
||||
if (proc->flags & MPBP) {
|
||||
bcpu = &cpu[ncpu];
|
||||
}
|
||||
ncpu++;
|
||||
p += sizeof(struct PCMPprocessor);
|
||||
p += sizeof(struct MPPE);
|
||||
continue;
|
||||
case PcmpBUS:
|
||||
cprintf("a bus\n");
|
||||
p += sizeof(struct PCMPbus);
|
||||
case MPBUS:
|
||||
p += sizeof(struct MPBE);
|
||||
continue;
|
||||
case PcmpIOAPIC:
|
||||
cprintf("an IO APIC\n");
|
||||
p += sizeof(struct PCMPioapic);
|
||||
case MPIOAPIC:
|
||||
cprintf("an I/O APIC\n");
|
||||
p += sizeof(struct MPIOAPIC);
|
||||
continue;
|
||||
case PcmpIOINTR:
|
||||
cprintf("an IO interrupt assignment\n");
|
||||
p += sizeof(struct PCMPintr);
|
||||
case MPIOINTR:
|
||||
p += sizeof(struct MPIE);
|
||||
continue;
|
||||
default:
|
||||
cprintf("mpinit: unknown PCMP type 0x%x (e-p 0x%x)\n", *p, e-p);
|
||||
|
|
@ -134,6 +341,23 @@ mpinit()
|
|||
break;
|
||||
}
|
||||
}
|
||||
|
||||
lapic_init(cpu-bcpu);
|
||||
cprintf("ncpu: %d boot %d\n", ncpu, cpu-bcpu);
|
||||
|
||||
cprintf("ncpu: %d\n", ncpu);
|
||||
lapic_online();
|
||||
|
||||
extern uint8_t _binary_bootother_start[], _binary_bootother_size[];
|
||||
memmove(KADDR(APBOOTCODE),_binary_bootother_start,
|
||||
(uint32_t) _binary_bootother_size);
|
||||
|
||||
acquire_spinlock(&kernel_lock);
|
||||
for (c = cpu; c < &cpu[ncpu]; c++) {
|
||||
if (c == bcpu) continue;
|
||||
cprintf ("starting processor %d\n", c - cpu);
|
||||
release_grant_spinlock(&kernel_lock, c - cpu);
|
||||
lapic_startap(c, (uint32_t) KADDR(APBOOTCODE));
|
||||
acquire_spinlock(&kernel_lock);
|
||||
cprintf ("done starting processor %d\n", c - cpu);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
138
mp.h
138
mp.h
|
|
@ -1,7 +1,10 @@
|
|||
/*
|
||||
* MultiProcessor Specification Version 1.[14].
|
||||
*
|
||||
* Credit: Plan 9 sources
|
||||
*/
|
||||
struct _MP_ { /* floating pointer */
|
||||
|
||||
struct MP { /* floating pointer */
|
||||
uint8_t signature[4]; /* "_MP_" */
|
||||
physaddr_t physaddr; /* physical address of MP configuration table */
|
||||
uint8_t length; /* 1 */
|
||||
|
|
@ -12,7 +15,7 @@ struct _MP_ { /* floating pointer */
|
|||
uint8_t reserved[3];
|
||||
};
|
||||
|
||||
struct PCMP { /* configuration table header */
|
||||
struct MPCTB { /* configuration table header */
|
||||
uint8_t signature[4]; /* "PCMP" */
|
||||
uint16_t length; /* total table length */
|
||||
uint8_t version; /* [14] */
|
||||
|
|
@ -21,15 +24,15 @@ struct PCMP { /* configuration table header */
|
|||
uintptr_t oemtable; /* OEM table pointer */
|
||||
uint16_t oemlength; /* OEM table length */
|
||||
uint16_t entry; /* entry count */
|
||||
uintptr_t lapicbase; /* address of local APIC */
|
||||
uintptr_t lapicaddr; /* address of local APIC */
|
||||
uint16_t xlength; /* extended table length */
|
||||
uint8_t xchecksum; /* extended table checksum */
|
||||
uint8_t reserved;
|
||||
};
|
||||
|
||||
struct PCMPprocessor { /* processor table entry */
|
||||
struct MPPE { /* processor table entry */
|
||||
uint8_t type; /* entry type (0) */
|
||||
uint8_t apicno; /* local APIC id */
|
||||
uint8_t apicid; /* local APIC id */
|
||||
uint8_t version; /* local APIC verison */
|
||||
uint8_t flags; /* CPU flags */
|
||||
uint8_t signature[4]; /* CPU signature */
|
||||
|
|
@ -37,13 +40,13 @@ struct PCMPprocessor { /* processor table entry */
|
|||
uint8_t reserved[8];
|
||||
};
|
||||
|
||||
struct PCMPbus { /* bus table entry */
|
||||
struct MPBE { /* bus table entry */
|
||||
uint8_t type; /* entry type (1) */
|
||||
uint8_t busno; /* bus id */
|
||||
char string[6]; /* bus type string */
|
||||
};
|
||||
|
||||
struct PCMPioapic { /* I/O APIC table entry */
|
||||
struct MPIOAPIC { /* I/O APIC table entry */
|
||||
uint8_t type; /* entry type (2) */
|
||||
uint8_t apicno; /* I/O APIC id */
|
||||
uint8_t version; /* I/O APIC version */
|
||||
|
|
@ -51,7 +54,7 @@ struct PCMPioapic { /* I/O APIC table entry */
|
|||
uintptr_t addr; /* I/O APIC address */
|
||||
};
|
||||
|
||||
struct PCMPintr { /* interrupt table entry */
|
||||
struct MPIE { /* interrupt table entry */
|
||||
uint8_t type; /* entry type ([34]) */
|
||||
uint8_t intr; /* interrupt type */
|
||||
uint16_t flags; /* interrupt flag */
|
||||
|
|
@ -61,71 +64,34 @@ struct PCMPintr { /* interrupt table entry */
|
|||
uint8_t intin; /* destination APIC [L]INTIN# */
|
||||
};
|
||||
|
||||
struct PCMPsasm { /* system address space mapping entry */
|
||||
uint8_t type; /* entry type (128) */
|
||||
uint8_t length; /* of this entry (20) */
|
||||
uint8_t busno; /* bus id */
|
||||
uint8_t addrtype;
|
||||
uintptr_t addrbase[2];
|
||||
uint32_t addrlength[2];
|
||||
};
|
||||
enum { /* table entry types */
|
||||
MPPROCESSOR = 0x00, /* one entry per processor */
|
||||
MPBUS = 0x01, /* one entry per bus */
|
||||
MPIOAPIC = 0x02, /* one entry per I/O APIC */
|
||||
MPIOINTR = 0x03, /* one entry per bus interrupt source */
|
||||
MPLINTR = 0x04, /* one entry per system interrupt source */
|
||||
|
||||
struct PCMPhierarchy { /* bus hierarchy descriptor entry */
|
||||
uint8_t type; /* entry type (129) */
|
||||
uint8_t length; /* of this entry (8) */
|
||||
uint8_t busno; /* bus id */
|
||||
uint8_t info; /* bus info */
|
||||
uint8_t parent; /* parent bus */
|
||||
uint8_t reserved[3];
|
||||
};
|
||||
MPSASM = 0x80,
|
||||
MPHIERARCHY = 0x81,
|
||||
MPCBASM = 0x82,
|
||||
|
||||
struct PCMPcbasm { /* compatibility bus address space modifier entry */
|
||||
uint8_t type; /* entry type (130) */
|
||||
uint8_t length; /* of this entry (8) */
|
||||
uint8_t busno; /* bus id */
|
||||
uint8_t modifier; /* address modifier */
|
||||
uint32_t range; /* predefined range list */
|
||||
};
|
||||
/* PCMPprocessor and PCMPioapic flags */
|
||||
MPEN = 0x01, /* enabled */
|
||||
MPBP = 0x02, /* bootstrap processor */
|
||||
|
||||
enum { /* table entry types */
|
||||
PcmpPROCESSOR = 0x00, /* one entry per processor */
|
||||
PcmpBUS = 0x01, /* one entry per bus */
|
||||
PcmpIOAPIC = 0x02, /* one entry per I/O APIC */
|
||||
PcmpIOINTR = 0x03, /* one entry per bus interrupt source */
|
||||
PcmpLINTR = 0x04, /* one entry per system interrupt source */
|
||||
/* PCMPiointr and PCMPlintr flags */
|
||||
MPPOMASK = 0x03, /* polarity conforms to specifications of bus */
|
||||
MPHIGH = 0x01, /* active high */
|
||||
MPLOW = 0x03, /* active low */
|
||||
MPELMASK = 0x0C, /* trigger mode of APIC input signals */
|
||||
MPEDGE = 0x04, /* edge-triggered */
|
||||
MPLEVEL = 0x0C, /* level-triggered */
|
||||
|
||||
PcmpSASM = 0x80,
|
||||
PcmpHIERARCHY = 0x81,
|
||||
PcmpCBASM = 0x82,
|
||||
|
||||
/* PCMPprocessor and PCMPioapic flags */
|
||||
PcmpEN = 0x01, /* enabled */
|
||||
PcmpBP = 0x02, /* bootstrap processor */
|
||||
|
||||
/* PCMPiointr and PCMPlintr flags */
|
||||
PcmpPOMASK = 0x03, /* polarity conforms to specifications of bus */
|
||||
PcmpHIGH = 0x01, /* active high */
|
||||
PcmpLOW = 0x03, /* active low */
|
||||
PcmpELMASK = 0x0C, /* trigger mode of APIC input signals */
|
||||
PcmpEDGE = 0x04, /* edge-triggered */
|
||||
PcmpLEVEL = 0x0C, /* level-triggered */
|
||||
|
||||
/* PCMPiointr and PCMPlintr interrupt type */
|
||||
PcmpINT = 0x00, /* vectored interrupt from APIC Rdt */
|
||||
PcmpNMI = 0x01, /* non-maskable interrupt */
|
||||
PcmpSMI = 0x02, /* system management interrupt */
|
||||
PcmpExtINT = 0x03, /* vectored interrupt from external PIC */
|
||||
|
||||
/* PCMPsasm addrtype */
|
||||
PcmpIOADDR = 0x00, /* I/O address */
|
||||
PcmpMADDR = 0x01, /* memory address */
|
||||
PcmpPADDR = 0x02, /* prefetch address */
|
||||
|
||||
/* PCMPhierarchy info */
|
||||
PcmpSD = 0x01, /* subtractive decode bus */
|
||||
|
||||
/* PCMPcbasm modifier */
|
||||
PcmpPR = 0x01, /* predefined range list */
|
||||
/* PCMPiointr and PCMPlintr interrupt type */
|
||||
MPINT = 0x00, /* vectored interrupt from APIC Rdt */
|
||||
MPNMI = 0x01, /* non-maskable interrupt */
|
||||
MPSMI = 0x02, /* system management interrupt */
|
||||
MPExtINT = 0x03, /* vectored interrupt from external PIC */
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -136,23 +102,23 @@ enum { /* table entry types */
|
|||
* Local APIC Timer Vector Table.
|
||||
*/
|
||||
enum {
|
||||
ApicFIXED = 0x00000000, /* [10:8] Delivery Mode */
|
||||
ApicLOWEST = 0x00000100, /* Lowest priority */
|
||||
ApicSMI = 0x00000200, /* System Management Interrupt */
|
||||
ApicRR = 0x00000300, /* Remote Read */
|
||||
ApicNMI = 0x00000400,
|
||||
ApicINIT = 0x00000500, /* INIT/RESET */
|
||||
ApicSTARTUP = 0x00000600, /* Startup IPI */
|
||||
ApicExtINT = 0x00000700,
|
||||
APIC_FIXED = 0x00000000, /* [10:8] Delivery Mode */
|
||||
APIC_LOWEST = 0x00000100, /* Lowest priority */
|
||||
APIC_SMI = 0x00000200, /* System Management Interrupt */
|
||||
APIC_RR = 0x00000300, /* Remote Read */
|
||||
APIC_NMI = 0x00000400,
|
||||
APIC_INIT = 0x00000500, /* INIT/RESET */
|
||||
APIC_STARTUP = 0x00000600, /* Startup IPI */
|
||||
APIC_ExtINT = 0x00000700,
|
||||
|
||||
ApicPHYSICAL = 0x00000000, /* [11] Destination Mode (RW) */
|
||||
ApicLOGICAL = 0x00000800,
|
||||
APIC_PHYSICAL = 0x00000000, /* [11] Destination Mode (RW) */
|
||||
APIC_LOGICAL = 0x00000800,
|
||||
|
||||
ApicDELIVS = 0x00001000, /* [12] Delivery Status (RO) */
|
||||
ApicHIGH = 0x00000000, /* [13] Interrupt Input Pin Polarity (RW) */
|
||||
ApicLOW = 0x00002000,
|
||||
ApicRemoteIRR = 0x00004000, /* [14] Remote IRR (RO) */
|
||||
ApicEDGE = 0x00000000, /* [15] Trigger Mode (RW) */
|
||||
ApicLEVEL = 0x00008000,
|
||||
ApicIMASK = 0x00010000, /* [16] Interrupt Mask */
|
||||
APIC_DELIVS = 0x00001000, /* [12] Delivery Status (RO) */
|
||||
APIC_HIGH = 0x00000000, /* [13] Interrupt Input Pin Polarity (RW) */
|
||||
APIC_LOW = 0x00002000,
|
||||
APIC_RemoteIRR = 0x00004000, /* [14] Remote IRR (RO) */
|
||||
APIC_EDGE = 0x00000000, /* [15] Trigger Mode (RW) */
|
||||
APIC_LEVEL = 0x00008000,
|
||||
APIC_IMASK = 0x00010000, /* [16] Interrupt Mask */
|
||||
};
|
||||
|
|
|
|||
1
param.h
1
param.h
|
|
@ -1,3 +1,4 @@
|
|||
#define NPROC 64
|
||||
#define PAGE 4096
|
||||
#define KSTACKSIZE PAGE
|
||||
#define NCPU 8
|
||||
|
|
|
|||
9
picirq.c
9
picirq.c
|
|
@ -4,15 +4,6 @@
|
|||
#include "x86.h"
|
||||
#include "defs.h"
|
||||
|
||||
#define MAX_IRQS 16 // Number of IRQs
|
||||
|
||||
// I/O Addresses of the two 8259A programmable interrupt controllers
|
||||
#define IO_PIC1 0x20 // Master (IRQs 0-7)
|
||||
#define IO_PIC2 0xA0 // Slave (IRQs 8-15)
|
||||
|
||||
#define IRQ_SLAVE 2 // IRQ at which slave connects to master
|
||||
#define IRQ_OFFSET 32 // IRQ 0 corresponds to int IRQ_OFFSET
|
||||
|
||||
// Current IRQ mask.
|
||||
// Initial IRQ mask has interrupt 2 enabled (for slave 8259A).
|
||||
uint16_t irq_mask_8259A = 0xFFFF & ~(1<<IRQ_SLAVE);
|
||||
|
|
|
|||
39
spinlock.c
Normal file
39
spinlock.c
Normal file
|
|
@ -0,0 +1,39 @@
|
|||
#include "types.h"
|
||||
#include "defs.h"
|
||||
#include "x86.h"
|
||||
|
||||
#define LOCK_FREE -1
|
||||
|
||||
uint32_t kernel_lock = LOCK_FREE;
|
||||
|
||||
// lock = LOCK_FREE if free, else = cpu_id of owner CPU
|
||||
void
|
||||
acquire_spinlock(uint32_t* lock)
|
||||
{
|
||||
int cpu_id = lapic_cpu_number();
|
||||
cprintf ("acquire: %d\n", cpu_id);
|
||||
|
||||
if (*lock == cpu_id)
|
||||
return;
|
||||
while ( cmpxchg(LOCK_FREE, cpu_id, lock) != cpu_id ) { ; }
|
||||
}
|
||||
|
||||
void
|
||||
release_spinlock(uint32_t* lock)
|
||||
{
|
||||
int cpu_id = lapic_cpu_number();
|
||||
cprintf ("release: %d\n", cpu_id);
|
||||
if (*lock != cpu_id)
|
||||
panic("release_spinlock: releasing a lock that i don't own\n");
|
||||
*lock = LOCK_FREE;
|
||||
}
|
||||
|
||||
void
|
||||
release_grant_spinlock(uint32_t* lock, int c)
|
||||
{
|
||||
int cpu_id = lapic_cpu_number();
|
||||
cprintf ("release_grant: %d -> %d\n", cpu_id, c);
|
||||
if (*lock != cpu_id)
|
||||
panic("release_spinlock: releasing a lock that i don't own\n");
|
||||
*lock = c;
|
||||
}
|
||||
20
string.c
20
string.c
|
|
@ -38,3 +38,23 @@ memcmp(const void *v1, const void *v2, unsigned n)
|
|||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void *
|
||||
memmove(void *dst, const void *src, unsigned n)
|
||||
{
|
||||
const char *s;
|
||||
char *d;
|
||||
|
||||
s = src;
|
||||
d = dst;
|
||||
if (s < d && s + n > d) {
|
||||
s += n;
|
||||
d += n;
|
||||
while (n-- > 0)
|
||||
*--d = *--s;
|
||||
} else
|
||||
while (n-- > 0)
|
||||
*d++ = *s++;
|
||||
|
||||
return dst;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -27,3 +27,8 @@ trapret:
|
|||
popl %ds
|
||||
addl $0x8, %esp /* trapno and errcode */
|
||||
iret
|
||||
|
||||
|
||||
.globl acpu
|
||||
acpu:
|
||||
.long 0
|
||||
|
|
|
|||
24
x86.h
24
x86.h
|
|
@ -261,6 +261,17 @@ cpuid(uint32_t info, uint32_t *eaxp, uint32_t *ebxp, uint32_t *ecxp, uint32_t *e
|
|||
*edxp = edx;
|
||||
}
|
||||
|
||||
static __inline uint32_t
|
||||
cmpxchg(uint32_t oldval, uint32_t newval, volatile uint32_t* lock_addr)
|
||||
{
|
||||
uint32_t result;
|
||||
__asm__ __volatile__(
|
||||
"lock; cmpxchgl %2, %0"
|
||||
:"+m" (*lock_addr), "=a" (result) : "r"(newval), "1"(oldval) : "cc"
|
||||
);
|
||||
return result;
|
||||
}
|
||||
|
||||
static __inline uint64_t
|
||||
read_tsc(void)
|
||||
{
|
||||
|
|
@ -299,3 +310,16 @@ struct Trapframe {
|
|||
uint16_t tf_ss;
|
||||
uint16_t tf_padding4;
|
||||
};
|
||||
|
||||
|
||||
#define MAX_IRQS 16 // Number of IRQs
|
||||
|
||||
// I/O Addresses of the two 8259A programmable interrupt controllers
|
||||
#define IO_PIC1 0x20 // Master (IRQs 0-7)
|
||||
#define IO_PIC2 0xA0 // Slave (IRQs 8-15)
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||||
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||||
#define IRQ_SLAVE 2 // IRQ at which slave connects to master
|
||||
#define IRQ_OFFSET 32 // IRQ 0 corresponds to int IRQ_OFFSET
|
||||
|
||||
#define IRQ_ERROR 19
|
||||
#define IRQ_SPURIOUS 31
|
||||
|
|
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|||
Loading…
Reference in a new issue