gem5/src/mem
Nilay Vaish 45b411fc5f Ruby: Commit files missing from previous commit
The previous commit on functional access support in Ruby did not have
some of the files required. This patch adds those files to the repository.
2011-07-01 16:29:33 -05:00
..
cache scons: rename TraceFlags to DebugFlags 2011-06-02 17:36:21 -07:00
config Fixes to get prefetching working again. 2009-02-16 08:56:40 -08:00
protocol Ruby: Add support for functional accesses 2011-06-30 19:49:26 -05:00
ruby Ruby: Commit files missing from previous commit 2011-07-01 16:29:33 -05:00
slicc Ruby: Add support for functional accesses 2011-06-30 19:49:26 -05:00
bridge.cc trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
bridge.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
Bridge.py DMA: Add IOCache and fix bus bridge to optionally only send requests one 2007-08-10 16:14:01 -04:00
bus.cc trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
bus.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
Bus.py bus: clean up default responder code. 2010-08-17 05:06:21 -07:00
dram.cc Replace curTick global variable with accessor functions. 2011-01-07 21:50:29 -08:00
dram.hh stats: Fix all stats usages to deal with template fixes 2009-03-05 19:09:53 -08:00
mem_object.cc params: Get rid of the remnants of the old style parameter configuration stuff. 2008-08-11 12:22:17 -07:00
mem_object.hh params: Get rid of the remnants of the old style parameter configuration stuff. 2008-08-11 12:22:17 -07:00
MemObject.py Major changes to how SimObjects are created and initialized. Almost all 2007-07-23 21:51:38 -07:00
mport.cc Replace curTick global variable with accessor functions. 2011-01-07 21:50:29 -08:00
mport.hh Create a message port for sending messages as apposed to reading/writing a memory range. 2008-10-12 12:08:51 -07:00
packet.cc Ruby: Add support for functional accesses 2011-06-30 19:49:26 -05:00
packet.hh Ruby: Add support for functional accesses 2011-06-30 19:49:26 -05:00
packet_access.hh arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh 2009-09-23 08:34:21 -07:00
page_table.cc trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
page_table.hh Faults: Pass the StaticInst involved, if any, to a Fault's invoke method. 2010-09-13 19:26:03 -07:00
physical.cc Mem: Use sysconf to get the page size instead of the PAGE_SIZE macro. 2011-06-08 00:57:50 -07:00
physical.hh SE: Fix simulating more than 4GB of RAM in SE mode 2010-11-19 18:01:01 -06:00
PhysicalMemory.py Make default PhysicalMemory latency slightly more realistic. 2008-08-03 18:13:29 -04:00
port.cc trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
port.hh types: clean up types, especially signed vs unsigned 2009-06-04 23:21:12 -07:00
port_impl.hh arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh 2009-09-23 08:34:21 -07:00
request.hh Spelling: Fix the a spelling error by changing mmaped to mmapped. 2011-03-01 23:18:47 -08:00
SConscript scons: rename TraceFlags to DebugFlags 2011-06-02 17:36:21 -07:00
tport.cc trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
tport.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
translating_port.cc includes: sort all includes 2011-04-15 10:44:06 -07:00
translating_port.hh fix the translating ports so it can add a page on a fault 2007-05-09 15:37:46 -04:00
vport.cc arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh 2009-09-23 08:34:21 -07:00
vport.hh includes: sort all includes 2011-04-15 10:44:06 -07:00