..
insts
ARM: fix bits-to-fp conversion function declarations.
2012-03-01 17:26:30 -06:00
isa
Merge with head, hopefully the last time for this batch.
2012-01-31 22:40:08 -08:00
linux
MEM: Make port proxies use references rather than pointers
2012-02-24 11:45:30 -05:00
ArmInterrupts.py
ARM: Boilerplate full-system code.
2009-11-17 18:02:08 -06:00
ArmNativeTrace.py
ARM: Make the ARM native tracer stop M5 if control diverges.
2009-07-29 00:17:11 -07:00
ArmSystem.py
ARM: Add VExpress_E support with PCIe to gem5
2011-08-19 15:08:08 -05:00
ArmTLB.py
MEM: Introduce the master/slave port roles in the Python classes
2012-02-13 06:43:09 -05:00
faults.cc
Implement Ali's review feedback.
2012-01-29 02:04:34 -08:00
faults.hh
SE/FS: Get rid of FULL_SYSTEM in the ARM ISA.
2011-11-02 01:25:15 -07:00
interrupts.cc
ARM: Implement ARM CPU interrupts
2010-06-02 12:58:16 -05:00
interrupts.hh
Fix bugs due to interaction between SEV instructions and O3 pipeline
2011-08-19 15:08:07 -05:00
intregs.hh
ARM: Further break up condition code into NZ, C, V bits.
2011-05-13 17:27:01 -05:00
isa.cc
mem: Add a master ID to each request object.
2012-02-12 16:07:38 -06:00
isa.hh
trace: reimplement the DTRACE function so it doesn't use a vector
2011-04-15 10:44:32 -07:00
isa_traits.hh
StaticInst: Merge StaticInst and StaticInstBase.
2011-09-09 02:40:11 -07:00
kernel_stats.hh
Make commenting on close namespace brackets consistent.
2011-01-03 14:35:43 -08:00
locked_mem.hh
includes: sort all includes
2011-04-15 10:44:06 -07:00
microcode_rom.hh
arm: include missing file for arm
2009-04-21 15:40:26 -07:00
miscregs.cc
clang: Enable compiling gem5 using clang 2.9 and 3.0
2012-01-31 12:05:52 -05:00
miscregs.hh
ARM: update TLB to set request packet ASID field
2011-09-13 12:06:13 -05:00
mmapped_ipr.hh
Spelling: Fix the a spelling error by changing mmaped to mmapped.
2011-03-01 23:18:47 -08:00
nativetrace.cc
gcc: fix unused variable warnings from GCC 4.6.1
2011-12-13 11:49:27 -08:00
nativetrace.hh
ARM: Add vfpv3 support to native trace.
2011-05-04 20:38:26 -05:00
pagetable.hh
SE/FS: Get rid of includes of config/full_system.hh.
2011-11-18 02:20:22 -08:00
predecoder.cc
trace: reimplement the DTRACE function so it doesn't use a vector
2011-04-15 10:44:32 -07:00
predecoder.hh
includes: sort all includes
2011-04-15 10:44:06 -07:00
process.cc
MEM: Make port proxies use references rather than pointers
2012-02-24 11:45:30 -05:00
process.hh
includes: sort all includes
2011-04-15 10:44:06 -07:00
registers.hh
includes: sort all includes
2011-04-15 10:44:06 -07:00
remote_gdb.cc
SE/FS: Get rid of FULL_SYSTEM in the ARM ISA.
2011-11-02 01:25:15 -07:00
remote_gdb.hh
ARM: Add support for GDB on ARM
2010-11-15 14:04:03 -06:00
SConscript
SE/FS: Get rid of FULL_SYSTEM in the ARM ISA.
2011-11-02 01:25:15 -07:00
SConsopts
arm: add ARM support to M5
2009-04-05 18:53:15 -07:00
stacktrace.cc
MEM: Make port proxies use references rather than pointers
2012-02-24 11:45:30 -05:00
stacktrace.hh
trace: reimplement the DTRACE function so it doesn't use a vector
2011-04-15 10:44:32 -07:00
system.cc
ARM: move kernel func event to correct location.
2012-03-01 17:26:31 -06:00
system.hh
MEM: Add port proxies instead of non-structural ports
2012-01-17 12:55:08 -06:00
table_walker.cc
MEM: Move port creation to the memory object(s) construction
2012-02-24 11:43:53 -05:00
table_walker.hh
MEM: Move port creation to the memory object(s) construction
2012-02-24 11:43:53 -05:00
tlb.cc
Merge with head, hopefully the last time for this batch.
2012-01-31 22:40:08 -08:00
tlb.hh
Merge with head, hopefully the last time for this batch.
2012-01-31 22:40:08 -08:00
types.hh
cpus/isa: add a != operator for pcstate
2011-06-19 21:43:33 -04:00
utility.cc
MEM: Make port proxies use references rather than pointers
2012-02-24 11:45:30 -05:00
utility.hh
ARM: Further break up condition code into NZ, C, V bits.
2011-05-13 17:27:01 -05:00
vtophys.cc
MEM: Make port proxies use references rather than pointers
2012-02-24 11:45:30 -05:00
vtophys.hh
MEM: Clean-up of Functional/Virtual/TranslatingPort remnants
2012-01-30 03:44:25 -05:00